JPH06201504A - Manufacture of semiconductor dynamical amount sensor - Google Patents

Manufacture of semiconductor dynamical amount sensor

Info

Publication number
JPH06201504A
JPH06201504A JP5292083A JP29208393A JPH06201504A JP H06201504 A JPH06201504 A JP H06201504A JP 5292083 A JP5292083 A JP 5292083A JP 29208393 A JP29208393 A JP 29208393A JP H06201504 A JPH06201504 A JP H06201504A
Authority
JP
Japan
Prior art keywords
substrate
electrode
silicon substrate
layer
sensor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5292083A
Other languages
Japanese (ja)
Other versions
JP2519393B2 (en
Inventor
Hiroyuki Kaneko
洋之 金子
Toshiaki Shinohara
俊朗 篠原
Shigeo Hoshino
重夫 星野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP5292083A priority Critical patent/JP2519393B2/en
Publication of JPH06201504A publication Critical patent/JPH06201504A/en
Application granted granted Critical
Publication of JP2519393B2 publication Critical patent/JP2519393B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the cost and to make the quality common by manufacturing semiconductor sensors of the same characteristics by a batch processing. CONSTITUTION:A sensor cover 102 is prepared by forming a recession 24 in a substrate and by forming a P-type diffused region 21 for an upper electrode on the surface wherein the recession 24 is formed. A sensor main body 100 is prepared by forming a P-type diffused layer 13 for wiring and a P-type diffused layer 12 for a lower electrode separately in the surface of a substrate 11 and by forming an oxide film 14 selectively on the upper side of these layers. Next, the sensor cover 102 and the sensor main body 100 are opposed to each other and bonded by a polysilicon layer 17, and after bonding, chip split is conducted for each sensor as a unit. By this method, a manufacturing process is simplified and thus the cost can be reduced, while it is made possible, by using polysilicon, to make the adhesion strong and the quality common.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、コンデンサの静電容量
の変化によって力学量、例えば圧力を測定する半導体力
学量センサの製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor mechanical quantity sensor for measuring a mechanical quantity, for example, a pressure by changing a capacitance of a capacitor.

【0002】[0002]

【従来の技術】この種の圧力センサとして、例えば図4
に示すようなものが従来から知られている(特開昭58
−63826号公報)。図4において、圧力導入用のパ
イプ1と一体化した金属性ステム2上面には、貫通孔3
aを有するシリコン台座3が接着層4aを介して接着さ
れ、このシリコン台座3上面にはウエハから切り出され
たシリコンダイヤフラム5が接着層4bを介して固着さ
れる。シリコンダイヤフラム5の中央部には圧力により
撓む撓み部5aが形成され、この撓み部5aには、その
撓み量に相応した抵抗変化を得る半導体歪ゲ−ジ6が所
定箇所に設けられている。また、ステム2には、ハ−メ
チックシ−ル8により気密封止されかつ絶縁された状態
でリ−ドピン7が貫設され、歪ゲ−ジ6は、ボンディン
グワイヤ9,リ−ドピン7を介して図示せぬ外部回路と
接続されている。さらに、ステム2には、上部に通気孔
10aを有する金属性のキャップ10が放電加工,ハン
ダ等により接続され、真空槽内でこの通気孔10aをハ
ンダ11で封じることにより真空基準圧室12を得る。
以上のようにして、真空圧を基準圧力とする絶対型圧力
センサが作製される。
2. Description of the Related Art As a pressure sensor of this type, for example, FIG.
The one shown in FIG.
-63826). In FIG. 4, the through hole 3 is formed in the upper surface of the metallic stem 2 integrated with the pressure introducing pipe 1.
The silicon pedestal 3 having a is bonded via the adhesive layer 4a, and the silicon diaphragm 5 cut out from the wafer is fixed to the upper surface of the silicon pedestal 3 via the adhesive layer 4b. A bending portion 5a that bends due to pressure is formed in the central portion of the silicon diaphragm 5, and a semiconductor strain gauge 6 that provides a resistance change corresponding to the bending amount is provided at a predetermined position on the bending portion 5a. . Further, a lead pin 7 is provided through the stem 2 in a hermetically sealed and insulated state by a hermetic seal 8, and the strain gauge 6 is connected via a bonding wire 9 and a lead pin 7. Is connected to an external circuit (not shown). Further, a metal cap 10 having a vent hole 10a on the top is connected to the stem 2 by electric discharge machining, soldering, etc., and the vent hole 10a is sealed with a solder 11 in a vacuum chamber to form a vacuum reference pressure chamber 12. obtain.
As described above, the absolute pressure sensor having the vacuum pressure as the reference pressure is manufactured.

【0003】このような圧力センサにパイプ1を介して
圧力が導入されると、シリコンダイヤフラム5の撓み部
5aは上下の圧力差に応じて撓み、その撓み量に応じた
歪ゲ−ジ6の抵抗値変化がボンディングワイヤ9および
リードピン7を介して図示しない外部回路に電気信号と
して入力され、これにより圧力が測定される。
When pressure is introduced into such a pressure sensor through the pipe 1, the bending portion 5a of the silicon diaphragm 5 bends in accordance with the pressure difference between the upper and lower sides, and the strain gauge 6 corresponding to the amount of the bending bends. The change in resistance value is input as an electric signal to an external circuit (not shown) via the bonding wire 9 and the lead pin 7, whereby the pressure is measured.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上述の
圧力センサにあっては、半導体ウエハ上に形成したダイ
ヤフラム5をそれぞれチップ分割した後にカンパッケ−
ジ等を用いてチップ毎に真空実装している。すなわち、
チップ分割後、キャップ10に設けられた通気孔10a
を真空槽内においてハンダ等により封止して真空基準圧
室10を形成するため製造コストが高いという問題点が
ある。また、ダイヤフラム5はウエハをチップ分割して
作製するため品質を共通化できるのに対し、ダイヤフラ
ム5を真空実装して圧力センサを作製する際には、例え
ば圧力導入用のパイプ1の取り付け位置等に誤差が生じ
るため、作製した圧力センサの特性にばらつきが生じる
という問題点がある。
However, in the above-mentioned pressure sensor, the diaphragm 5 formed on the semiconductor wafer is divided into chips and then the package of the package is formed.
Each chip is vacuum-mounted using a die or the like. That is,
Vent hole 10a provided in cap 10 after chip division
There is a problem in that the manufacturing cost is high because the vacuum reference pressure chamber 10 is formed by sealing the inside of the vacuum chamber with solder or the like in the vacuum chamber. Further, since the diaphragm 5 is manufactured by dividing the wafer into chips, the quality can be made common. On the other hand, when manufacturing the pressure sensor by vacuum-mounting the diaphragm 5, for example, the mounting position of the pipe 1 for pressure introduction, etc. Therefore, there is a problem in that the characteristics of the manufactured pressure sensor vary.

【0005】本発明の目的は、同一特性の半導体センサ
をバッチ処理で作製してコスト低減と品質の共通化を図
った半導体力学量センサの製造方法を提供することにあ
る。
An object of the present invention is to provide a method for manufacturing a semiconductor dynamical quantity sensor in which cost reduction and quality standardization are achieved by manufacturing semiconductor sensors having the same characteristics by batch processing.

【0006】[0006]

【課題を解決するための手段】一実施例を示す図1,2
により説明すると、本発明は、第1のシリコン基板20
に複数の凹部24を形成し、各凹部24の内周面から周
縁にかけて第1の電極21を形成する工程と、第2のシ
リコン基板11の表面に、互いに絶縁された第2の電極
12と配線層13とを備えた領域を、第1のシリコン基
板20の凹部24と同一配置で形成し、各領域の上面に
絶縁層14を形成し、この絶縁層14に、配線層13と
接続するための第1の開口部14bおよび第2の開口部
14cと、第2の電極12と接続するための第3の開口
部14aとをそれぞれ設ける工程と、第1の開口部14
bに配線層13と接続される第1の配線部16を設ける
とともに、第3の開口部14aに第2の電極12と接続
される第2の配線部15を設ける工程と、凹部24の周
縁と略同形のポリシリコン層17を、その一部が第2の
開口部14cを介して配線層13と導通するように絶縁
層14上に形成する工程と、第1のシリコン基板20と
第2のシリコン基板11とを対向させ、凹部24の周縁
とポリシリコン層17とを所定の圧力雰囲気中で熱接着
する工程と、接着された第1のシリコン基板20と第2
のシリコン基板11とを、領域を単位として分割する工
程と、を備えることにより、上記目的は達成される。
[Means for Solving the Problems] FIGS.
The present invention will be described with reference to the first silicon substrate 20.
Forming a plurality of recesses 24 in each of the recesses 24 and forming the first electrode 21 from the inner peripheral surface to the peripheral edge of each recess 24; and forming the second electrodes 12 insulated from each other on the surface of the second silicon substrate 11. A region including the wiring layer 13 is formed in the same arrangement as the recess 24 of the first silicon substrate 20, an insulating layer 14 is formed on the upper surface of each region, and the insulating layer 14 is connected to the wiring layer 13. A first opening portion 14b and a second opening portion 14c for connecting the second electrode 12 and a third opening portion 14a for connecting to the second electrode 12, respectively;
a step of providing a first wiring part 16 connected to the wiring layer 13 in b and a second wiring part 15 connected to the second electrode 12 in the third opening 14a; Forming a polysilicon layer 17 having substantially the same shape as that on the insulating layer 14 so that a part of the polysilicon layer 17 is electrically connected to the wiring layer 13 through the second opening 14c; the first silicon substrate 20 and the second silicon substrate 20. Of the first recessed portion 24 and the polysilicon layer 17 are thermally bonded together in a predetermined pressure atmosphere, and the first silicon substrate 20 and the second bonded silicon substrate 11 are bonded together.
And the step of dividing the silicon substrate 11 of FIG.

【0007】[0007]

【作用】第1の電極21が形成された第1のシリコン基
板20と第2の電極12が形成された第2のシリコン基
板11とを対向させ、第1のシリコン基板20に形成さ
れた複数の凹部24と、第2のシリコン基板11に形成
された凹部24の周縁と略同形のポリシリコン層17と
を所定の圧力雰囲気中で熱接着した後、両シリコン基板
11,20をチップ単位で分割するようにしたため、分
割前に両シリコン基板11,20を所定の圧力雰囲気中
で熱接着して複数の半導体力学量センサを同時に作製で
き、従来不可欠であった真空実装作業が不要となり、製
造工程を極めて簡素化でき、低廉な半導体力学量センサ
が得られる。また、接着にポリシリコン層17を用いる
ため、接着力の強化や品質の共通化が図れる。
The first silicon substrate 20 on which the first electrode 21 is formed and the second silicon substrate 11 on which the second electrode 12 is formed are opposed to each other, and a plurality of silicon substrates formed on the first silicon substrate 20 are arranged. And the polysilicon layer 17 having substantially the same shape as the peripheral edge of the recess 24 formed in the second silicon substrate 11 are thermally bonded in a predetermined pressure atmosphere, and then both silicon substrates 11 and 20 are chip-by-chip unit. Since it is divided, a plurality of semiconductor dynamic quantity sensors can be simultaneously manufactured by thermally adhering both silicon substrates 11 and 20 in a predetermined pressure atmosphere before the division, and the vacuum mounting work which was conventionally indispensable becomes unnecessary. The process can be extremely simplified and an inexpensive semiconductor dynamic quantity sensor can be obtained. Further, since the polysilicon layer 17 is used for adhesion, it is possible to strengthen the adhesive force and standardize the quality.

【0008】なお、本発明の構成を説明する上記課題を
解決するための手段と作用の項では、本発明を分かり易
くするために実施例の図を用いたが、これにより本発明
が実施例に限定されるものではない。
Incidentally, in the section of means and action for solving the above-mentioned problems for explaining the constitution of the present invention, the drawings of the embodiments are used to make the present invention easy to understand. It is not limited to.

【0009】[0009]

【実施例】図1〜図3に基づいて本発明の一実施例を説
明する。図1に示すように、本発明に係る半導体圧力サ
ンサ100は、半導体基板から構成されるセンサ本体1
01と、その上面に接着され基準圧室RRを形成し半導
体基板から構成されるセンサカバ−102とを有し、セ
ンサ本体101の下部電極用P型拡散層12とカバ−本
体102の上部電極用P型拡散層21とが基準圧力室R
Rを挟んで対向しコンデンサを構成している。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, a semiconductor pressure sensor 100 according to the present invention includes a sensor body 1 including a semiconductor substrate.
01 and a sensor cover 102 that is bonded to the upper surface of the sensor cover 102 to form a reference pressure chamber RR and is composed of a semiconductor substrate. The P type diffusion layer 12 for the lower electrode of the sensor body 101 and the upper electrode of the cover body 102 are provided. The P-type diffusion layer 21 and the reference pressure chamber R
They face each other across R and form a capacitor.

【0010】センサ本体101は、N型シリコン基板1
1上に形成された下部電極用P型拡散層12および上部
電極用P型拡散層21の配線用P型拡散層13と、N形
シリコン基板11の表面に形成された酸化膜14とを有
する。下部電極用P型拡散層12の端部はコンタクトホ
−ル14aを介して配線15に接続され、配線用P型拡
散層13の端部もコンタクトホ−ル14bを介して配線
16に接続されている。これらの配線15,16はコン
デンサの信号線として用いられる。酸化膜14上にはポ
リシリコン層17を介してカバ−本体102が配設され
ている。
The sensor body 101 is an N type silicon substrate 1.
1, a wiring P-type diffusion layer 13 of the lower electrode P-type diffusion layer 12 and the upper electrode P-type diffusion layer 21, and an oxide film 14 formed on the surface of the N-type silicon substrate 11. . The end of the lower electrode P-type diffusion layer 12 is connected to the wiring 15 via the contact hole 14a, and the end of the wiring P-type diffusion layer 13 is also connected to the wiring 16 via the contact hole 14b. ing. These wirings 15 and 16 are used as signal lines for capacitors. A cover body 102 is provided on the oxide film 14 via a polysilicon layer 17.

【0011】カバ−本体102は、後述の如くN型半導
体基板に上部電極用P型拡散層21,埋込みP型拡散層
22,N型エピタキシャル層23,基準圧力室用凹部2
4を形成した後にN型半導体基板をエッチングで除去し
て成る。ここで、N型エピタキシャル層23が撓み部と
して機能する。その上部電極用P型拡散層21は、酸化
膜14のコンタクトホ−ル14cに設けられたポリシリ
コン17を介して配線用P型拡散層13に接続されてい
る。また、上部電極用P型拡散層21は、酸化膜14を
介して下部電極用P型拡散層12と絶縁されている。
The cover body 102 has an upper electrode P-type diffusion layer 21, a buried P-type diffusion layer 22, an N-type epitaxial layer 23, and a reference pressure chamber recess 2 on an N-type semiconductor substrate, as will be described later.
After forming 4, the N-type semiconductor substrate is removed by etching. Here, the N-type epitaxial layer 23 functions as a bending portion. The upper electrode P-type diffusion layer 21 is connected to the wiring P-type diffusion layer 13 via the polysilicon 17 provided in the contact hole 14c of the oxide film 14. The upper electrode P-type diffusion layer 21 is insulated from the lower electrode P-type diffusion layer 12 through the oxide film 14.

【0012】このような圧力センサ100を圧力雰囲気
中に配置すると、この雰囲気圧力と基準圧力室RR内の
基準圧力との圧力差に応じてカバ−本体102の撓み部
25が撓み、これにより上部電極用P型拡散層21と下
部電極用P型拡散層12との間の静電容量が変化する。
この静電容量変化を検出することにより雰囲気圧力が検
出される。すなわち、以上の構成の圧力センサ100
は、チップ分割する前に2枚の基板を真空中で接着して
作成することができ、従来不可欠であった各チップ毎の
真空実装作業が不要となり、製造工程を極めて簡素化で
き、低廉な半導体力学量センサが得られる。
When such a pressure sensor 100 is arranged in a pressure atmosphere, the bending portion 25 of the cover body 102 bends in accordance with the pressure difference between this atmosphere pressure and the reference pressure in the reference pressure chamber RR, and as a result, the upper portion The electrostatic capacitance between the electrode P-type diffusion layer 21 and the lower electrode P-type diffusion layer 12 changes.
The atmospheric pressure is detected by detecting this change in capacitance. That is, the pressure sensor 100 having the above configuration
Can be made by bonding two substrates together in a vacuum before chip division, eliminating the need for vacuum mounting work for each chip, which was indispensable in the past, and greatly simplifying the manufacturing process and making it inexpensive. A semiconductor dynamic quantity sensor is obtained.

【0013】次に、図2,3によりこの半導体力学量セ
ンサの製造工程について説明する。なお、図2,3で
は、半導体圧力センサ1個分の構造を示すが、実際には
図2,3の構造の半導体圧力センサが半導体基板上に複
数形成されている。 (a) 図2(a)に示すように、P型拡散層22が埋
め込まれN型エピタキシャル層23が形成されたカバ−
本体用基板20(例えば面方位(100)のN型シリコ
ン基板から成る)の下面全体に熱酸化あるいはCVD等
により酸化膜31を形成し、次いで両端の酸化膜31を
フォトエッチング等により除去する。 (b) 図2(b)に示すように、酸化膜31をマスク
としてヒドラジン等の異方性エッチング溶液により異方
性エッチングを行ない、基板20の両端下部を所定深さ
まで除去し、凸部20aを形成する。 (c) 凸部20a下面の酸化膜31を除去した後、再
び基板20の下面全体に酸化膜32を上述の方法により
形成し、フォトエッチングにより凸部20a中央の酸化
膜32を除去する(図2(c))。 (d) 図2(d)に示すように、酸化膜32をマスク
としてヒドラジン等の異方性エッチング液により基板2
0の凸部20a中央を所定深さまで除去して凹部20b
(24)を形成する。この凹部20bが基準圧力室RR
を形成する。 (e) ボロンの熱拡散あるいはイオン注入とアニ−ル
等により上部電極用P型拡散層21を凸部20aの下面
全体に形成する(図2(e))。
Next, the manufacturing process of this semiconductor dynamical quantity sensor will be described with reference to FIGS. Although FIGS. 2 and 3 show the structure of one semiconductor pressure sensor, a plurality of semiconductor pressure sensors having the structures of FIGS. 2 and 3 are actually formed on the semiconductor substrate. (A) As shown in FIG. 2A, a cover in which a P-type diffusion layer 22 is embedded and an N-type epitaxial layer 23 is formed.
An oxide film 31 is formed on the entire lower surface of the main body substrate 20 (made of, for example, an N-type silicon substrate having a plane orientation (100)) by thermal oxidation or CVD, and then the oxide films 31 at both ends are removed by photoetching or the like. (B) As shown in FIG. 2B, anisotropic etching is performed with an anisotropic etching solution such as hydrazine using the oxide film 31 as a mask, and the lower portions of both ends of the substrate 20 are removed to a predetermined depth. To form. (C) After removing the oxide film 31 on the lower surface of the convex portion 20a, the oxide film 32 is formed again on the entire lower surface of the substrate 20 by the above method, and the oxide film 32 at the center of the convex portion 20a is removed by photoetching (see FIG. 2 (c)). (D) As shown in FIG. 2D, the substrate 2 is etched with an anisotropic etching solution such as hydrazine using the oxide film 32 as a mask.
The center of the convex portion 20a of 0 is removed to a predetermined depth to form the concave portion 20b.
(24) is formed. This recess 20b is the reference pressure chamber RR.
To form. (E) The P-type diffusion layer 21 for the upper electrode is formed on the entire lower surface of the protrusion 20a by thermal diffusion of boron or ion implantation and annealing (FIG. 2 (e)).

【0014】(f) 図3(a)に示すように、例えば
面方位(100)のN型シリコンから成る別の基板11
の上部表面にボロンの熱拡散あるいはイオン注入とアニ
−ル等により下部電極用P型拡散層12および配線用P
型拡散層13を選択的に形成する。 (g) 図3(b)に示すように、基板11の上部表面
全体に酸化膜14を形成した後、上部電極接続用のコン
タクトホール領域14b,14cと下部電極接続用のコ
ンタクトホール領域14aの酸化膜をフォトエッチング
により除去する。
(F) As shown in FIG. 3A, another substrate 11 made of N-type silicon having a plane orientation (100), for example.
The lower electrode P-type diffusion layer 12 and the wiring P are formed on the upper surface of the substrate by thermal diffusion of boron or ion implantation and annealing.
The type diffusion layer 13 is selectively formed. (G) As shown in FIG. 3B, after forming the oxide film 14 on the entire upper surface of the substrate 11, contact hole regions 14b and 14c for connecting upper electrodes and a contact hole region 14a for connecting lower electrodes are formed. The oxide film is removed by photoetching.

【0015】(h) 図3(c)に示すように、凹部2
0bの周縁と略同形のポリシリコン層17を、コンタク
トホール領域14cに形成して配線用P型拡散層13と
接続するとともに、酸化膜14上に形成して下部電極用
P型拡散層12と絶縁させる。また、コンタクトホール
領域14a,14bにそれぞれ配線15,16を形成す
る。次に、基板20,11をともに親水処理を施した
後、基板11と基板20とを対向させ、基板11のポリ
シリコン層17と基板20の凹部20bの周縁とを、清
浄な環境の所定の圧力下において密着させ加熱する。こ
れにより、基板20と基板11が接着され、凹部20b
で基準圧力室RRが形成される。上述した所定の圧力が
この基準圧力室RR内の基準圧力となり、この圧力は予
め適切な値に設定される。また、加熱時の温度も、例え
ば密着強度等を考慮して予め適切な値に設定される。
(H) As shown in FIG. 3 (c), the recess 2
A polysilicon layer 17 having substantially the same shape as the peripheral edge of 0b is formed in the contact hole region 14c and connected to the wiring P-type diffusion layer 13, and is formed on the oxide film 14 to form the lower electrode P-type diffusion layer 12. Insulate. Further, wirings 15 and 16 are formed in the contact hole regions 14a and 14b, respectively. Next, after the substrates 20 and 11 are both subjected to hydrophilic treatment, the substrate 11 and the substrate 20 are opposed to each other, and the polysilicon layer 17 of the substrate 11 and the peripheral edge of the recess 20b of the substrate 20 are provided in a predetermined clean environment. Contact and heat under pressure. As a result, the substrate 20 and the substrate 11 are adhered, and the recess 20b is formed.
Thus, the reference pressure chamber RR is formed. The above-mentioned predetermined pressure becomes the reference pressure in the reference pressure chamber RR, and this pressure is set to an appropriate value in advance. Further, the temperature at the time of heating is also set in advance to an appropriate value in consideration of adhesion strength and the like.

【0016】(i) 図3(d)に示すように、基板2
0をエッチングしてP型拡散層21,22で囲まれてい
る領域以外を除去してカバ−本体102を形成する。こ
のP型拡散層21,22により過度のエッチングが防止
されるのでカバ−本体102の形状を均一化でき、安定
したセンサ特性を持つ圧力センサが得られる。 (j) 最後に、対向密着された両半導体基板を、図3
(d)に示す半導体圧力センサを単位としてチップ分割
する。
(I) As shown in FIG. 3 (d), the substrate 2
0 is etched to remove the regions other than the regions surrounded by the P-type diffusion layers 21 and 22 to form the cover body 102. Since the P-type diffusion layers 21 and 22 prevent excessive etching, the shape of the cover body 102 can be made uniform, and a pressure sensor having stable sensor characteristics can be obtained. (J) Finally, as shown in FIG.
The semiconductor pressure sensor shown in (d) is divided into chips.

【0017】上記製造工程において、各基板11,20
同士の接着に用いるポリシリコンは、各基板11,20
の材質であるシリコンと接着性がよく、加熱することに
より強力な接着力が得られる。また、ポリシリコン層1
7の形成は蒸着等によって行われ、その厚さは任意に制
御できるため、上部電極用P型拡散層21と下部電極用
P型拡散層12との間隔を各圧力センサで共通にするこ
とができる。さらに、ポリシリコンは導電性に優れるた
め、上部電極用P型拡散層21と配線用P型拡散層22
とをほぼ同電位にすることができる。上記のようなポリ
シリコンの特徴により、半導体基板上に図1の構造の圧
力センサを複数作製した後チップ分割して得られるそれ
ぞれの圧力センサの特性は均一になる。また、本発明の
製造方法によれば、基板11の表面に下部電極用の配線
15と上部電極用の配線16の双方を設けることができ
るため、ボンディング等を行いやすくなる。
In the above manufacturing process, each substrate 11, 20
The polysilicon used to bond the substrates together is the substrate 11, 20.
It has good adhesiveness to silicon, which is the material of, and a strong adhesive force can be obtained by heating. Also, the polysilicon layer 1
7 is formed by vapor deposition or the like, and its thickness can be arbitrarily controlled. Therefore, the distance between the upper electrode P-type diffusion layer 21 and the lower electrode P-type diffusion layer 12 can be made common to each pressure sensor. it can. Further, since polysilicon has excellent conductivity, the P-type diffusion layer 21 for the upper electrode and the P-type diffusion layer 22 for the wiring are formed.
And can be made to have substantially the same potential. Due to the characteristics of polysilicon as described above, the characteristics of each pressure sensor obtained by dividing a chip after manufacturing a plurality of pressure sensors having the structure of FIG. 1 on a semiconductor substrate become uniform. Further, according to the manufacturing method of the present invention, both the wiring 15 for the lower electrode and the wiring 16 for the upper electrode can be provided on the surface of the substrate 11, so that bonding or the like becomes easy.

【0018】なお、凸部20aと基板11との接着前
に、エッチングあるいは機械研磨等により基板20を機
械強度の保たれる範囲で薄膜化しておいてもよい。
Before the protrusion 20a and the substrate 11 are bonded together, the substrate 20 may be thinned by etching, mechanical polishing or the like within a range where mechanical strength is maintained.

【0019】上記実施例の製造方法に作製した半導体力
学量センサは上述した圧力センサとして用いることがで
きる他、加速度を検出する加速度センサとしても用いる
ことができる。
The semiconductor mechanical quantity sensor manufactured by the manufacturing method of the above embodiment can be used not only as the pressure sensor described above but also as an acceleration sensor for detecting acceleration.

【0020】このように構成された実施例にあっては、
基板20が第1のシリコン基板に、凹部24が凹部に、
上部電極用P型拡散層21が第1の電極に、基板11が
第2のシリコン基板に、下部電極用P型拡散層12が第
2の電極に、配線用P型拡散層13が配線層に、酸化膜
14が絶縁層に、コンタクトホール14bが第1の開口
部に、コンタクトホール14cが第2の開口部に、コン
タクトホール14aが第3の開口部に、配線16が第1
の配線部に、配線15が第2の配線部に、ポリシリコン
層17がポリシリコン層に、それぞれ対応する。
In the embodiment constructed as described above,
The substrate 20 is the first silicon substrate, the recess 24 is the recess,
The upper electrode P-type diffusion layer 21 is the first electrode, the substrate 11 is the second silicon substrate, the lower electrode P-type diffusion layer 12 is the second electrode, and the wiring P-type diffusion layer 13 is the wiring layer. First, the oxide film 14 serves as an insulating layer, the contact hole 14b serves as the first opening, the contact hole 14c serves as the second opening, the contact hole 14a serves as the third opening, and the wiring 16 serves as the first opening.
, The wiring 15 corresponds to the second wiring portion, and the polysilicon layer 17 corresponds to the polysilicon layer.

【0021】[0021]

【発明の効果】本発明によれば、第1の電極が形成され
た第1のシリコン基板と第2の電極が形成された第2の
シリコン基板とを対向させて所定の圧力雰囲気中で互い
に接合して複数の半導体力学量センサを同時に作製する
ようにしたため、チップ分割する前に両基板を例えば真
空中で接着して作成することができ、従来不可欠であっ
たチップごとの真空実装が不要となり、製造工程を極め
て簡素化でき、低廉な半導体力学量センサを提供でき
る。また、ポリシリコン層によって両シリコン基板を接
着するようにしたため、強力な接着力が得られる。さら
に、ポリシリコン層の厚さは任意に制御できるため、両
シリコン基板の間隔を各半導体力学量センサで共通にす
ることができる。さらにまた、ポリシリコン層は導電性
に優れるため、第1の電極と第2の電極の各電圧を正確
に検出でき、センサの検出精度が向上するとともに、第
2のシリコン基板表面に第1および第2の電極の取り出
しのための第1の配線部および第2の配線部を形成する
ことができるため、ボンディング等を行いやすくなる。
According to the present invention, the first silicon substrate on which the first electrode is formed and the second silicon substrate on which the second electrode is formed are opposed to each other in a predetermined pressure atmosphere. Since two or more semiconductor dynamic quantity sensors are bonded at the same time, it is possible to bond both substrates in a vacuum before dividing them into chips, which eliminates the need for vacuum mounting for each chip, which was indispensable in the past. Thus, the manufacturing process can be extremely simplified, and an inexpensive semiconductor dynamic quantity sensor can be provided. Moreover, since both silicon substrates are adhered by the polysilicon layer, a strong adhesive force can be obtained. Furthermore, since the thickness of the polysilicon layer can be controlled arbitrarily, the distance between both silicon substrates can be made common to each semiconductor dynamical quantity sensor. Furthermore, since the polysilicon layer has excellent conductivity, the voltages of the first electrode and the second electrode can be accurately detected, the detection accuracy of the sensor is improved, and the first and second electrodes are formed on the surface of the second silicon substrate. Since the first wiring portion and the second wiring portion for taking out the second electrode can be formed, bonding and the like can be easily performed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による半導体力学量センサの製造方法に
より作製した半導体力学量センサの断面図である。
FIG. 1 is a cross-sectional view of a semiconductor dynamic quantity sensor manufactured by a method for manufacturing a semiconductor dynamic quantity sensor according to the present invention.

【図2】図1に示す半導体力学量センサの製造工程を順
を追って説明する図である。
2A to 2C are views for sequentially explaining a manufacturing process of the semiconductor dynamical amount sensor shown in FIG.

【図3】図2に続く製造工程を順を追って説明する図で
ある。
FIG. 3 is a diagram for sequentially explaining the manufacturing process subsequent to FIG.

【図4】従来の半導体圧力センサの断面図である。FIG. 4 is a sectional view of a conventional semiconductor pressure sensor.

【符号の説明】[Explanation of symbols]

11 N型半導体基板 12下部電極用P型拡散層 13 配線用P型拡散層 14酸化膜 14a〜14c コンタクトホ−ル 15,16 配線 17 ポリシリコン層 21 上部電極用P型拡散層 22 埋め込みP型拡散層 24 凹部 25 撓み部 101 センサ本体 102 センサカバ− RR 基準圧力室 11 N-type semiconductor substrate 12 P-type diffusion layer for lower electrode 13 P-type diffusion layer for wiring 14 Oxide film 14a to 14c Contact holes 15, 16 Wiring 17 Polysilicon layer 21 P-type diffusion layer for upper electrode 22 Embedded P-type Diffusion layer 24 Recessed portion 25 Bent portion 101 Sensor body 102 Sensor cover RR Reference pressure chamber

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 第1のシリコン基板に複数の凹部を形成
し、各凹部の内周面から周縁にかけて第1の電極を形成
する工程と、 第2のシリコン基板の表面に、互いに絶縁された第2の
電極と配線層とを備えた領域を、前記第1のシリコン基
板の凹部と同一配置で形成し、各領域の上面に絶縁層を
形成し、この絶縁層に、前記配線層と接続するための第
1の開口部および第2の開口部と、前記第2の電極と接
続するための第3の開口部とをそれぞれ設ける工程と、 前記第1の開口部に前記配線層と接続される第1の配線
部を設けるとともに、前記第3の開口部に前記第2の電
極と接続される第2の配線部を設ける工程と、 前記凹部の周縁と略同形のポリシリコン層を、その一部
が前記第2の開口部を介して前記配線層と導通するよう
に前記絶縁層上に形成する工程と、 前記第1のシリコン基板と前記第2のシリコン基板とを
対向させ、前記凹部の周縁と前記ポリシリコン層とを所
定の圧力雰囲気中で熱接着する工程と、 接着された前記第1のシリコン基板と前記第2のシリコ
ン基板とを、前記領域を単位として分割する工程と、を
備えることを特徴とする半導体力学量センサの製造方
法。
1. A step of forming a plurality of recesses in a first silicon substrate and forming a first electrode from an inner peripheral surface to a peripheral edge of each recess, and a surface of the second silicon substrate insulated from each other. A region including a second electrode and a wiring layer is formed in the same arrangement as the recess of the first silicon substrate, an insulating layer is formed on the upper surface of each region, and the insulating layer is connected to the wiring layer. A first opening and a second opening for connecting the second electrode and a third opening for connecting to the second electrode, and connecting the wiring layer to the first opening. And a second wiring part connected to the second electrode in the third opening, and a polysilicon layer having substantially the same shape as the peripheral edge of the recess, The insulating layer is formed so that a part thereof is electrically connected to the wiring layer through the second opening. A step of forming the first silicon substrate and a step of causing the first silicon substrate and the second silicon substrate to face each other, and thermally bonding the peripheral edge of the recess and the polysilicon layer in a predetermined pressure atmosphere; And a step of dividing the first silicon substrate and the second silicon substrate in units of the region.
JP5292083A 1993-11-22 1993-11-22 Method for manufacturing semiconductor dynamic quantity sensor Expired - Fee Related JP2519393B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5292083A JP2519393B2 (en) 1993-11-22 1993-11-22 Method for manufacturing semiconductor dynamic quantity sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5292083A JP2519393B2 (en) 1993-11-22 1993-11-22 Method for manufacturing semiconductor dynamic quantity sensor

Publications (2)

Publication Number Publication Date
JPH06201504A true JPH06201504A (en) 1994-07-19
JP2519393B2 JP2519393B2 (en) 1996-07-31

Family

ID=17777330

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2519393B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007010553A (en) * 2005-07-01 2007-01-18 Alps Electric Co Ltd Capacitive pressure sensor element
JP2010032220A (en) * 2008-07-24 2010-02-12 Panasonic Electric Works Co Ltd Electrode removing structure for semiconductor device
WO2012164975A1 (en) * 2011-06-03 2012-12-06 アルプス電気株式会社 Capacitive pressure sensor and method for manufacturing same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5710270A (en) * 1980-06-20 1982-01-19 Hitachi Ltd Semiconductor capacitor type pressure sensor
JPS5764978A (en) * 1980-10-03 1982-04-20 Ibm Capacitive pressure transducer
JPS57134805A (en) * 1981-02-13 1982-08-20 Hitachi Ltd Method of connecting insulating material
JPS62500545A (en) * 1984-10-12 1987-03-05 ロ−ズマウント インコ. Pressure sensing cell using brittle diaphragm

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5710270A (en) * 1980-06-20 1982-01-19 Hitachi Ltd Semiconductor capacitor type pressure sensor
JPS5764978A (en) * 1980-10-03 1982-04-20 Ibm Capacitive pressure transducer
JPS57134805A (en) * 1981-02-13 1982-08-20 Hitachi Ltd Method of connecting insulating material
JPS62500545A (en) * 1984-10-12 1987-03-05 ロ−ズマウント インコ. Pressure sensing cell using brittle diaphragm

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007010553A (en) * 2005-07-01 2007-01-18 Alps Electric Co Ltd Capacitive pressure sensor element
JP2010032220A (en) * 2008-07-24 2010-02-12 Panasonic Electric Works Co Ltd Electrode removing structure for semiconductor device
WO2012164975A1 (en) * 2011-06-03 2012-12-06 アルプス電気株式会社 Capacitive pressure sensor and method for manufacturing same
JPWO2012164975A1 (en) * 2011-06-03 2015-02-23 アルプス電気株式会社 Capacitance type pressure sensor and manufacturing method thereof

Also Published As

Publication number Publication date
JP2519393B2 (en) 1996-07-31

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