JPH0619829A - Automatic address allocation system for input/output device - Google Patents

Abstract

PURPOSE:To automatically allocate the address of an input/output device at high speed or at low speed in an information processor by which inputted data through the input/output device is processed at high speed or low speed. CONSTITUTION:The respective addresses of the input/output device 3 are stored in a main input/output allocation memory 9a in order from the head of unit. It is checked in which input/output registers of high speed/low speed user programs 7a and 7b, and high speed/low speed tag information 8a and 8b the respective addresses stored in the main input/output allocation memory are set, the addresses which are set in the input/output registers of the high speed user program and the high speed tag information among the addresses of the main input/output alocation memory are registered in a high speed operation allocation table 9b and the addresses which are set in the input/output registers of the low speed user program and the low speed tag information are registered in a low speed operation allocation table 9c.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for processing various data input / output through an input / output device at high speed or low speed, and automatically addresses each address of the input / output device at high speed or The present invention relates to an automatic address assignment system for I / O devices that are assigned at low speed.

[0002]

2. Description of the Related Art For example, in a process control device for controlling various devices in a large-scale factory with a computer, a large number of process data from various detectors are input to one input / output device, and each device is also processed. A large number of operation data are output for. Then, in this process control device, various control calculations are executed on various data input through the input / output device, and each manipulated variable is calculated and sent to each controlled object.

In this case, depending on the type of the input data, there are cases where it is necessary to perform the calculation at a short cycle, that is, high speed, and there are cases where the calculation may be performed at a long cycle, that is, at a relatively low speed. Then, a high-speed user program and a low-speed user program are stored in the storage device. Further, high speed or low speed tag information for processing various data is also set. In each of the high-speed and low-speed user programs, the address used by the own program is stored in its own input / output register.

When a new input / output device is connected to the process control device in which the high-speed / low-speed program and the high-speed / low-speed tag information are set, each input / output device to / from which various data is input / output from the outside It is necessary to set in advance in the allocation table whether the address is for high speed processing or for low speed processing.

In this case, the user or service person sequentially decodes each high-speed / low-speed user program and tag information set in the process control device, and each address of the input / output device is processed at high speed. It is necessary to determine whether the address is the address of the data to be processed or the address of the data that may be processed at low speed, and set it in the allocation table by, for example, a manual operation.

[0006]

However, as described above, the user or service person of the apparatus sequentially decodes the low-speed and high-speed user programs which have already been set, and the respective addresses of the input / output device become high-speed. It is very complicated to determine which of the speed levels for high speed and low speed is the address of the data to be processed and to sequentially allocate the addresses to the allocation table. Therefore, the work efficiency of the assignment work of the input / output device is significantly reduced.

Further, since the allocation work is carried out artificially, setting mistakes are likely to occur. Further, there is a problem that only a worker who is familiar with the contents of the user program can carry out this address assignment work.

Further, even when the configuration of the input / output device, the change of the address, and the change of each user program occur, it is necessary to carry out the work of setting each address of the input / output device in the allocation table by the procedure described above. is there.

The present invention has been made in view of such circumstances, and by searching the input / output register of each user program, the user or service person is not aware of the high speed or low speed of each address, Each address of the input / output device can be automatically assigned to the assignment table, the work efficiency of the assignment work can be greatly improved, and the occurrence of the assignment error can be prevented, and the reliability of the entire device can be improved. The purpose is to provide the automatic address allocation method of.

[0010]

In order to solve the above problems, the present invention has user programs for performing data processing at high speed and low speed, and high speed and low speed tag information, and uses an input / output device. In the automatic address assignment method of the input / output device in the information processing device that processes the various data input / output by the user program assigned to the operation assignment table,

Address storage means for storing each address of the input / output device in the main input / output allocation memory in order from the head of the unit and each address stored in the main input / output allocation memory in response to the allocation command input The address search means for checking which user program and tag information input / output register is set, and the address set in the high speed user program and high speed tag information input / output register among the main input / output allocation memory addresses Address registration means for registering in the high speed operation allocation table and for registering the addresses set in the input / output registers for the low speed user program and the low speed tag information in the low speed operation allocation table.

[0012]

According to the automatic address assignment system of the input / output device thus constructed, each address of the input / output device is temporarily stored in the main input / output assignment memory. Then, the respective addresses stored in the main input / output allocation memory are sequentially read to automatically determine which of the high speed user program and the low speed user program corresponds. Then, each address of the input / output device is automatically set in the high speed operation allocation table or the low speed operation allocation table according to the determination result.

Therefore, the user or service person
Each address of the input / output device can be automatically assigned to the assignment table without being aware of the high speed or low speed of each address.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a process control device as an information processing device to which the address automatic allocation system of the input / output device of the embodiment is applied.

A processor (MPU) 2 for executing various arithmetic processes and various process data are input from a controlled equipment and a manipulated variable is sent to a bus line 1 composed of an address bus, a data bus and a control bus. Interface 4 to which the input / output device 3 is connected, an input / output device configuration memory 5 for storing the configuration of the input / output device 3,
Control program memory 6 for storing control program 6a
Etc. are connected.

Further, on the bus line 1, a high-speed user program 7a for executing high-speed control arithmetic processing on various data input via the input / output device 3 and a low-speed control arithmetic processing are executed. The user program memory 7 storing the low-speed user program 7b, the tag information memory 8 storing the high-speed tag information 8a used in the high-speed tag processing and the low-speed tag information 8b used in the low-speed tag processing, and the entire address of the input / output device 3 Main input / output allocation memory 9a for storing and high-speed operation allocation table 9b
An allocation memory 9 for storing the low-speed operation allocation table 9c and the like are connected.

When the input / output device 3 is newly connected to the interface 4, each user program 7a, 7
When b or each tag information 8a, 8b is changed, when an operation command is input from a keyboard or an operation panel (not shown), the processor 2 executes a predetermined address allocation process according to the control program 6a.

That is, when the allocation command is input, each address of the input device is sequentially read from the head of the unit and temporarily stored in the main input / output allocation memory 9a of the allocation memory 9. Therefore, at this point, the input / output device 3
It is unclear whether each of the addresses is for high-speed processing or for low-speed processing.

When all the addresses in the input / output device 3 are stored in the main input / output allocation memory 9a, the input / output allocation processing shown in FIG. 2 is started. When the input / output device allocation process is started in step F1, first, one address stored in the main input / output allocation memory 9a is read (F2). Next, the high-speed tag information 8a in the tag information memory 8
The address of the input / output register of the one piece of high-speed tag information 8a set to is read (F3). Then, it is checked whether or not the address read from the main input / output allocation memory 9a matches the address of the input / output register (F4). If they match, the address read from the main input / output allocation memory 9a is the address of the data to be subjected to the high-speed tag processing, so this address is registered in the high-speed operation allocation table 9b (F10).

If they do not match, the address of the input / output register of the other high-speed tag information 8a is read to check whether it matches the address previously read from the main input / output allocation memory 9a (F4). If the addresses of all the high-speed tag information 8a set in the tag information memory 8 do not match (F5), the process proceeds to F6, and the address of one input / output register of the high-speed user program 7a in the user program memory 7 is reached. Read out.

Then, first, the main input / output allocation memory 9a
Check whether it matches the address read from (F
7). If they match, the address read from the main input / output allocation memory 9a is the address of the data to be processed by this high-speed user program.
This address is registered in the high speed operation allocation table 9b (F10).

If they do not match, the high-speed user program 7
Read the address of the other input / output register in a,
It is checked whether or not it matches the address previously read from the main input / output allocation memory 9a (F7). If the addresses do not match the respective addresses set in all the input / output registers of the high speed user program 7a (F8), the data of the address read from the main input / output allocation memory 9a first does not need to be processed at high speed. It can be judged as data. Therefore, this address is registered in the low speed operation allocation table 9c.

High-speed operation allocation table 9b for one address stored in the main input / output allocation memory 9a
Alternatively, when the allocation processing for the low-speed operation allocation table 9c is completed, the process proceeds to F11, and if there is an unallocated address in the main input / output allocation memory 9a, F2 is executed.
Return to and read the next address.

High-speed operation allocation table 9b for all addresses stored in the main input / output allocation memory 9a
Alternatively, when the allocation process for the low-speed operation allocation table 9c ends, this flow chart is ended (F12).

When the allocation processing for all the addresses of the input / output device 3 is completed in this way, the process control device according to each user program 7a, 7b outputs each data input / output from the input / output device 3 to the controlled object. The control calculation process for is executed.

Specifically, as shown in FIG. 3, each data input via each address of the input / output device 3 is subjected to the batch input / output processing S1 and the high speed operation allocation table 9b.
Alternatively, according to the set address of the low-speed operation allocation table 9b, the high-speed operation and the low-speed operation are discriminated, and are collectively stored in the collective input / output register 10 formed of a large number of input / output registers formed in each user program 7a, 7b. .

Then, in the linearization processing S2, the linearization processing is executed for each data stored in the batch input / output register 10 at a speed designated by the tag information of the corresponding data.

Further, in the user program processing S3, each data stored in the batch input / output register 10 is extracted by using each user program 7a, 7b, and the control calculation processing is performed at the speed designated by each data. To execute. The calculation result in the user program processing S3 is sent to the input / output device 3 via the collective input / output processing S1.

According to the address automatic allocation system of the input / output device configured as described above, when the input / output device 3 is newly connected to the interface 4 or each user program 7
When a, 7b or each tag information 8a, 8b is changed,
When the operator inputs an allocation command from a keyboard or an operation panel (not shown), whether each address of the input / output device 3 is a data for which the data at the corresponding address should be automatically processed at high speed, or whether the data can be processed at low speed. Is automatically determined using the high speed / low speed user programs 7a, 7b and the high speed / low speed tag information 8a, 8b, and set in the high speed operation allocation table 9a or the low speed operation allocation table 9b.

Therefore, as in the conventional apparatus, the user or service person sequentially decodes the low-speed and high-speed user programs, and each address of the input / output device corresponds to either high-speed or low-speed data. There is no need to check if it is an address. Therefore, the work efficiency of the address assignment work of the input / output device can be greatly improved. In addition, it is possible to prevent artificial setting errors.

[0031]

As described above, according to the address automatic allocation system of the I / O device of the present invention, the I / O register of each high-speed / low-speed user program is searched by each address of the I / O device, High speed / low speed for the address is determined. Therefore, the user or service person can automatically assign each address of the input / output device to the assignment table without being aware of the high speed or low speed of each address, and the work efficiency of the assignment work can be significantly improved. The occurrence of allocation errors can be prevented and the reliability of the entire device can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a process control device adopting an automatic address assignment system for an input / output device according to an embodiment of the present invention;

FIG. 2 is a flow chart showing the operation of the system of the embodiment,

FIG. 3 is a schematic diagram showing a data processing operation of the entire process control device.

[Explanation of symbols]

1 ... system bus, 2 ... processor, 3 ... input / output device,
6a ... Control program, 7a ... High-speed user program,
7b ... low speed user program, 8a ... high speed tag information, 8
b ... low speed tag information, 9a ... main input / output allocation memory, 9
b ... High speed operation allocation table, 9c ... Low speed operation allocation table.

Claims (1)

[Claims] 1. A user program for performing data processing at high speed and low speed, and tag information for high speed and low speed, and various data input / output through an input / output device are assigned to an operation assignment table. In the automatic address assigning method of the input / output device in the information processing device that processes data by either one of the user programs, an address storage means for storing each address of the input / output device in the main input / output assigning memory in order from the head of the unit. ,
Address search means for checking which user program and tag information input / output register each address stored in the main input / output allocation memory is responsive to an allocation command input, and the main input / output. Register the addresses that were set in the high-speed user program and high-speed tag information I / O registers in the high-speed operation allocation table among the addresses in the allocation memory, and change the addresses that were set in the low-speed user program and low-speed tag information I / O registers. An automatic address assignment system for input / output devices equipped with address registration means for registering in the low-speed operation assignment table.