JPH0619757B2 - Microcomputer data transfer synchronization method - Google Patents

Description

Description: (a) Technical Field The present invention includes a CPU, a DMAC (direct memory access controller), a dynamic RAM (hereinafter simply referred to as a memory), and an I / O device, and performs data transfer in a CPU mode or a DMA mode. The present invention relates to a data transfer synchronization method when executing a CPU mode or a DMA mode in a microcomputer configured to perform any of the modes.

(b) Prior art and its drawbacks A data transfer mode of a microcomputer in which a CPU and a DMAC coexist as processors and each shares an address bus is either a CPU or a memory or an I / O.
CPU mode for data transfer between devices and DMA for data transfer between memory and I / O device without CPU
It is divided into mode and. Of these, in the CPU mode, the address of the I / O device or memory to be accessed is directly specified by the CPU, so the specified I / O device or memory is C-dependent according to the length of its own access time.
A wait signal is generated to put the PU into a wait state, whereby synchronization with the CPU can be achieved. On the other hand, in the DMA mode, the memory address is output from the DMAC, but the I / O address is not output, so that the access time of the I / O device is shortened depending on the type of the I / O device to be accessed. Therefore, different wait times must be generated accordingly. When using dynamic RAM as memory,
Memory control must be performed in synchronization with the wait time. Therefore, conventionally, as shown in FIG. 1, the weight control circuit 1 for executing the CPU mode and the weight control circuit 2 for executing the DMA mode are separately assigned to the respective I / O devices, and the CPU mode is set. At the time of execution, the READY signal (weight signal) formed by the wait control circuit 1 is given from the gate 3 to the CPU, and at the time of executing the DMA mode of I / O read and memory write, the wait control circuit 2 sends the READY signal to the DMAC. I was trying to give.

However, in the above method, since it is necessary to assign two types of weight control circuits to each I / O device,
When the circuit becomes complicated and a new I / O device is to be retrofitted, it is necessary to add two types of weight control circuits and peripheral gate circuits accordingly.

(c) Object of the Invention The object of the present invention is to use the wait control circuit between the CPU and the memory in the CPU mode in the DMA mode in which the memory data is transferred from the I / O device side.
Memory control in MA mode is simplified and each I / O
The weight control circuit assigned to the device is simplified,
Another object of the present invention is to provide a data transfer synchronization method for a microcomputer, which allows I / O devices having different access speeds to be easily retrofitted.

(d) Structure and Effect of the Invention In summary, when executing the CPU mode, the wait signal is formed by the CPU mode wait time individually assigned to the memory or the I / O device as in the conventional case. When executing the DMA mode in which memory transfer is performed from the I / O device side, a data set time required to complete the data set of the input data is generated in the I / O device to be accessed.
The weight signal is added to the mode wait time to form a wait signal.

(e) Embodiment FIG. 2 is a conceptual block diagram of a microcomputer for carrying out the data transfer synchronization method of the present invention. In the figure, a weight control circuit 4 is a weight control circuit for forming a CPU mode weight signal of the memory 5. The weight control circuit 1 is a circuit for forming a CPU mode weight signal of the I / O device 6 as in the case of FIG. The configuration is different from that of FIG. 1 in that a weight control circuit for forming a DMA mode wait signal is not assigned to each I / O device, and that when the DMA mode is executed, the I / O device 6 is not affected by the DISK or the like. The point is that when the data set of the input data is completed, the DSET signal is output to the start terminal of the wait control circuit 4 which forms the CPU mode wait signal of the memory 5. To form the DSET signal in the I / O device 6, for example, a sist register or the like is used. With this configuration, D
When the MA mode is executed, the weight control circuit 4 is I
Since it will be activated at the time of data setup in the I / O device 6, the I / O device 6
Then, the wait signal, that is, the READY signal, of the time obtained by adding the time until the data set of the input data is completed and the access time of the memory 5 is supplied,
The synchronization will be taken when the MA mode is executed.

As described above, according to the present invention, the wait signal during the DMA mode execution of I / O read and memory write is sent to the CPU of the memory.
Since the mode wait time is added to the data set time in the I / O device to be accessed, the wait control circuit assigned to each I / O device for the DMA mode is unnecessary, and the dynamic RAM is further added. Although the control and the circuit are simplified, the I / O devices having different access speeds can be easily retrofitted.

FIG. 3 is a block diagram of a microcomputer for carrying out the data transfer synchronization method of the present invention.

Upper 3 of 16-bit address bus AB of A0 to A15
Bits A13 to A15 are input to the address decoder ADC and select the memory M or I / O device to be accessed. The output decoded by the address decoder ADC is the memory control circuit MC and the I / O control circuit I / O.
Input to C and one of them is selected. In FIG. 3, one I / O device and one memory M are provided, but when there are a plurality of these, the memory control circuit MC and the I / O control circuit I / O are correspondingly provided.
C is provided and the decode output of the address decoder ADC selects only one of those control circuits.
When the memory control circuit MC is selected, the control circuit MC outputs a write / read control signal to the memory M forming the dynamic RAM. When the I / O control circuit I / OC is selected, a control signal is output to the I / O device.

In the CPU mode and the DMA mode, the READY signal for synchronizing the data transfer is the gates G1 to C.
Given to PU and DMAC. The READY terminal of the address decoder ADC and the READY terminal of the memory control circuit MC are connected to the input side of the gate G1. As will be described later, the RE of the address decoder ADC
The ADY terminal becomes low (true) during the CPU mode wait time of the I / O device. READ of the memory control circuit MC
Y terminal is used for memory CPU mode wait time and DM
Goes low during A-mode wait time.

When shifting to the DMA mode, first, the I / O control circuit I / O
A DMA request is issued from the OC to the DMAC. When the DMAC receives this DMA request, it requests the CPU to release the bus, and the I / O control circuit I / OC receives D
It outputs a DACK signal indicating that it can move to MA. Further, when data is transferred from the I / O device to the memory, the DMAC outputs a signal to the I / O control circuit I / OC.

FIG. 4 is a detailed block diagram of a part of the address decoder ADC. The data of the address buses A13, A14, A15 are input to the input terminals A, B, C of the decoder DC, respectively. The select signal M / input to the gate G2 and the gate G3 is controlled to be high when the memory M is selected, and to be low when the I / O device is selected. The decode output terminals Y1 to Y7 are output to the select terminals of the memory control circuit MC or the I / O control circuit I / OC via the respective gates. Here, it is assumed that the memory control circuit MC is selected via the gate G4 and the gate G3 when the decode output terminal Y6 or Y7 is selected.

An input terminal of the address latch signal ALE output from the CPU in the CPU mode is provided at the input of the shift register SR1 provided by the number of I / O devices together with the decoder DC, and at the rising edge of the address latch signal ALE. Start up and count CLOCK1. The second stage output QB of the shift register SR1 is input to the gate G5 together with the output of the gate G2. As a result,
Since the I / O device is selected in the CPU mode and the output of the gate G2 becomes high, the shift register SR1
The READY signal will be output from the gate G5 until the output of the stage QB becomes high. The shift register SR1 corresponds to the weight control circuit 1 shown in FIG.

FIG. 5 is a time chart when the I / O device is selected in the CPU mode. READ in the figure
The period T (I / O) in which the Y signal is low is the CPU mode wait time, and this READY signal itself is the wait signal for the CPU. As is apparent from FIG. 4, the length of the CPU mode wait time T (I / O) depends on which stage output of the shift register SR1 the input terminal of the gate G5 is connected to. Therefore, for an I / O device with a long access time, the input terminal of the gate G5 may be connected to the QC, QD or QE terminal according to the length of the access time, and conversely with an I / O device with a very short access time. For the / O device, the input terminal of the gate G5 may be connected to the QA terminal. By forming the CPU mode wait time of the I / O device in this way, C
It is possible to synchronize the PU and the I / O device.

FIG. 6 is a detailed block diagram of a part of the memory control circuit MC. The memory select signal from the address decoder ADC is input to the gate G6. The signal generated when reading from the memory and the signal generated when writing to the memory are gate G7.
To the memory select signal at the gate G6. Shift register SR
2 is activated when the output of the gate G6 becomes high when the CLOCK input terminal T is high and the refresh signal RFSH is high, that is, when it is not in the refresh period. Stage outputs QA and Q of shift register SR2
C is given to the memory M as a memory control signal via the gate G8 and the inverter IN1. The fourth stage output QD is the inverter I
It is guided to the gate 9 together with the output of the gate G6 via N2, and the gate G1 shown in FIG.
Is output to the input side of.

The CLOCK input terminal T of the shift register SR2 has a C
The output of the gate G10 which ANDs the LOCK2 and the data setup signal generated when the data set is completed in the DMA mode execution I / O device is input, and the shift register SR2 changes the signal from low to high. At this time, that is, when the DMA mode is executed, the I / O device is activated when the data set time has elapsed. Normally, the signal is high, so shift register SR2
Is activated when the signal on gate G6 goes high. Therefore, when the memory is executed in the CPU mode, the wait time is formed by the shift register SR2. That is, in the CPU mode execution of the memory, when the output of the gate G6 becomes high, the stage outputs QA to QE are sequentially set in synchronization with CLOCK2, and when the stage output QD becomes high, the READY signal goes from low to high. become. The shift control circuit 4 shown in FIG. 2 corresponds to the shift register SR2.

FIG. 7 is a time chart showing the operation of the memory control circuit MC in the CPU mode. In the figure, the time T (M) when the READY signal becomes low, that is, the CPU mode wait time, is the stage output of the shift register SR2 from the time when the output of the gate G6 becomes high and the memory select signal is formed by the address decoder ADC. QD
Until when it goes high. This time T (M) is the same as the shift register SR1 shown in FIG.
It can be lengthened or shortened by changing the stage output input to 9. The writing to the memory at this time is performed in synchronization with the trailing edge of.

FIG. 8 is a detailed block diagram of a part of the I / O control circuit I / OC.

As described above, the DACK signal and the signal are input from the DMAC to the I / O control circuit I / OC. The shift register SR3 is effectively driven when the signal is low, that is, when data is read from the I / O device and written to the memory. Also, C of the shift register SR3
CLOCK1 is input to the LOCK input terminal T, and the DAC
Count CLOCK1 when the K signal is high. The IOR is connected to the T terminal of the D-type flip-flop D-FF.
A signal is input to the reset terminal R via the gate 11 through the stage output QC and DAC of the shift register SR3.
K signal is input. The Q output of the flip-flop D-FF and the signal IOR are input to the gate 12, and the gate 1
2 is used to form a signal. Since the shift register SR3 and the flip-flop D-FF operate when the signal DACK and the signal are output from the DMAC, they form the signal only in the DMA mode.

When shifting to the DMA mode and reading data from the I / O device and writing to the memory, the operation is as follows.

When the DACK signal goes high and the signal goes low,
The stage outputs QA to QE of the shift register SR3 are CL
They are sequentially set in synchronization with OCK1. The flip-flop D-FF makes the Q output high by the fall of the signal, and the stage output QC of the shift register SR3.
The Q output goes low at the falling edge of. As a result,
The signal is low from the time when the signal falls to the time when the Q output of the flip-flop D-FF falls. Referring to FIG. 6, the shift register SR2 does not operate when the data setup signal is low, but is activated when the signal rises from low to high and the stage output Q2 is output.
A to QE are sequentially set in synchronization with CLOCK2. On the other hand, in the DMA mode, the address decoder A
A memory select signal is generated from DC, and a signal is generated when data is read from the I / O device and written to the memory. Therefore, the output of the gate G6 is high even if the shift register SR2 is not operating. Then, the READY signal is output via the gate 9. When the data setup signal becomes high shortly after the memory select signal is output and the READY signal is output, the shift register SR2 is activated and the stage outputs QA to QE are sequentially set. Then, the READY signal is reset when the stage output QD is set. That is, in the DMA mode,
A time obtained by adding the CPU mode wait time T (M) of the memory to the data set time from when the data setup signal rises from low to high is output to the DMAC as a READY signal. In this case, writing to the memory is controlled by delaying the fall of the memory.

FIG. 9 is a time chart showing the operations of the memory control circuit MC and the I / O control circuit I / OC in the DMA mode. Since the DMAC outputs a signal following the DACK signal, the shift register SR3 is activated when the signal becomes low. Then, when the stage output QC is set, the flip-flop D-FF is reset via the gate 11. As a result, at the output of the gate 12, a time T '(I / I) from the time when the signal falls to the time when the stage output QC is set.
A data setup signal whose O) is low is output and led to the gate 10. On the other hand, the gate G6 has D
Since the memory select signal has been output since the time of shifting to the MA mode, the shift register S is output from the gate G9.
The READY signal has been output before R2 is activated. Then, when the output of the gate G10 becomes high and the shift register SR2 is activated and the stage output QD is set, the READY signal is reset. Therefore, during this period, that is, the time T (DMA) from the output of the memory select signal to the reset of the stage output QD of the shift register SR2, the CPU mode wait time of the memory is added to the data set time of the I / O device. It will be the value. In this way, in the DMA mode, the CPU mode wait time of the memory is added to the data set time of the I / O device to synchronize with the DMAC and control the memory. The shift register SR3 and the flip-flop D-FF are
When there are a plurality of I / O devices, they are provided corresponding to each I / O device. The stage output of the shift register SR3 connected to the gate 11 is connected to QD or QE for the I / O device having a long access time, and is connected to the gate 11 for the I / O device having a short access time. Connect the stage output to QA or QB. By doing so, it is easy to lengthen or shorten the data set time T '(I / O).
The most efficient synchronization can be achieved with the I / O device.

[Brief description of drawings]

FIG. 1 is a conceptual block diagram of a microcomputer for explaining a conventional data transfer synchronization method. The second
FIG. 1 is a conceptual block diagram of a microcomputer for explaining a data transfer synchronization method according to an embodiment of the present invention. FIG. 3 is a schematic block diagram of a microcomputer for implementing the data transfer synchronization method of the present invention, FIG. 4 is a detailed block diagram of a part of the address decoder ADC, and FIG. 5 shows the operation of the address decoder ADC in the CPU mode. FIG. 6 is a detailed block diagram of a part of the memory control circuit MC, FIG. 7 is a time chart showing the operation of the memory control circuit MC in the CPU mode, and FIG. 8 is an I / O control circuit I / O. FIG. 9 is a detailed block diagram of part of the OC, and FIG. 9 shows the memory control circuit MC in the DMA mode.
3 is a time chart showing the operation of the I / O control circuit I / OC. DC ... Decoder, SR1 to SR3 ... Shift register.

Claims (2)

[Claims] 1. A CPU, a DMAC (Direct Memory Access Controller), a dynamic RAM and an I / O.
C which has a device and performs data transmission between a CPU and a dynamic RAM or between I / O devices as a data transfer mode.
It has a PU mode and a DMA (direct memory access) mode in which data is transferred between the dynamic RAM and the I / O device without going through the CPU, and the CPU is executed when the CPU mode is executed or when the DMA mode is executed.
Alternatively, in a data transfer synchronization method of a microcomputer for forming a wait signal for keeping the DMAC in a wait state for a predetermined time so as to synchronize data transfer, a dynamic RAM or each I / O is executed when the CPU mode is executed.
A wait signal is formed according to the CPU mode wait time individually assigned to the O device, and when the DMA mode is executed in which the input data is transferred to the dynamic RAM, the I / O device to be accessed until the data set of the input data is completed. The data set time required for
A method for synchronizing data transfer of a microcomputer, characterized in that a wait signal is formed by adding to a CPU mode wait time of AM. 2. When executing a DMA mode for transferring input data to a dynamic RAM, a wait control circuit for generating a CPU mode wait time of the dynamic RAM is started at the time when the data set time has elapsed, and the output of the wait control circuit is activated. The data transfer synchronization method for a microcomputer according to claim 1, wherein the weight signal is given to the DMAC.