JPH06197089A - Bit error addition device - Google Patents

Abstract

PURPOSE:To add a bit error equally to each channel of a test signal subjected to time division multiplexing outputted from a test signal generator. CONSTITUTION:A frequency division clock signal (b) subjected to 1/N frequency division by a 1/N frequency divider 7 is further frequency-divided to 1/M by a 1/M frequency divider 9. Then a frequency division signal (d) of the 1/M frequency divider 9 is counted by a counter circuit 18 and the result is outputted as a count value [D1D2D3]. A decoder circuit 22 outputting output signals h1-h8 corresponding to each channel lets the output signal represented by the count value be a bit error addition signal. Signal inverting circuits 141-148 invert the signal level of the digital test signal of a channel corresponding to an output signal of the bit error additional signal among digital test signals c1-c8 corresponding to each channel outputted from a pulse pattern generating circuit 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus incorporated in various digital communication systems such as PCM communication and a test signal generating apparatus for generating a test signal for testing a transmission line, and more particularly, The present invention relates to a bit error addition device that intentionally adds a bit error to a test signal output from this test signal generation device.

[0002]

2. Description of the Related Art For example, in the communication system shown in FIG. 6, N terminals 2 are connected to one transceiver device 1,
N terminals 4 are connected to the other transmitter / receiver 3.
The transmission / reception devices 1 and 3 are connected to each other through one transmission line 5. When one transceiver device 1 transmits each data of each terminal 2 connected to itself to each other terminal 4,
As shown in FIG. 7, each piece of N pieces of data from each terminal 2, that is, pieces of data of N channels are time-division multiplexed into one digital signal having a frame period T ₀ , and the transmission line 5 is transmitted.
Output to. The transmitting / receiving device 3 on the receiving side, which receives the digital signal of the format shown in FIG. 7, separates each time-division-multiplexed N-channel data included in the digital signal and transmits it to each terminal 4.

To evaluate the operating characteristics of a communication device that processes such time-division-multiplexed digital signals, a digital test signal having a predetermined pulse pattern is applied to the communication device under test, Check whether the communication device operates normally.

In recent years, as digital communication has become faster, in addition to a normal operation test for a communication device under test,
The bit error rate has become an important index as one of the characteristics of the test target digital signal transmission section. That is, a bit error is intentionally added to the digital test signal applied to the communication device to be evaluated or the digital signal transmission section, and the communication device to be tested correctly detects the bit error, or the digital signal transmission section to be tested is Evaluate whether the bit error is correctly transmitted.

Specifically, a digital test signal with a bit error added for each predetermined bit error period T _{E is} continuously applied for a certain period of time, and the bit error rate is measured at the output side of the measurement object. Evaluate how well they match.

FIG. 8 is a test signal generator for generating a test signal for performing a test on each communication device or transmission line of the communication system shown in FIG. 6, which transmits N-channel data by time division multiplexing. 3 is a block diagram showing a schematic configuration of FIG.

A reference clock signal a having a period T _C (= 1 / f _C f _C ; carrier frequency) supplied from a clock oscillator (not shown) is fed through an input terminal 6 to a 1 / N frequency divider 7
Is input to. The divided clock signal b divided into 1 / N by the 1 / N divider 7 is input to the next pulse pattern generation circuit 8 and also to the 1 / M divider 9 in the bit error addition device 10. Is applied. The 1 / M frequency divider 9 further frequency-divides the input frequency-divided clock signal b into 1 / M (M: a positive integer) and outputs it as a frequency-divided signal d.

As shown in FIG. 9, the pulse pattern generating circuit 8 outputs the N-channel digital test signal c in synchronization with the divided clock signal b. The digital test signal c of each channel is composed of, for example, a pseudo random signal having a (2 ⁿ -1) bit period. Each N channel digital test signal c is applied to the next multiplexer circuit 11. However, of the N channels, for example, 1
Only the digital test signal c of the second channel 1 is applied to the multiplexer circuit 11 via the exclusive OR gate 12 as a signal inverting circuit.

The divided signal d output from the 1 / M frequency divider 9 is applied to the other input terminal of the exclusive OR gate 12.
Has been entered. Therefore, the signal level of each bit data of the digital test signal c of channel 1 is forcibly inverted when the divided signal d is in the high (H) level state. That is, a bit error is added.

The multiplexer circuit 11 time-division-multiplexes the input N-channel digital test signal c into one test signal e having a frame period T ₀ in synchronization with the reference clock signal a and outputs it to the output terminal 13. Output.

FIG. 10 is a time chart showing the operation of each part when the number of channels N is set to 8 and the frequency division ratio M of the 1 / M division period 9 is set to 3.

In this case, the cycle of outputting one data of each digital test signal c of 8 channels output from the pulse pattern generating circuit 8 is the cycle T of the reference clock signal a.
It becomes N (= 8) times _C , which is equal to the frame period T ₀ of the test signal e finally output from the output terminal. Further, the period of the divided signal d output from the 1 / M frequency divider 9 is (N × M = 2) with respect to the period T _C of the reference clock signal a.
4) Double. Therefore, the bit error period T _{E in which} one bit error occurs in the digital test signal c of channel 1 is 24 times the period T _C of the reference clock signal a, that is, the frame period T ₀ , as shown in the equation (1). 3 times.

T _E = (N × M) T _C = M · T ₀ (1) Therefore, the test signal e output from the output terminal 13 includes one bit error in 24 bits. In this embodiment, the first data 11 and 4 of channel 1 are used.
The signal level of the th data 41 is inverted, resulting in a bit error.

As described above, by incorporating the bit error adding device 10, it is possible to intentionally add a bit error to the test signal e at a constant bit error period T _E.

[0015]

However, the bit error addition device 10 shown in FIG. 8 has a problem that a channel to which a bit error is added is fixed to a specific channel.

Therefore, when a bit error test is carried out on a part of a transmission line having a PCM communication line or a maintenance section (lower layer), a bit error may not occur at all in the channel to be tested, This causes a problem that an accurate bit error analysis cannot be performed.

For example, in the test signal generator incorporating the bit error addition device 10 of FIG.
8 and the frequency division ratio M of the 1 / M frequency divider 9 is set to 125, the bit error rate (1 / T _E ) of the bit error added to the test signal e is 1 × 10 ^−5. Therefore, the bit error is added only to the specific channel among the channels 1 to 8.

The present invention has been made in view of such circumstances, and specifies channels to which a bit error is added among the digital test signals output from the pulse pattern generation circuit in order or according to a fixed procedure. In this way, it is possible to add bit errors to all channels evenly, and to provide a bit error addition device that can perform an advanced bit error test even on a test object that handles a multiplexed data signal. To aim.

[0019]

In order to solve the above problems, the bit error adding device of the present invention comprises a 1 / N frequency divider for dividing a reference clock signal into 1 / N (N: a positive integer). , A pulse pattern generation circuit which outputs N channel digital test signals in parallel in synchronization with a divided clock signal output from the 1 / N frequency divider, and an N channel digital test output from the pulse pattern generation circuit And a multiplexer circuit that multiplexes the signals into one test signal in synchronization with the reference clock signal.

The bit error adding device divides the divided clock signal into 1 / M (M: a positive integer) and 1 / M.
A frequency divider, a counter circuit for counting the frequency-divided signals output from the 1 / M frequency divider and outputting a count value, and one output signal having N output signals and designated by the count value And a decoder circuit that makes a bit error addition signal, and is inserted in the signal path of the digital test signal of each channel input to the multiplexer circuit, and each output signal of the decoder circuit is applied,
N to invert the signal level of the digital test signal of the corresponding channel when the applied output signal is the bit error addition signal
And a signal inversion circuit.

In addition, in another invention, in addition to the above-mentioned means, the frequency-divided signal output from the 1 / M frequency divider is 1
/ K (K: a positive integer) is divided into 1 / K frequency dividers for outputting as operation prohibition signals, and 1 / K frequency division signals are input to the 1 / M frequency dividers. A gate circuit is inserted to prohibit the input of the frequency division signal to the 1 / M frequency divider during the duration of the operation prohibition signal output from the frequency divider.

In a bit error adding device of still another invention, in addition to the means of claim 1, a count value to be applied to the decoder circuit is externally supplied to an input path of the count value to the decoder circuit if necessary. An error channel fixing circuit for fixing the count value corresponding to the bit error addition channel designated by is inserted.

[0023]

In the bit error adder thus constructed, the divided clock signal output from the 1 / N frequency divider is further divided into 1 / M by the 1 / M frequency divider. The clock of the divided signal output from the 1 / M frequency divider is counted by the next counter circuit. Therefore, the count value is updated every time the bit error period (N · M · T _C ) elapses. Every time this count value is input, the decoder circuit uses the output signal of the channel designated by the count value as the bit error addition signal.

Therefore, a bit error is added to the digital test signals of the channels sequentially designated by the decoder circuit among the N channel digital test signals input to the multiplexer circuit. Therefore, bit errors are added to the digital test signals of all the channels at a constant cycle.

In another invention, the divided signal output from the 1 / M divider is further divided by the 1 / K divider, and the divided signal is used as an operation prohibition signal, The divided clock signal for the M divider is applied to the gate circuit inserted in the signal path.

[0026] Thus, every time the operation inhibiting signal having a (N · M · K · T C) cycle is inputted, the counting operation in the 1 / M frequency divider is delayed. As a result, the count value, which is updated every time the bit error period (N · M · T _C ) elapses, further shifts by one every (N · M · K · T _C ) period. Therefore, the bit error period (N · M
· T _C) although assigned a bit error addition signal sequentially to different channels for each further, (N · M · K · T C)
Bit error addition signals are continuously assigned to the same channel for each cycle.

As a result, the bit error period as a whole becomes longer, and bit errors are added more randomly.

Further, in another invention, a channel in which a bit error is caused can be arbitrarily designated by the error channel fixing circuit, if necessary.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the schematic arrangement of a test signal generator in which the bit error addition device of the embodiment is incorporated. The same parts as those of the conventional device shown in FIG. 8 are designated by the same reference numerals. Therefore, detailed description of the overlapping portions is omitted. FIG. 2 is a detailed circuit block diagram showing a main part of the bit error adding device according to the embodiment.

The reference clock signal a having the period T _C input from the input terminal 6 is divided by the 1 / N frequency divider 7,
The divided clock signal b is applied to the pulse pattern generation circuit 8. As shown in FIG. 2, the pulse pattern generation circuit 8 outputs each N channel digital test signal in synchronization with the divided clock signal b having a frame period T ₀ (= N · T _C ). Since the number of channels N is set to 8 in the apparatus of the embodiment, each of the eight channels of digital test signals c _{1 to} C ₈ is output.

The digital test signals c _{1 to} c ₈ output from the pulse pattern generating circuit 8 are input to the multiplexer circuit 11 via exclusive OR gates 14 _{1 to} 14 ₈ as signal inverting circuits, respectively. The multiplexer circuit 11 synchronizes the input digital test signals c _{1 to} c ₈ of N (= 8) channels with the test clock e having a frame period T ₀ in synchronization with the reference clock signal a.
_It is time-division multiplexed to ₁ and output to the output terminal 13.

The divided clock signal b output from the 1 / N frequency divider 7 is applied to the clock terminal of the 1 / M frequency divider 9 via an OR gate 15 as a gate circuit and the error channel fixing circuit 16 is also provided. Is applied to each of the trigger terminals T of the three flip-flops (FF) 17a to 17c.

The 1 / M frequency divider 9 further divides the input divided clock signal b into 1 / M and outputs it as a divided signal d. The frequency-divided signal d output from the 1 / M frequency divider 9 is applied to each clock terminal of the counter circuit 18 and the 1 / K frequency divider 19.

The 1 / K frequency divider 19 further divides the input frequency-divided signal d into 1 / K (K: a positive integer), and as shown in FIG. 5, a constant pulse width T ₀ (= N.multidot.N). It is output as an operation prohibiting signal g having T _C ). Therefore, the period T _G of the operation inhibition signal g is (N · M · K) times the period T _C of the reference clock signal a as shown in the equation (2).

T _G = (N · M · K) T _C = 3K · T ₀ = 8T _E (2) For example, the frequency division ratio K is set to the number N (= 8) of channels to be multiplexed for the test signal e ₁ . When the frequency division ratio M is set to 3 and T is set to 3, T _G = 192T _C. And the pulse width is 8T
It becomes _C.

The operation inhibition signal g output from the 1 / K frequency divider 19 is applied to the other end of the OR gate 15 via the changeover switch 20 operated by the operator. Therefore, 1
Even if the divided clock signal b of the period T ₀ is input to the / M frequency divider 9 during the period in which the H-level operation prohibition signal g is applied (frame period T ₀ ), it is not counted. Therefore, the divided signal d output from the 1 / M frequency divider 9 is 1
Get out of the pulse.

The counter circuit 18 counts the frequency-divided signal d output from the 1 / M frequency divider 9 and outputs the counted value in parallel 4-bit (4-digit) data (D ₁ , D ₂ , D ₃ , D). ₄ ) Output as. Since the count value that can be represented by 4-bit data is 1 to 16 in the decimal system, when the count value reaches 16, the count value returns to the initial value of 1 in response to the next input of the frequency division signal d.

Therefore, the data D ₁ , D ₂ , D of each digit
_As shown in the time chart of FIG. 4, ₃ and D ₄ indicate signal waveforms obtained by dividing the divided signal d into 1/2, 1/4, 1/8, and 1/16, respectively.

The data D ₁ , D ₂ , and D ₃ of each digit output from the counter circuit 18 are exclusive OR gate 2 respectively.
1 ₁ , 21 ₂ . The data terminal D of each FF 17a, 17b, 17c in the error channel fixing circuit 16 via 21 _3.
Is applied to. Further, the data D ₄ of the remaining digits is the exclusive OR gates 21 ₁ , 21 ₂ . 21 ₃ is applied to the other end. Therefore, while the digit data D ₄ having the longest period is in the H level period, the remaining digit signals D ₁ ,
The signal levels of D ₂ and D ₃ are inverted.

Each of the FFs 17a, 17b and 17c receives data every time the divided clock signal b of the cycle T ₀ is input to the trigger terminal T in a state where the set terminal S and the reset terminal R are both fixed to [L]. The next decoder circuit 2 is provided by taking in each data D ₁ , D ₂ , D ₃ applied to the terminal D.
2 is applied.

The error channel designating section 23 is provided at the set terminal S and the reset terminal R of each FF 17a, 17b, 17c.
To H level or L level designation signals are applied.
For example, if the set terminal S and the reset terminal R are fixed to [H] and [L], the data D value of the output terminal Q is [H].
(= 1)]. On the contrary, if the set terminal S and the reset terminal R are fixed to [L] and [H], the output terminal Q
The data D value of is fixed to [L (= 0)]. Therefore, the error channel designating unit 23 can fix the count value determined by the combination [D ₁ D ₂ D ₃ ] of the data D ₁ , D ₂ , and D ₃ applied to the decoder circuit 22 to an arbitrary value.

Eight output signals h ₁ , h ₂ , ..., H ₇ , h ₈ corresponding to each channel from channel 1 to channel 8 output from the decoder circuit 22 are exclusive OR gates of each channel. 14 ₁ , 14 ₂ , ..., 14
It is applied to the other input terminal of ₇ , 14 ₈ . Then, the decoder circuit 22 inputs the count value [D ₁ D ₂ every time the frequency-divided signal d of the period T _E (= 3T ₀ ) is input.
One output signal indicated by D ₃ ] is an H level bit error addition signal. For example, the count value [D ₁ D ₂ D ₃ ] is [00
0] Output signal h ₁ channel 1 becomes H level bit error addition signal when the count value [D ₁ D ₂ D _3] is [110] Output signal h ₇ of the channel 7 is at the H level in the case of It becomes a bit error addition signal.

Since the count value [D ₁ D ₂ D ₃ ] output from the counter circuit 18 is sequentially increased, the digital test signals c _{1 to} c ₈ output from the pulse pattern generation circuit 8 are sequentially output. A bit error addition signal is applied to the bit error signal and the bit error is added. The digital test signals c _{1 to} c ₈ to which the bit error is added are the multiplexer circuits 1
It is converted into _one test signal e 1 at 1 and output from the output terminal 13.

The operation of the test signal generator incorporating the bit error addition device thus constructed will be described with reference to the time charts shown in FIGS. 3, 4 and 5. 4 and 5 are enlarged views of the time axis of the time chart of FIG. The same parts as those in the time chart of the conventional apparatus shown in FIG. 10 are designated by the same reference numerals. Therefore, detailed description of the overlapping portions is omitted.

First, as shown in FIG. 1, the changeover switch 20
Is opened to prohibit the operation prohibition signal g output from the 1 / K frequency divider 19 from being input to the 1 / M frequency divider 9. In this case, the divided clock signal b output from the 1 / N frequency divider 7 is unconditionally input to the 1 / M frequency divider 9 via the OR gate 15. Further, in the error channel designating section 23 of the error channel fixing circuit 16, the FFs 17a to 17a are provided.
[L] [L] is set to the set terminal S and the reset terminal R of c so that the 3-digit count value [D ₁ D ₂ D ₃ ] output from the counter circuit 18 is input to the decoder circuit 22. Set.

In this state, as shown in FIG.
In synchronization with the frequency-divided signal d, the data D ₁ , D ₂ , and D ₃ of each digit output from the counter circuit 18 are subjected to an exclusive OR operation with the data D ₄ of another digit having a long cycle. Therefore, the count value [D ₁ D ₂ D ₃ ] at the time of being applied to the decoder circuit 22 is, as shown in the figure, the period (D) of the frequency-divided signal d when the data D ₄ of the longest period digit is in the H level period. Each time the bit error period T _E ) elapses, [0] [1]
[2] ... [6] [7], and in the L level period of the data D ₄ of the longest cycle digit, every time the cycle T _{E of the} divided signal d elapses, conversely [7] [ 6] [5] ……
It goes down as [1] [0].

The rising period T _F / 2 and the falling period T _F / 2 are the period T of the divided signal d.
It is N times _E (bit error period). Therefore, with the period T _F = 2NT _E , the decoder circuit 22 outputs the bit error addition signal for the same channel.

Therefore, each of the output signals h _{1 to} h ₈ output from the decoder circuit 22 has a bit error having a pulse width equal to the frame period T ₀ every time the period T _E (bit error period) of the divided signal d elapses. The additional signals are output in order. Therefore, the signal levels of the digital test signals c _{1 to} C ₈ of the channel corresponding to the period during which the bit error signal is output are inverted.

For example, as shown in FIG. 3, when a bit error is first added to the bit data 11 of the digital test signal c ₁ of the channel 1, the digital test signal of the channel 2 is sent when the bit error period T _{E has} elapsed. A bit error is added to the bit data 42 of c ₂ .

In this way, bit errors are sequentially added to the digital test signals c _{1 to} c ₈ of different channels each time the bit error period T _E elapses. Therefore, output terminal 1
A bit error is evenly added to the bit data of each channel of the test signal e ₁ output from _No. 3.

Next, the operation when the changeover switch 20 is closed will be described with reference to the time chart of FIG.

When the changeover switch 20 is closed, the operation prohibiting signal g having the cycle T _G (= 8T _E ) is applied to the cycle 9 of 1 / M minutes via the OR gate 15.
As a result, the divided signal d output from the 1 / M frequency divider 9 is missed by one pulse during the duration of the operation inhibition signal g having the pulse width T ₀ . As a result, the count value in the counter circuit 18 also maintains the same value.

For example, in FIG. 5, the decoder circuit 22
The count value [D ₁ D ₂ D ₃ ] input to the counter changes from [110] to [111], and while the same count value [111] continues, the same count of cycle T ₀ caused by the operation prohibition signal g is obtained. The number [111] is inserted. As a result, next output signal h ₈
Becomes a bit error addition signal with a delay of one frame period T ₀ .

On the other hand, from the pulse pattern generation circuit 8,
Since the digital test signals c _{1 to} c ₈ are output without a break, as a result, the digital test signal c of the channel 8 is output.
_The timing of adding bit error to ₈ is delayed. For example, the case of FIG. 4 with the changeover switch 20 opened is compared with the case of FIG. 5 with the changeover switch 20 turned on. When the changeover switch 20 is opened, a bit error is added to the 22nd data and the 25th data of the digital test signal c ₈ of the channel 8, but when the changeover switch 20 is turned on, the 22nd data is added. A bit error is added to the data and the 26th data.

As described above, by using the operation prohibition signal g output from the 1 / K frequency divider 19, the last bit error cycle is set to the normal bit error every time the cycle T _G of the operation prohibition signal g elapses. The period T _E is extended to (T _E + T ₀ ). Therefore, the bit error period of the entire device increases, and as a result, bit errors are added even more randomly.

Further, the error channel designating section 23 in the error channel fixing circuit 16 causes the decoder circuit 2
The count value [D ₁ D ₂ D ₃ ] applied to 2 can be fixed to any value. Therefore, the bit error can be added only to the arbitrarily specified specific digital test signal among the eight channels of digital test signals c _{1 to} c ₈ output from the pulse pattern generation circuit 8.

As a result, a bit error can be added by designating an arbitrary channel in the test signal e ₁ output from the output terminal 13, and a more detailed test can be performed on the test object.

The present invention is not limited to the above embodiment. For example, the number of output digits of the counter circuit 18 is limited to 3, each exclusive logic wheel gate 21 _{1 to} 21 ₃ is removed, and each data D ₁ , D ₂ and D ₃ is directly input to each FF 17.
It is also possible to input to a, 17b and 17c. In this case, the bit error added signals are output signals h ₁ , h ₂ ,
,, h ₇ , h ₈ appearing in order, and then the same h ₁ ~
Repeat in the order of h ₈ .

Further, in the embodiment, the frequency division ratio K of the 1 / K frequency divider 19 is set equal to the number of channels N, but it may be set to any positive integer other than N. Also, the number of channels N is not limited to 8 and can be set arbitrarily.

[0061]

As described above, in the bit error adding device of the present invention, the channels to which bit errors are added among the digital test signals output from the pulse pattern generating circuit are designated in order or according to a fixed procedure. ing. Therefore, it is possible to add bit errors evenly to all channels in the output test signal,
Even if the test object handles a time-division multiplexed data signal, an advanced bit error test can be performed.

Further, by operating the error channel fixing circuit, the channel to which the bit error is added can be arbitrarily selected and fixed as necessary, so that a more precise bit error test can be performed by designating the channel, for example.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a test signal generation device incorporating a bit error addition device according to an embodiment of the present invention.

FIG. 2 is a detailed block diagram showing a main part of the apparatus of the embodiment.

FIG. 3 is a time chart showing the operation of the apparatus of the embodiment.

FIG. 4 is a time chart showing the operation of the apparatus of the same embodiment.

FIG. 5 is a time chart showing the operation of the apparatus of the same embodiment.

FIG. 6 is a diagram showing a general communication system.

FIG. 7 is a diagram showing a general transmission format.

FIG. 8 is a block diagram showing a schematic configuration of a test signal generator in which a conventional bit error addition device is incorporated.

FIG. 9 is a detailed block diagram showing an essential part of the conventional apparatus.

FIG. 10 is a time chart showing the operation of the conventional device.

[Explanation of symbols]

7 ... 1 / N frequency divider, 8 ... Pulse pattern generation circuit, 9 ...
1 / M frequency divider, 11 ... Multiplexer circuit, 14 ₁ to 1
4 ₈ ... Exclusive OR gate, 15 ... OR gate, 16 ...
Error channel fixing circuit, 17a to 17c ... Flip-flop, 18 ... Counter circuit, 19 ... 1 / K frequency divider, 2
0 ... Changeover switch, 21 _{1 to} 21 ₃ ... Exclusive OR gate, 22 ... Decoder circuit, 23 ... Error channel designating section, a ... Reference clock signal, b ... Divided clock signal, c
₁ to c ₈ ... digital test signal, e ₁ ... test signal, d ... divided signal, g ... operation inhibiting signal, h ₁ ~h ₈ ... output signal.

Claims (3)

[Claims] 1. A 1 / N frequency divider (7) for frequency-dividing a reference clock signal into 1 / N (N: a positive integer) and a frequency-divided clock signal output from the 1 / N frequency divider. And a N-channel digital test signal for parallel output, and an N-channel digital test signal output from the pulse pattern generation circuit in one test signal in synchronization with the reference clock signal. In a bit error addition device for adding a bit error to a test signal output from a test signal generator having a multiplexer circuit (11) for multiplexing, the divided clock signal is divided into 1 / M (M: positive integer). A 1 / M frequency divider (9) that divides and a counter circuit (1 that counts the frequency-divided signal output from this 1 / M frequency divider and outputs a count value
8) and N output signals, 1 specified by the count value
Decoder circuit that uses each output signal as a bit error addition signal
(22), is inserted in the signal path of the digital test signal of each channel input to the multiplexer circuit, and each output signal of the decoder circuit is applied, the applied output signal of the bit error addition signal A bit error adding device provided with N signal inverting circuits (14 _{1 to} 14 ₈ ) for inverting the signal level of the digital test signal of the corresponding channel. 2. A 1 / K frequency divider (19) for frequency-dividing the frequency-divided signal output from the 1 / M frequency-divider into 1 / K (K: a positive integer) and outputting it as an operation prohibition signal. , 1 / M of the frequency-divided signal during the duration of the operation prohibition signal output from the 1 / K frequency divider, which is inserted in the signal path of the frequency-divided signal input to the 1 / M frequency divider The bit error adding device according to claim 1, further comprising a gate circuit (15) for inhibiting input to the frequency divider. 3. A count value inserted into an input path of the count value to the decoder circuit and applied to the decoder circuit,
2. The bit error addition device according to claim 1, further comprising an error channel fixing circuit (16) for fixing the count value corresponding to the bit error addition channel designated from the outside, if necessary.