JPH06196351A - Manufacture of layered ceramic capacitor - Google Patents

Manufacture of layered ceramic capacitor

Info

Publication number
JPH06196351A
JPH06196351A JP4344213A JP34421392A JPH06196351A JP H06196351 A JPH06196351 A JP H06196351A JP 4344213 A JP4344213 A JP 4344213A JP 34421392 A JP34421392 A JP 34421392A JP H06196351 A JPH06196351 A JP H06196351A
Authority
JP
Japan
Prior art keywords
plating
layer
ceramic capacitor
intermediate layer
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4344213A
Other languages
Japanese (ja)
Inventor
Toshio Kawada
敏雄 川田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP4344213A priority Critical patent/JPH06196351A/en
Publication of JPH06196351A publication Critical patent/JPH06196351A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/228Terminals
    • H01G4/232Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H01G4/2325Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electroplating And Plating Baths Therefor (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Ceramic Capacitors (AREA)

Abstract

PURPOSE:To provide a method for manufacturing a layered ceramic capacitor in which an irregularity in a thickness of an Ni-plated layer is small and a uniform thickness can be obtained. CONSTITUTION:A method for manufacturing a layered ceramic capacitor has the step of forming terminal electrodes 3a, 3b made of a base film 31 of an Ag conductor film, an Ni-plated intermediate layer 32 and an externally plated layer 33 on an end of a layer in which inner electrodes 2a, 2b and dielectric layers 1 are alternately laminated and sintered, and comprises the step of adding organic compound having =C-SI2-structure in Ni-plating solution to form the layer 32.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、積層セラミックコンデ
ンサの製造方法、特に、端子電極を構成するNiメッキ
中間層の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a monolithic ceramic capacitor, and more particularly to a method for manufacturing a Ni-plated intermediate layer which constitutes a terminal electrode.

【0002】[0002]

【従来の技術】積層セラミックコンデンサは、チタン酸
バリウム系の誘電体材料からなる誘電体シート上に、パ
ラジウム又はパラジウム合金(Ag−Pdなど)からな
る導体ペーストを内部電極層の形状に応じて印刷を行
い、このような誘電体シートを複数枚積層・圧着した
後、隣接対向する内部電極層が異なる端面部に露出する
ように、裁断して、所定雰囲気・温度で焼結して、積層
体を形成する。
2. Description of the Related Art In a multilayer ceramic capacitor, a conductor sheet made of palladium or a palladium alloy (Ag-Pd, etc.) is printed on a dielectric sheet made of a barium titanate-based dielectric material according to the shape of internal electrode layers. After laminating and pressure-bonding a plurality of such dielectric sheets, cutting is performed so that adjacent internal electrode layers are exposed at different end faces, and sintering is performed at a predetermined atmosphere and temperature to obtain a laminated body. To form.

【0003】続いて、積層体の端面に端子電極を形成し
て、積層セラミックコンデンサを製造していた。
Subsequently, a terminal electrode was formed on the end surface of the laminated body to manufacture a laminated ceramic capacitor.

【0004】端子電極の具体的な製造方法としては、焼
結された積層体の端面に、Ag系導体ペーストをディッ
プ法で、塗布し、乾燥・焼きつけして、下地膜を形成し
た後、硫酸ニッケル、塩化ニッケル、硼酸、水を含むN
iメッキ液中で、メッキ処理して、Ag系導体膜の下地
膜上に、Niメッキ中間層を被覆していた。さらにその
後、Niメッキ中間層上に、外部メッキ層、例えば、S
nメッキ液中でメッキ処理してSnメッキ層を形成して
いた。
As a specific method of manufacturing the terminal electrode, an Ag-based conductor paste is applied to the end surface of the sintered laminate by a dipping method, dried and baked to form a base film, and then sulfuric acid is added. N containing nickel, nickel chloride, boric acid, water
A plating treatment was performed in an i-plating solution to coat a Ni-plating intermediate layer on the base film of the Ag-based conductor film. After that, an external plating layer such as S is formed on the Ni plating intermediate layer.
An Sn plating layer was formed by plating in an n plating solution.

【0005】[0005]

【発明が解決しようとする課題】しかし、上述のNiメ
ッキ中間層の製造工程において、Niメッキ中間層の厚
みにバラツキが発生してしまうという問題点があった。
Niメッキ中間層の厚みは、好ましくは、1.3〜2.
7μm、特に1.5〜2.5μm程度となることが望ま
しいが、実際には、1.0〜3.0μmとバラツキが大
きくなる。Niメッキ中間層は、積層セラミックコンデ
ンサをプリント配線基板上に半田接合する際、半田によ
ってAg系導体膜の下地膜が食われないように、また、
その熱に対して耐え得るようにするために形成されるも
のであるが、1.3μm以下と薄くなると、Ag系導体
膜の下地膜の半田くわれが顕著になり、また耐熱信頼性
も大きく低下してしまう。
However, there is a problem in that the thickness of the Ni-plated intermediate layer varies in the manufacturing process of the Ni-plated intermediate layer described above.
The thickness of the Ni-plated intermediate layer is preferably 1.3 to 2.
It is desirable that the thickness is 7 μm, particularly about 1.5 to 2.5 μm, but in reality, the variation becomes large, 1.0 to 3.0 μm. The Ni-plated intermediate layer prevents the underlying film of the Ag-based conductor film from being eaten by the solder when the multilayer ceramic capacitor is solder-bonded onto the printed wiring board.
It is formed to withstand the heat, but when it is as thin as 1.3 μm or less, the solder layer of the base film of the Ag-based conductor film becomes remarkable, and the heat resistance is also large. Will fall.

【0006】本発明は、上述の問題点に鑑みて案出され
たものであり、その目的は、Niメッキ中間層の厚みを
所定厚み以上に、且つのバラツキを少なくして、Ag系
導体膜の下地膜の半田くわれを有効に防止できる積層セ
ラミックコンデンサの製造方法を提供するものである。
The present invention has been devised in view of the above-mentioned problems, and an object thereof is to make the thickness of the Ni-plating intermediate layer equal to or more than a predetermined thickness and to reduce the variation thereof, thereby making the Ag-based conductor film. The present invention provides a method for manufacturing a monolithic ceramic capacitor, which can effectively prevent solder scuffing of the underlying film.

【0007】[0007]

【課題を解決するための手段】本発明は、内部電極層、
誘電体層が交互に積層され、焼結された積層体の端部
に、Ag系導体材料を塗布・焼き付けを行い、さらに、
Ag系導体膜上に、Niメッキ液でメッキ処理してNi
メッキ中間層を形成し、さらに、Niメッキ中間層上に
外部メッキ層を形成した積層セラミックコンデンサの製
造方法において、前記Niメッキ液中に、=C−SO2
−構造を有する有機化合物を添加して、Niメッキ中間
層を形成した積層セラミックコンデンサの製造方法であ
る。
The present invention is directed to an internal electrode layer,
Dielectric layers are alternately laminated, and an Ag-based conductor material is applied / baked to the end of the sintered laminated body, and further,
Ni-plated on the Ag-based conductor film with Ni plating solution
In a method of manufacturing a laminated ceramic capacitor, wherein a plating intermediate layer is formed, and an external plating layer is further formed on the Ni plating intermediate layer, in the Ni plating solution, = C-SO 2
-A method for producing a monolithic ceramic capacitor in which a Ni-plated intermediate layer is formed by adding an organic compound having a structure.

【0008】[0008]

【作用】本発明によれば、Niメッキ中間層の形成にあ
たり、Niメッキ液(硫酸ニッケル、塩化ニッケル、硼
酸、水)に、さらに、=C−SO2 −構造を有するサッ
カリン、1・5ナフタリンジスルホン酸ナトリウム、
1.3.6ナフタレントリスルホン酸ナトリウム、パラ
トルエンスルホンアミドなどの有機化合物の少なくとも
1種類を添加したため、Niメッキ中間層の厚みが1.
3〜2.7μm、特に好ましい範囲である1.5〜2.
5μmとなり、バラツキが少ないメッキ層を形成するこ
とができる。
According to the present invention, in forming the Ni plating intermediate layer, a Ni plating solution (nickel sulfate, nickel chloride, boric acid, water) is further added, and saccharin having a = C-SO 2 -structure and 1.5 naphthalene. Sodium disulfonate,
1.3.6 Since at least one organic compound such as sodium naphthalene trisulfonate and paratoluene sulfonamide was added, the thickness of the Ni plating intermediate layer was 1.
3 to 2.7 μm, which is a particularly preferable range of 1.5 to 2.
Since the thickness is 5 μm, it is possible to form a plating layer with less variation.

【0009】これにより、プリント配線基板への半田接
合時における耐熱信頼性が向上し、また、端子電極の半
田食われを有効に防止できることになる。
As a result, the heat resistance reliability at the time of solder joining to the printed wiring board is improved, and the solder erosion of the terminal electrode can be effectively prevented.

【0010】[0010]

【実施例】以下、本発明の積層セラミックコンデンサの
製造方法を詳説する。
EXAMPLES The method for producing a monolithic ceramic capacitor of the present invention will be described in detail below.

【0011】積層セラミックコンデンサは、図1に示す
ように、誘電体層1と内部電極層2a、2bとを交互に
積層した積層体10の両端に端子電極3a、3bが形成
されている。
In the monolithic ceramic capacitor, as shown in FIG. 1, terminal electrodes 3a and 3b are formed at both ends of a laminate 10 in which dielectric layers 1 and internal electrode layers 2a and 2b are alternately laminated.

【0012】具体的には、誘電体層1となる誘電体セラ
ミックのグリーンシート上に、内部電極層2aまたは2
bとなる内部電極パターンをパラジウムまたはパラジウ
ム合金の導体ペーストで印刷塗布し、その後、各グリー
ンシートを内部電極層2aと2bとが互いに対向し、且
つ積層体10の対向する両端から各々露出するように積
層・熱圧着し、積層セラミックコンデンサの形状に応じ
て裁断した後、所定焼成条件で焼結して、焼結された積
層体10を得ていた。
Specifically, the internal electrode layer 2a or 2 is formed on the dielectric ceramic green sheet to be the dielectric layer 1.
The internal electrode pattern to be b is printed and applied with a conductive paste of palladium or a palladium alloy, and then the respective green sheets are arranged so that the internal electrode layers 2a and 2b face each other and are exposed from both ends of the laminated body 10 facing each other. Then, the laminated body 10 was laminated and thermocompression-bonded, cut according to the shape of the laminated ceramic capacitor, and then sintered under predetermined firing conditions to obtain a sintered laminated body 10.

【0013】次に、積層体10の両端に露出した内部電
極層2a、2bに端子電極3a、3bを形成する。ま
ず、積層体10の対向する両端面に、Ag系導体ペース
トをディッピング法で塗布し、その後所定条件で焼きつ
けを行い、80〜100μmの膜厚のAg系導体膜から
成る下地膜31を形成する。続いて、硫酸ニッケル、塩
化ニッケル、硼酸、水からなるNiメッキ液に、さら
に、=C−SO2 −構造を有する例えばサッカリンを添
加した液に、電解メッキを行い、2.0μm程度のNi
メッキ中間層32を形成する。続いて、5〜6μm程度
のSnメッキ層33を形成する。その後、中和処理、水
洗処理、アルコールによる置換、乾燥を行い、積層セラ
ミックコンデンサが製造される。
Next, terminal electrodes 3a and 3b are formed on the internal electrode layers 2a and 2b exposed at both ends of the laminated body 10. First, an Ag-based conductor paste is applied to both end surfaces of the laminated body 10 facing each other by a dipping method, and then baked under predetermined conditions to form a base film 31 made of an Ag-based conductor film having a thickness of 80 to 100 μm. . Subsequently, electrolytic plating is performed on a Ni plating solution composed of nickel sulfate, nickel chloride, boric acid, and water, and further, for example, a solution obtained by adding, for example, saccharin having a = C-SO 2 -structure, to obtain Ni of about 2.0 μm.
The plating intermediate layer 32 is formed. Then, the Sn plating layer 33 of about 5 to 6 μm is formed. After that, neutralization treatment, water washing treatment, substitution with alcohol, and drying are carried out to manufacture a monolithic ceramic capacitor.

【0014】ここで、端子電極3a、3bのAg系導体
膜の下地膜31は、内部電極層2a、2bとの接続を確
実におこなうために作用し、Niメッキ中間層32は、
主にAg系導体膜の下地膜31の半田食われを防止する
とともに、耐熱性を向上させるものである。例えば、A
g系導体膜の下地膜31が露出する場合には、270
℃、10秒程度の熱でAg系導体膜の下地膜31が劣化
してしまうが、Niメッキ中間層32を形成することに
より、270℃、60秒程度にまで、耐熱性を向上させ
ることができる。Snメッキ層33は、主に半田接合さ
せる際の半田濡れ性を向上させるために作用する。
Here, the base film 31 of the Ag-based conductor film of the terminal electrodes 3a and 3b acts to ensure the connection with the internal electrode layers 2a and 2b, and the Ni-plated intermediate layer 32 is
The main purpose is to prevent solder erosion of the base film 31 of the Ag-based conductor film and to improve heat resistance. For example, A
If the underlying film 31 of the g-based conductor film is exposed, 270
Although the base film 31 of the Ag-based conductor film is deteriorated by heat of about 10 ° C. for about 10 seconds, heat resistance can be improved to about 270 ° C. for about 60 seconds by forming the Ni plating intermediate layer 32. it can. The Sn plating layer 33 acts mainly to improve solder wettability when soldering.

【0015】本発明は、上述したように、Niメッキ中
間層32を形成するにあたり、Niメッキ液に、=C−
SO2 −構造を有する有機化合物を添加したことであ
る。=C−SO2 −構造を有する有機化合物としては、
上述のサッカリンの他に、1.5ナフタリンジスルホン
酸ナトリウム、1.3.6ナフタレントリスルホン酸ナ
トリウム、パラトルエンスルホンアミドなどが挙げら
れ、その1種類、または2種類以上が添加される。ま
た、その添加量は、Niメッキ液1l(リットル)に対
して、5〜15ml(ミリリットル)を添加する。
As described above, according to the present invention, when forming the Ni plating intermediate layer 32, the Ni plating solution is: C-
That is, an organic compound having a SO 2 − structure was added. As an organic compound having a ═C—SO 2 — structure,
In addition to the above-mentioned saccharin, 1.5 sodium naphthalene disulfonate, 1.3.6 sodium naphthalene trisulfonate, paratoluene sulfonamide and the like can be mentioned, and one kind or two or more kinds thereof are added. The amount of addition is 5 to 15 ml (milliliter) with respect to 1 l (liter) of Ni plating solution.

【0016】このように、Niメッキ液に=C−SO2
−構造を有する有機化合物を添加することにより、Ni
メッキ中間層32を、その膜厚を最適な膜厚である2.
0μm程度に、且つそのバラツキを少なくすることがで
き、プリント配線基板上に積層セラミックコンデンサを
半田接合した時、Ag導体膜の下地層31の半田食われ
による不良が大幅に改善できる。
As described above, the Ni plating solution is used as = C-SO 2
Ni by adding an organic compound having a structure
1. The plating intermediate layer 32 has an optimal film thickness.
The variation can be reduced to about 0 μm, and when a multilayer ceramic capacitor is soldered on a printed wiring board, a defect due to solder erosion of the underlayer 31 of the Ag conductor film can be significantly reduced.

【0017】(実験例)本発明者は、3.2mm×1.
6mmの積層セラミックコンデンサの端子電極3a、3
bとして、Ag系導体膜の下地層31を形成した後、N
iメッキ液1リットルに対して、0〜15ミリリットル
の=C−SO2 −構造を有する有機化合物であるサッカ
リンを添加し、20A・20分の条件で、下地層31上
にNiメッキ中間層32を形成して、そのサッカリンの
添加量の変化によるNiメッキ中間層32の膜厚のバラ
ツキを調べた。その結果を図2に示し、そのバラツキ度
合を図3に示した。
(Experimental Example) The inventor of the present invention has 3.2 mm × 1.
6mm monolithic ceramic capacitor terminal electrodes 3a, 3
As b, after forming the underlayer 31 of the Ag-based conductor film, N
i plating solution to one liter of 0-15 ml = C-SO 2 - was added saccharin is an organic compound having a structure, in 20A · 20 minutes condition, Ni-plated intermediate layer over the base layer 31 32 Was formed, and the variation in the film thickness of the Ni-plated intermediate layer 32 due to the change in the amount of saccharin added was investigated. The results are shown in FIG. 2, and the degree of variation is shown in FIG.

【0018】図2において、サッカリンを添加しない通
常のNiメッキ液では、Niメッキ中間層32が、膜厚
約1.0〜3.0μmと大きなバラツキが発生したの対
して、5ml/l添加した場合には、約1.3〜2.7
μmであり、さらに10ml/l添加した場合には、約
1.5〜2.5μmであり、それ以上添加しても、略同
一の膜厚であった。
In FIG. 2, in the normal Ni plating solution containing no saccharin, the Ni plating intermediate layer 32 showed a large variation of about 1.0 to 3.0 μm in film thickness, while 5 ml / l was added. In some cases, about 1.3 to 2.7.
μm, and when 10 ml / l was further added, it was about 1.5 to 2.5 μm, and even if it was added more, the film thickness was substantially the same.

【0019】尚、サッカリン以外の=C−SO2 −構造
を有する有機化合物であっても、同様の結果が得られ
た。
Similar results were obtained with organic compounds having a ═C—SO 2 — structure other than saccharin.

【0020】以上のように、Niメッキ中間層32を形
成するにあたり、Niメッキ液に、=C−SO2 −構造
を有する有機化合物を添加することにより、Niメッキ
中間層32の膜厚のバラツキが改善される。従って、こ
のバラツキ、特に膜厚の薄い膜で発生していたAg系導
体膜の下地膜31の半田食われが大幅に抑えることがで
き、歩留りが大幅に向上する。
As described above, when the Ni plating intermediate layer 32 is formed, by adding an organic compound having a ═C—SO 2 — structure to the Ni plating solution, the film thickness of the Ni plating intermediate layer 32 varies. Is improved. Therefore, this variation, particularly the solder erosion of the base film 31 of the Ag-based conductor film, which has occurred in the thin film, can be significantly suppressed, and the yield is greatly improved.

【0021】また、その添加量としては、少なくとも5
ml/l以上添加することが好ましく、上限としては、
15ml/lである。5ml/l以上添加しなくては、
バラツキの減少を行う効果を充分に得ることはできず、
また、15ml/l以上添加すると、メッキが脆くなっ
たり、割れが発生するという不具合が生じる。
The amount of addition is at least 5
It is preferable to add at least ml / l, and the upper limit is
15 ml / l. If you do not add more than 5 ml / l,
It is not possible to obtain the effect of reducing variations sufficiently,
Further, if it is added in an amount of 15 ml / l or more, problems occur that the plating becomes brittle and cracks occur.

【0022】尚、上述の実施例において、Niメッキ中
間層32上には、Snメッキ層33を被着した例を示し
たが、Sn/Pbメッキでなどの半田濡れ性の良好な材
料であればよく、また、単層または2種類以上のメッキ
層を積層して形成しても構わない。
In the above embodiment, the Sn plating layer 33 is deposited on the Ni plating intermediate layer 32. However, a material having good solder wettability such as Sn / Pb plating may be used. Alternatively, it may be formed in a single layer or by laminating two or more kinds of plating layers.

【0023】[0023]

【発明の効果】本発明によれば、積層セラミックコンデ
ンサの端子電極のNiメッキ中間層を形成するにあた
り、Niメッキ液中に、=C−SO2 −構造を有する有
機化合物を添加したため、Niメッキ中間層の厚みのバ
ラツキを大きく改善でき、特に膜厚が薄いことによるA
g系導体膜の下地膜の半田食われを有効に防止でき、耐
熱性にすぐれた端子電極を形成することができる。
According to the present invention, since an organic compound having a ═C—SO 2 — structure is added to the Ni plating solution when forming the Ni plating intermediate layer of the terminal electrode of the laminated ceramic capacitor, the Ni plating is performed. The variation in the thickness of the intermediate layer can be greatly reduced, and especially due to the small thickness A
It is possible to effectively prevent solder erosion of the base film of the g-based conductor film, and to form a terminal electrode having excellent heat resistance.

【図面の簡単な説明】[Brief description of drawings]

【図1】典型的な積層セラミックコンデンサの断面図で
ある。
FIG. 1 is a cross-sectional view of a typical monolithic ceramic capacitor.

【図2】サッカリンの添加量の変化によるNiメッキ中
間層の膜厚のバラツキを示す特性図である。
FIG. 2 is a characteristic diagram showing variations in the film thickness of the Ni-plated intermediate layer due to changes in the amount of saccharin added.

【図3】図2におけるバラツキ度合いを示す特性図であ
る。
FIG. 3 is a characteristic diagram showing the degree of variation in FIG.

【符号の説明】[Explanation of symbols]

1・・・・誘電体層 2a、2b・・・・内部電極層 3a、3b・・・・端子電極 31・・・・下地膜 32・・・・Niメッキ中間層 33・・・・Snメッキ層 1 ... Dielectric layer 2a, 2b ... Internal electrode layer 3a, 3b ... Terminal electrode 31 ... Base film 32 ... Ni plating intermediate layer 33 ... Sn plating layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 内部電極層、誘電体層が交互に積層さ
れ、焼結された積層体の端部に、端子電極としてAg系
導体材料を塗布・焼き付けを行い、さらに、Ag系導体
膜上にNiメッキ液でメッキ処理してNi中間層を形成
し、さらに、Niメッキ層上に外部メッキ層を形成した
積層セラミックコンデンサの製造方法において、 前記Niメッキ液に、=C−SO2 −構造を有する有機
化合物を添加して、Niメッキ層を形成することを特徴
とする積層セラミックコンデンサの製造方法。
1. An Ag-based conductor material is applied and baked as a terminal electrode to an end portion of a laminated body in which internal electrode layers and dielectric layers are alternately laminated, and further, on an Ag-based conductor film. In the method for manufacturing a monolithic ceramic capacitor, wherein a Ni intermediate layer is formed by plating with a Ni plating solution, and an outer plating layer is further formed on the Ni plating layer, wherein the Ni plating solution has a = C-SO 2 -structure. A method for manufacturing a monolithic ceramic capacitor, comprising forming an Ni plating layer by adding an organic compound having
JP4344213A 1992-12-24 1992-12-24 Manufacture of layered ceramic capacitor Pending JPH06196351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4344213A JPH06196351A (en) 1992-12-24 1992-12-24 Manufacture of layered ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4344213A JPH06196351A (en) 1992-12-24 1992-12-24 Manufacture of layered ceramic capacitor

Publications (1)

Publication Number Publication Date
JPH06196351A true JPH06196351A (en) 1994-07-15

Family

ID=18367508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4344213A Pending JPH06196351A (en) 1992-12-24 1992-12-24 Manufacture of layered ceramic capacitor

Country Status (1)

Country Link
JP (1) JPH06196351A (en)

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US6373683B1 (en) * 1999-10-08 2002-04-16 Murata Manufacturing Co., Ltd. Electronic parts
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US10354802B1 (en) * 2018-09-18 2019-07-16 Samsung Electro-Mechanics Co., Ltd. Ceramic electronic component
JP2020072246A (en) * 2018-10-29 2020-05-07 サムソン エレクトロ−メカニックス カンパニーリミテッド. Capacitor component
US10957488B2 (en) * 2018-04-20 2021-03-23 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component
US11776754B2 (en) 2019-04-26 2023-10-03 Murata Manufacturing Co., Ltd. Electronic component and mounting structure
US12020868B2 (en) 2018-04-20 2024-06-25 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6373683B1 (en) * 1999-10-08 2002-04-16 Murata Manufacturing Co., Ltd. Electronic parts
JP2001210545A (en) * 2000-01-26 2001-08-03 Murata Mfg Co Ltd Chip electrical component and chip capacitor
JP3630056B2 (en) * 2000-01-26 2005-03-16 株式会社村田製作所 Chip-type electronic components and chip-type capacitors
JP2015046451A (en) * 2013-08-28 2015-03-12 株式会社村田製作所 Electronic component
US10957488B2 (en) * 2018-04-20 2021-03-23 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component
US11488779B2 (en) 2018-04-20 2022-11-01 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component
US12020868B2 (en) 2018-04-20 2024-06-25 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component
US10354802B1 (en) * 2018-09-18 2019-07-16 Samsung Electro-Mechanics Co., Ltd. Ceramic electronic component
JP2020072246A (en) * 2018-10-29 2020-05-07 サムソン エレクトロ−メカニックス カンパニーリミテッド. Capacitor component
US10804034B2 (en) * 2018-10-29 2020-10-13 Samsung Electro-Mechanics Co., Ltd. Capacitor component having secondary phase material contained in external electrode thereof
US11152155B2 (en) 2018-10-29 2021-10-19 Samsung Electro-Mechanics Co., Ltd. Capacitor component having secondary phase material contained in external electrode thereof
US11776754B2 (en) 2019-04-26 2023-10-03 Murata Manufacturing Co., Ltd. Electronic component and mounting structure

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