JP2001210545A - Chip electrical component and chip capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chip electrical component which enables effective prevention of both tombstone phenomenon and soldering crack, even if the component is miniaturized further. SOLUTION: This multilayer capacitor is a sintered ceramic 2 of 0.6 mm or smaller length, 0.3 mm or less in width, 0.3 mm or less in thickness as an electronic component, each side surfaces 2a and 2b having external electrodes 4 and 5 which have sintered metal layers 4 and 5, which are laminated with Ni-plated layer 4b and 5b, when viewed in cross-sectional plane from the length and the thickness directions, the thickness of the sintered metal layers 4a, 5b (T1) is 10 μm or less, the thickness of the plated layer 4b and 5b (T2) is 6 μm and T2>T1×0.25.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type electronic component such as a multilayer capacitor and a chip type capacitor, and more particularly, to an electronic component body and an external electrode formed on an outer surface of the electronic component body. To improved chip-type electronic components and chip-type capacitors.

[0002]

2. Description of the Related Art In recent years, with miniaturization of electronic equipment, further miniaturization of various chip-type electronic components such as multilayer capacitors has been required. Conventionally, as a small chip type multilayer capacitor, the dimension in the length direction is 3.2 mm ×
Those having a dimension in the width direction of 1.6 mm and a dimension in the thickness direction of 1.25 mm have been widely used. FIGS. 3A and 3B show the structure of this multilayer capacitor.

In the multilayer capacitor 51, internal electrodes 53a to 53d are formed in a ceramic sintered body 52. An external electrode 54 is formed on the end face 52a so as to be electrically connected to the internal electrodes 53a and 53c. Further, an external electrode 55 is formed to cover the end face 52b so as to be electrically connected to the internal electrodes 53b and 53d.

The external electrodes 54 and 55 are respectively formed of a sintered metal layer 54a, 55a formed by applying and baking a silver paste, and Ni plating formed by wet plating on the sintered metal layer 54a, 55a. Layers 54b and 55
b and Sn plating layers 54c and 55c. In the multilayer capacitor 51 having the above dimensions, the silver paste is applied to the end face 52.
Although applied from the side of a or 52b, the thickness tends to be thin at the edge of the ceramic sintered body 52.
For example, as is clear from FIG. 3 (b) which shows the circle A in FIG. 3 (a) in an enlarged manner, the applied thickness of the silver paste becomes relatively thin at the edge portion, so that the thickness of the sintered metal layer 54a is reduced. The edges tended to be thin. That is, the thickness of the sintered metal layers 54a and 55a tends to be thin at the edges formed by the end surfaces 52a and 52b and the upper surface 52c, the lower surface 52d and the side surfaces adjacent to the end surfaces 52a and 52b.

At the edges, the sintered metal layers 54a, 54
When the thickness of 4b is reduced, the solder erosion of the sintered metal layers 54a and 54b is likely to occur when mounting on a printed circuit board or the like.

Therefore, conventionally, the edge portion is rounded by barrel polishing or the like, whereby the sintered metal layer 5 at the edge portion is rounded.
Attempts have been made to increase the thickness of 4a, 54b. However, as the miniaturization of the multilayer capacitor 51 progresses, when mounting on a printed circuit board or the like using the molten solder, the chip-type multilayer capacitor 51 causes one of the external electrodes 54 and 55 to face upward due to the surface tension of the molten solder. , The so-called tombstone phenomenon tends to occur.

On the other hand, as described above, the ceramic sintered body 5
When the amount of polishing for rounding the edge portion 2 is small, solder erosion is likely to occur. Therefore, the multilayer capacitor 51
Then, in order to prevent solder erosion, the sintered metal layer 54
The Ni plating layers 54b and 55b are formed on the surfaces of the a and 55a. The thickness of each of the Ni plating layers 54b and 55b is generally about 1 to 2 μm, and is formed to have a substantially uniform thickness. In order to prevent the solder erosion, it is preferable to increase the thickness of the Ni plating layer.

On the other hand, Ni formed by a wet plating method
The plating layers 54b and 55b apply a tightening stress to the ceramic sintered body 52. Therefore, if the thickness of the Ni plating layers 54b and 55b is increased in order to prevent solder erosion, cracks and the like tend to occur in the ceramic sintered body 52. In particular, it has been found that when the thickness of the Ni plating layer is larger than 6 μm, the cracks are easily generated.

In addition, if the current flowing during wet plating is increased in order to increase the thickness of the Ni plating layers 54b and 55b, thickness variations of the Ni plating layers 54b and 55b tend to occur. In addition, since hydrogen is generated, irregularities called pits easily occur on the surfaces of the Ni plating layers 54b and 55b.

On the other hand, when the thickness of the silver paste applied to form the sintered metal layers 54a and 55a is increased on the edge portion where the thickness tends to be small, the external electrodes 54 and 55 are formed on the edge portion. Becomes larger,
Again, the tombstone phenomenon described above tends to occur.

In general, external electrodes of electronic components are required to have a uniform thickness. However, in the external electrodes 54 and 55, the sintered metal layers 54a and 55a
Is often formed by applying a silver paste by a paste dipping method. Therefore, as described above, when the thickness of the conductive paste applied is increased, the external electrodes 54, 5
The roundness on the edge portion of No. 5 becomes large, and the tombstone phenomenon easily occurs. Conversely, when the conductive paste application thickness is reduced, the thickness of the sintered metal layers 54a and 55a on the edge portion is further reduced, and solder erosion is likely to occur.

[0012] Therefore, an object of the present invention is to prevent the tombstone phenomenon at the time of mounting on a printed circuit board or the like, and to prevent the solder erosion at the edge portion even when the size is further reduced. It is an object of the present invention to provide a chip-type electronic component and a chip-type capacitor that can prevent cracks.

[0013]

The chip-type electronic component according to the present invention has a longitudinal dimension of about 0.6 mm or less, a width dimension of about 0.3 mm or less, and a thickness dimension of about 0.3 mm or less. An electronic component body having first and second end faces located at both ends in the length direction, and first and second electronic component bodies.
The first and second external electrodes are formed so as to cover an end surface of the electronic component body and have an electrode covering portion extending to another surface adjacent to the end surface of the electronic component body. Layers and
In a chip-type electronic component including a Ni plating layer formed on a sintered metal layer, when viewed in a cross section in a direction parallel to the length direction and the thickness direction and orthogonal to the width direction,
The thickness T1 of the thinnest portion of the sintered metal layer at the edge between the end face of the electronic component body and the other adjacent face is 10
μm or less, the thickness T2 of the Ni plating layer on the portion is 6 μm or less, and T2> T1 × 0.25.

In a specific aspect of the chip-type electronic component according to the present invention, the edge of the electronic component body is rounded, and the edge has a radius of curvature of 30 μm when viewed in cross section.
m or less, and the radius of curvature of the outer surface of the sintered metal layer at the edge when viewed in cross section is 60 μm or less.

The chip type capacitor according to the present invention has a longitudinal dimension of about 0.6 mm or less and a width dimension of about 0.3 m.
m, a thickness in the thickness direction of about 0.3 mm or less, and a capacitor body having first and second end faces located at both ends in the length direction, and covering the first and second end faces of the capacitor body. And first and second external electrodes are formed so as to have an electrode covering portion extending to another surface adjacent to the end face of the capacitor body, and each external electrode is formed of a sintered metal layer and a sintered metal layer. In a chip-type capacitor including a Ni plating layer formed on a metal layer, the end face of the capacitor body is parallel to the length direction and the thickness direction and viewed in cross section in a direction orthogonal to the width direction. The thickness T1 of the thinnest portion of the sintered metal layer at the edge with the adjacent other surface is 10 μm
And the thickness T2 of the Ni plating layer on the portion is 6 μm
m or less, and T2> T1 × 0.25.

The chip-type electronic component and the chip-type capacitor according to the present invention preferably further comprise a plating layer formed on the Ni plating layer and made of one of Sn, Pb and Sn-Pb. Can be

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be clarified by specifically describing a chip type electronic component and a multilayer capacitor as a chip type capacitor according to the present invention with reference to the drawings.

FIGS. 1A and 1B are a longitudinal sectional view of a multilayer capacitor according to an embodiment of the present invention and a partially cutaway enlarged sectional view showing a circle A in FIG. The multilayer capacitor 1 is configured using a ceramic sintered body 2. In this embodiment, the multilayer capacitor 1 has a length dimension of about 0.6 mm or less and a width dimension of about 0.3 mm.
Hereinafter, the thickness direction dimension has a dimension of about 0.3 mm or less. Note that the length direction refers to a direction connecting the opposed first and second end faces 2a and 2b of the ceramic sintered body 2, and the thickness direction refers to the upper surface 2c and the lower surface 2d of the ceramic sintered body 2.
And the width direction refers to a direction orthogonal to the length direction and the width direction.

The ceramic sintered body 2 is made of a dielectric ceramic such as a barium titanate ceramic. In the ceramic sintered body 2, a plurality of internal electrodes 3a to 3d are formed so as to overlap with the ceramic sintered body layer interposed therebetween. Internal electrodes 3a, 3c
Are drawn out to the end face 2a, and the internal electrodes 3b, 3d
Is drawn out to the end face 2b.

A first external electrode 4 is formed to cover the end face 2a. The first external electrode 4 includes not only the end face 2a but also another face adjacent to the end face 2a, that is, the upper face 2c,
It is formed so as to reach the lower surface 2d and the pair of side surfaces. The external electrode portion reaching the surface adjacent to the end surface 2a is referred to as an electrode covering portion 4A.

A second external electrode 5 is also formed on the second end face 2b, similarly to the external electrode 4. Second external electrode 5
Also has an electrode covering portion 5A. The first and second external electrodes 4 and 5 have sintered metal layers 4a and 5a formed by applying and baking a conductive paste from the end surfaces 2a and 2b, respectively. As the conductive paste for forming the sintered metal layer, silver paste, copper paste,
A suitable metal powder-containing conductive paste having excellent conductivity, such as a silver-palladium alloy paste, can be used.

On the outer surfaces of the sintered metal layers 4a and 5a, Ni plating layers 4b and 5b are formed by wet plating to prevent solder erosion. Further, Sn plating layers 4c and 5c are formed on the outermost surface, that is, on the outer surfaces of the Ni plating layers 4b and 5b by the same wet plating method in order to enhance solderability.

The Ni plating layers 4b and 5b function as solder erosion prevention layers as described above,
c and 5c function as an easily solderable layer. In this embodiment, the Sn plating film is formed as the solderable layer. However, instead of the Sn plating film, the Sn plating film is made of another material having excellent solderability such as a Sn—Pb alloy plating film or a Pb plating film. A plating film may be formed.

The feature of the multilayer capacitor 1 of this embodiment is that the sintered metal layer 4 on the edge portion in the cross section parallel to the length dimension and the thickness direction, that is, the cross section shown in FIG.
The thickness T1 of the thinnest portion of the a and 5a is 10 μm or less, and the thickness of the Ni plating layers 4b and 5b on the edge portion is also 6 μm or less, and T2> T1 ×
0.25.

As described above, the tombstone phenomenon is likely to occur with the miniaturization of the multilayer capacitor.
Therefore, in order to suppress the tombstone phenomenon, the edges of the ceramic sintered body 2, that is, the end faces 2 a and 2 b
In addition, it is necessary to reduce a processing amount for rounding an edge portion formed by the upper surface 2c, the lower surface 2d, and the pair of side surfaces. The amount of processing of the edge portion is determined by the radius of curvature R of the edge portion in the cross section shown in FIG. 1, that is, the cross section parallel to the length direction and the thickness direction.
Based on the above, the amount is hereinafter referred to as R amount. The smaller the R amount, the more
The smaller the radius of curvature R is, the smaller the roundness is, and the larger the amount of R is, the more rounded the edge is.

As described above, when the tombstone phenomenon is suppressed, the entire multilayer capacitor, that is, the external electrodes 4,
It is necessary to reduce the amount of R at the edge portion after forming No. 5. External electrodes, especially sintered metal layers 4a, 4b
When the thickness of the conductive paste applied to configure the multilayer capacitor 1 is large, the R amount at the edge portion in the final multilayer capacitor 1 increases.

Therefore, it is necessary to apply the conductive paste for forming the sintered metal layers 4a and 5a as thinly and uniformly as possible, and to further reduce the R amount itself at the edge of the ceramic sintered body 2. .

However, when the R amount at the edge of the ceramic sintered body 2 is reduced, the thickness of the conductive paste applied on the edge is reduced, and solder erosion is likely to occur. The inventors of the present application have conducted various studies to achieve both the suppression of the tombstone phenomenon and the prevention of solder erosion, and as a result, as described above, about 0.6 mm or less × about 0.3 mm.
mm or less and about 0.3 mm or less, when the thickness T1 of the thinnest portion of the sintered metal layer is 10
μm or less, the thickness T2 of the Ni plating layer should be 6 μm or less, and T2> T1 × 0.25 should be satisfied. This will be described based on specific experimental examples.

Using the ceramic sintered body 2 having a length dimension of 0.57 mm, a width dimension of 0.27 mm, and a thickness dimension of 0.27 mm, the above R amount at the edge of the ceramic sintered body 2 is shown. Various multilayer capacitors having a radius of curvature of 20 to 25 μm were produced. In this case, the sintered metal layers 4a,
The thickness of 5a is 4 μm or 6 μm, and the thickness of Ni plating layers 4b and 5b is 0.7, 1.0, 1.5 and 2 μm.
Was changed.

Each of the multilayer capacitors obtained as described above was placed on a printed circuit board at a temperature of 250 ° C. for 6 hours.
Soldering is performed under the condition of 0 second, and the sintered metal layers 4a, 5a
The incidence of solder erosion was investigated. The results are shown in Table 1 below.

[0031]

[Table 1]

In Table 1, the rate of occurrence of solder erosion is defined as the rate of occurrence of solder erosion when solder erosion having a diameter of 5 μm or more is present. Show. Heretofore, it has been considered that the thicker the thickness of the sintered metal layer and the thickness of the Ni plating layer, the less likely it is for the sintered metal layer to suffer solder erosion with a diameter of 5 μm or more.

However, in such a very small chip-type multilayer capacitor, when applying a conductive paste by a dipping method, it is very difficult to control the applied thickness of the conductive paste. That is, when the same conductive paste is used, the R amount at the edge of the ceramic sintered body 2 must be changed.

In this case, as shown in FIG. 2A, when the R amount is very small, the applied thickness of the conductive paste 11 at the edge becomes very small. FIG.
As shown in (b), when the R amount is too large, the area of the thin portion becomes large, so that solder erosion easily occurs, and tombstones and the like easily occur in mounting.

On the other hand, as is apparent from Table 1,
The rate of solder erosion depends on the thickness of the sintered metal layers 4a and 5a,
It can be seen that it also changes depending on the ratio of the thickness of the Ni plating layers 4b, 5b. That is, it was confirmed that if T2> T1 × 0.25, solder erosion can be effectively prevented.

Accordingly, a chip using an electronic component element having a length dimension of about 0.6 mm or less, a width dimension of about 0.3 mm or less, and a thickness dimension of 0.3 mm or less as in this embodiment. In the multilayer capacitor, the thickness T1 of the thinnest portion at the edge of the sintered metal layer is 10 μm or less,
The thickness of the Ni plating layer at the edge portion was set to T2 of 6 μm.
In the following cases, by setting T2> T1 × 0.25, solder erosion can be reliably prevented.

The thickness of the Ni plating layers 4b, 5b is set to T
2 is 6 μm or less, the Ni
Cracks due to tightening stress from the plating layers 4b and 5b are unlikely to occur. Furthermore, since it is not necessary to increase the plating current during plating, it is possible to suppress the unevenness of the thickness of the Ni plating layers 4b and 5b and the occurrence of irregularities called pits.

In addition, since the thickness T1 of the thinnest portions of the sintered metal layers 4a and 5a is set to 10 μm or less, tombstone can be suppressed. In the multilayer capacitor 1, when the radius of curvature of the edge portion when viewed from the cross section shown in FIG. 1 exceeds 30 μm, it is difficult to sufficiently secure the film thickness of the external electrode on the edge portion of the element body. . On the other hand, when the radius of curvature of the outer surface of the sintered metal layer at the edge portion exceeds 60 μm, the tombstone phenomenon of the small chip type multilayer capacitor 1 described above tends to occur.

In the above embodiment, the multilayer capacitor is described. However, the chip-type electronic component according to the present invention is not limited to the multilayer capacitor, but has a length dimension of about 0.6 mm or less and a width dimension of about 0.3 mm. Hereinafter, various chip-type electronic components having an electronic component body having a dimension in the thickness direction of about 0.3 mm or less, and having external electrodes formed so as to cover the first and second entire surfaces of the electronic component body. Can be applied.
For example, the present invention can be applied to a chip thermistor, a chip resistor, a chip varistor, and the like.

[0040]

The chip-type electronic component according to the present invention has a length dimension of about 0.6 mm or less and a width dimension of about 0.3 mm.
mm or less, and in a chip-type electronic component using a very small electronic component body having a thickness dimension of approximately 0.3 mm or less, a cross section in a direction parallel to the length direction and the thickness direction and orthogonal to the width direction. When viewed, the thickness T1 of the thinnest portion of the sintered metal layer at the edge between the end surface of the electronic component element body and another adjacent surface is 10 μm or less, and the thickness T2 of the Ni plating layer on the portion is not more than 10 μm. Is 6 μm, and T2> T
Since it is 1 × 0.25, the occurrence of the tombstone phenomenon can be suppressed, and the solder erosion of the sintered metal layer can be effectively suppressed.

In particular, when viewed from the cross section, the radius of curvature of the edge of the electronic component body is 30 μm or less, and the radius of curvature of the outer surface of the sintered metal layer at the edge is 60 μm.
When it is less than m, the film thickness of the external electrode on the element edge can be made sufficiently large, and the tombstone phenomenon can be suppressed more reliably.

In the chip type capacitor according to the present invention, the length dimension is about 0.6 mm or less and the width dimension is about 0.3 mm.
mm or less, and in a chip type capacitor using a very small capacitor body having a thickness dimension of about 0.3 mm or less, the cross section was viewed in a direction parallel to the length direction and the thickness direction and orthogonal to the width direction. In this case, the thickness T1 of the thinnest portion of the sintered metal layer at the edge between the end face of the capacitor body and the other adjacent face is 10 μm or less,
The thickness T2 of the Ni plating layer on this portion is 6 μm,
Since 2> T1 × 0.25, it is possible to suppress the occurrence of the tombstone phenomenon and effectively suppress the solder erosion of the sintered metal layer.

In particular, the radius of curvature of the edge portion of the capacitor element when viewed in cross section is 30 μm or less,
The radius of curvature of the outer surface of the sintered metal layer at the edge is 60
In the case of μm or less, the thickness of the external electrode on the edge portion can be made sufficiently large, and the tombstone phenomenon can be suppressed more reliably.

In the present invention, the S
When the plating layer made of n, Pb or Sn-Pb is formed, the solderability of the external electrodes is improved.

[Brief description of the drawings]

FIGS. 1A and 1B are a longitudinal sectional view of a chip-type multilayer capacitor as a chip-type electronic component according to an embodiment of the present invention, and an enlarged sectional view of a portion indicated by a circle A in FIG. FIG.

FIGS. 2A and 2B are partial cutaway cross-sectional views showing changes in the thickness of a sintered metal layer when the R amount at the edge of the ceramic sintered body is small and large, respectively.

3A and 3B are a longitudinal sectional view showing an example of a conventional multilayer capacitor and an enlarged view of a portion indicated by a circle A in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Multilayer capacitor 2 ... Ceramic sintered body 2a, 2b ... 1st, 2nd end surface 2c ... Upper surface 2d ... Lower surface 3a-3d ... Internal electrode 4, 5 ... 1st, 2nd external electrode 4A, 5A ... Electrode Covering portion 4a, 5a: sintered metal layer 4b, 5b: Ni plating layer 4c, 5c: Sn plating layer

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01G 4/12 361 H01G 4/30 301F 4/30 301 1/14 VF term (Reference) 5E001 AB03 AC04 AD03 AE02 AE03 AF00 AF06 AH01 AH07 AH08 AJ03 5E033 BB09 BG03 BH02 5E034 DA07 DC01 DC05 DC09 DE07 5E082 AA01 AB03 BC40 FG26 FG27 FG52 GG10 GG11 GG26 GG28 JJ03 JJ05 JJ12 JJ21 JJ23 MM23

Claims (5)

[Claims] 1. A longitudinal dimension is about 0.6 mm or less, a width dimension is about 0.3 mm or less, and a thickness dimension is about 0.3 m.
m, and an electronic component body having first and second end faces located at both ends in the length direction, and an end face covering the first and second end faces of the electronic component body, and First and second external electrodes are formed so as to have an electrode covering portion reaching another surface adjacent to the
In a chip-type electronic component in which each external electrode includes a sintered metal layer and a Ni plating layer formed on the sintered metal layer, a direction parallel to the length direction and the thickness direction and orthogonal to the width direction. When viewed in cross section, the end face of the electronic component body,
The thickness T1 of the thinnest portion of the sintered metal layer at the edge with the adjacent other surface is 10 μm or less, and the thickness T2 of the Ni plating layer on the portion is 6 μm or less;
> T1 × 0.25, a chip-type electronic component. 2. An electronic component element according to claim 1, wherein an edge portion of the electronic component body is rounded, and a radius of curvature of the edge portion when viewed in a sectional view is three.
2. The chip-type electronic component according to claim 1, wherein the radius of curvature of the outer surface of the sintered metal layer at the edge portion when viewed in cross section is 60 μm or less. 3. It is formed on the Ni plating layer,
The chip-type electronic component according to claim 1, further comprising a plating layer made of one of Sn, Pb, and Sn—Pb. 4. A longitudinal dimension is about 0.6 mm or less, a width dimension is about 0.3 mm or less, and a thickness dimension is about 0.3 m.
m, and a capacitor body having first and second end faces located at both ends in the length direction; and covering the first and second end faces of the capacitor body and adjacent to the end faces of the capacitor body. First and second external electrodes are formed so as to have an electrode covering portion extending to another surface, and each external electrode is formed of a sintered metal layer and a Ni plating layer formed on the sintered metal layer. In a chip-type capacitor comprising: an end face of the capacitor element body, which is parallel to the length direction and the thickness direction, and when viewed in a cross-section in a direction orthogonal to the width direction, at an edge portion between another adjacent face. The thickness T1 of the thinnest portion of the sintered metal layer is 10 μm or less, the thickness T2 of the Ni plating layer on the portion is 6 μm or less,
A chip-type capacitor, wherein T2> T1 × 0.25. 5. The semiconductor device according to claim 1, wherein said second plating layer is formed on said Ni plating layer.
The chip-type capacitor according to claim 4, further comprising a plating layer made of one of Sn, Pb, and Sn-Pb.