JP2001210545A - Chip electrical component and chip capacitor - Google Patents

Chip electrical component and chip capacitor

Info

Publication number
JP2001210545A
JP2001210545A JP2000017427A JP2000017427A JP2001210545A JP 2001210545 A JP2001210545 A JP 2001210545A JP 2000017427 A JP2000017427 A JP 2000017427A JP 2000017427 A JP2000017427 A JP 2000017427A JP 2001210545 A JP2001210545 A JP 2001210545A
Authority
JP
Japan
Prior art keywords
thickness
less
chip
electronic component
sintered metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000017427A
Other languages
Japanese (ja)
Other versions
JP3630056B2 (en
Inventor
Takashi Nomichi
孝志 野路
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Priority to JP2000017427A priority Critical patent/JP3630056B2/en
Publication of JP2001210545A publication Critical patent/JP2001210545A/en
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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/228Terminals
    • H01G4/232Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H01G4/2325Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals

Abstract

PROBLEM TO BE SOLVED: To provide a chip electrical component which enables effective prevention of both tombstone phenomenon and soldering crack, even if the component is miniaturized further. SOLUTION: This multilayer capacitor is a sintered ceramic 2 of 0.6 mm or smaller length, 0.3 mm or less in width, 0.3 mm or less in thickness as an electronic component, each side surfaces 2a and 2b having external electrodes 4 and 5 which have sintered metal layers 4 and 5, which are laminated with Ni-plated layer 4b and 5b, when viewed in cross-sectional plane from the length and the thickness directions, the thickness of the sintered metal layers 4a, 5b (T1) is 10 μm or less, the thickness of the plated layer 4b and 5b (T2) is 6 μm and T2>T1×0.25.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、例えば積層コンデ
ンサのようなチップ型電子部品及びチップ型コンデンサ
に関し、より詳細には、電子部品素体及び電子部品素体
の外表面に形成される外部電極が改良されたチップ型電
子部品及びチップ型コンデンサに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type electronic component such as a multilayer capacitor and a chip type capacitor, and more particularly, to an electronic component body and an external electrode formed on an outer surface of the electronic component body. To improved chip-type electronic components and chip-type capacitors.

【0002】[0002]

【従来の技術】近年、電子機器の小型化に伴い、積層コ
ンデンサを始めとする様々なチップ型電子部品では、よ
り一層の小型化が求められている。従来、小型のチップ
型積層コンデンサとしては、長さ方向寸法3.2mm×
幅方向寸法1.6mm×厚み方向寸法1.25mmのも
のが広く用いられてきた。この積層コンデンサの構造を
図3(a)及び(b)に示す。
2. Description of the Related Art In recent years, with miniaturization of electronic equipment, further miniaturization of various chip-type electronic components such as multilayer capacitors has been required. Conventionally, as a small chip type multilayer capacitor, the dimension in the length direction is 3.2 mm ×
Those having a dimension in the width direction of 1.6 mm and a dimension in the thickness direction of 1.25 mm have been widely used. FIGS. 3A and 3B show the structure of this multilayer capacitor.

【0003】積層コンデンサ51では、セラミック焼結
体52内に、内部電極53a〜53dが形成されてい
る。内部電極53a,53cと電気的に接続されるよう
に、端面52aに外部電極54が形成されている。ま
た、内部電極53b,53dと電気的に接続されるよう
に、端面52bを覆うように外部電極55が形成されて
いる。
In the multilayer capacitor 51, internal electrodes 53a to 53d are formed in a ceramic sintered body 52. An external electrode 54 is formed on the end face 52a so as to be electrically connected to the internal electrodes 53a and 53c. Further, an external electrode 55 is formed to cover the end face 52b so as to be electrically connected to the internal electrodes 53b and 53d.

【0004】外部電極54,55は、それぞれ、銀ペー
ストを塗布し、焼き付けることにより形成された焼結金
属層54a,55aと、焼結金属層54a,55a上に
湿式メッキにより形成されたNiメッキ層54b,55
bと、Snメッキ層54c,55cとを有する。上記寸
法の積層コンデンサ51では、銀ペーストが、端面52
aまたは52b側から塗布されるが、セラミック焼結体
52のエッジ部において厚みが薄くなりがちであった。
例えば、図3(a)の円Aを拡大して示す図3(b)か
ら明らかなように、銀ペーストの塗布厚みがエッジ部に
おいて相対的に薄くなり、そのため焼結金属層54aの
厚みがエッジ部において薄くなりがちであった。すなわ
ち、端面52a,52bと、端面52a,52bに隣接
する上面52c、下面52d及び側面とのなすエッジ部
において、焼結金属層54a,55aの厚みが薄くなり
がちであった。
The external electrodes 54 and 55 are respectively formed of a sintered metal layer 54a, 55a formed by applying and baking a silver paste, and Ni plating formed by wet plating on the sintered metal layer 54a, 55a. Layers 54b and 55
b and Sn plating layers 54c and 55c. In the multilayer capacitor 51 having the above dimensions, the silver paste is applied to the end face 52.
Although applied from the side of a or 52b, the thickness tends to be thin at the edge of the ceramic sintered body 52.
For example, as is clear from FIG. 3 (b) which shows the circle A in FIG. 3 (a) in an enlarged manner, the applied thickness of the silver paste becomes relatively thin at the edge portion, so that the thickness of the sintered metal layer 54a is reduced. The edges tended to be thin. That is, the thickness of the sintered metal layers 54a and 55a tends to be thin at the edges formed by the end surfaces 52a and 52b and the upper surface 52c, the lower surface 52d and the side surfaces adjacent to the end surfaces 52a and 52b.

【0005】エッジ部において、焼結金属層54a,5
4bの厚みが薄くなると、プリント回路基板などに実装
する際に、焼結金属層54a,54bの半田喰われが生
じ易くなる。
At the edges, the sintered metal layers 54a, 54
When the thickness of 4b is reduced, the solder erosion of the sintered metal layers 54a and 54b is likely to occur when mounting on a printed circuit board or the like.

【0006】従って、従来、エッジ部をバレル研磨等に
より丸め、それによってエッジ部における焼結金属層5
4a,54bの厚みを増大させることが試みられてい
る。しかしながら、積層コンデンサ51の小型化が進む
につれて、溶融半田を用いてプリント回路基板などに実
装する場合に溶融半田の表面張力によりチップ型積層コ
ンデンサ51が一方の外部電極54,55が上方を向く
ように起立する、いわゆるツームストーン現象が生じが
ちとなる。
Therefore, conventionally, the edge portion is rounded by barrel polishing or the like, whereby the sintered metal layer 5 at the edge portion is rounded.
Attempts have been made to increase the thickness of 4a, 54b. However, as the miniaturization of the multilayer capacitor 51 progresses, when mounting on a printed circuit board or the like using the molten solder, the chip-type multilayer capacitor 51 causes one of the external electrodes 54 and 55 to face upward due to the surface tension of the molten solder. , The so-called tombstone phenomenon tends to occur.

【0007】他方、上記のように、セラミック焼結体5
2のエッジ部を丸めるための研磨量が小さくなると、半
田喰われが生じ易くなる。そこで、積層コンデンサ51
では、半田喰われを防止するために、焼結金属層54
a,55aの表面にNiメッキ層54b,55bが形成
されている。このNiメッキ層54b,55bの厚みは
通常1〜2μm程度であり、ほぼ均一な厚みに形成され
ている。上記半田喰われを防止するには、Niメッキ層
の厚みを厚くすることが好ましい。
On the other hand, as described above, the ceramic sintered body 5
When the amount of polishing for rounding the edge portion 2 is small, solder erosion is likely to occur. Therefore, the multilayer capacitor 51
Then, in order to prevent solder erosion, the sintered metal layer 54
The Ni plating layers 54b and 55b are formed on the surfaces of the a and 55a. The thickness of each of the Ni plating layers 54b and 55b is generally about 1 to 2 μm, and is formed to have a substantially uniform thickness. In order to prevent the solder erosion, it is preferable to increase the thickness of the Ni plating layer.

【0008】他方、湿式メッキ法により形成されたNi
メッキ層54b,55bは、セラミック焼結体52に締
め付け応力を与える。従って、半田喰われを防止するた
めに、Niメッキ層54b,55bの厚みを厚くする
と、セラミック焼結体52にクラック等が発生しがちと
なる。特に、Niメッキ層の厚みを6μmより厚くした
場合、上記クラックが生じ易くなることがわかってい
る。
On the other hand, Ni formed by a wet plating method
The plating layers 54b and 55b apply a tightening stress to the ceramic sintered body 52. Therefore, if the thickness of the Ni plating layers 54b and 55b is increased in order to prevent solder erosion, cracks and the like tend to occur in the ceramic sintered body 52. In particular, it has been found that when the thickness of the Ni plating layer is larger than 6 μm, the cracks are easily generated.

【0009】加えて、Niメッキ層54b,55bの厚
みを厚くするために、湿式メッキ時に流す電流を大きく
すると、Niメッキ層54b,55bの厚みばらつきが
生じ易くなる。また、水素が発生するために、Niメッ
キ層54b,55b表面に、ピットと称されている凹凸
が発生し易くなる。
In addition, if the current flowing during wet plating is increased in order to increase the thickness of the Ni plating layers 54b and 55b, thickness variations of the Ni plating layers 54b and 55b tend to occur. In addition, since hydrogen is generated, irregularities called pits easily occur on the surfaces of the Ni plating layers 54b and 55b.

【0010】他方、厚みが薄くなりがちである上記エッ
ジ部上において、焼結金属層54a,55aを構成する
ための銀ペースト塗布厚みを厚くした場合には、エッジ
部上において外部電極54,55の丸みが大きくなり、
やはり前述したツームストーン現象が発生しがちとな
る。
On the other hand, when the thickness of the silver paste applied to form the sintered metal layers 54a and 55a is increased on the edge portion where the thickness tends to be small, the external electrodes 54 and 55 are formed on the edge portion. Becomes larger,
Again, the tombstone phenomenon described above tends to occur.

【0011】一般に、電子部品の外部電極では、膜厚が
均一であることが求められている。しかしながら、上記
外部電極54,55では、焼結金属層54a,55a
は、ペースト浸漬法により銀ペーストを塗布することに
より形成されることが多い。従って、上記のように、導
電ペースト塗布厚みを大きくすると、外部電極54,5
5のエッジ部上における丸みが大きくなり、ツームスト
ーン現象が発生し易くなる。逆に、導電ペースト塗布厚
みを薄くした場合には、エッジ部上においてさらに焼結
金属層54a,55aの厚みが薄くなり、半田喰われが
発生し易くなる。
In general, external electrodes of electronic components are required to have a uniform thickness. However, in the external electrodes 54 and 55, the sintered metal layers 54a and 55a
Is often formed by applying a silver paste by a paste dipping method. Therefore, as described above, when the thickness of the conductive paste applied is increased, the external electrodes 54, 5
The roundness on the edge portion of No. 5 becomes large, and the tombstone phenomenon easily occurs. Conversely, when the conductive paste application thickness is reduced, the thickness of the sintered metal layers 54a and 55a on the edge portion is further reduced, and solder erosion is likely to occur.

【0012】よって、本発明の目的は、さらに小型化を
進めた場合であっても、プリント回路基板などに実装す
る際のツームストーン現象を確実に防止することがで
き、かつエッジ部における半田喰われを防止し得るチッ
プ型電子部品及びチップ型コンデンサを提供することに
ある。
[0012] Therefore, an object of the present invention is to prevent the tombstone phenomenon at the time of mounting on a printed circuit board or the like, and to prevent the solder erosion at the edge portion even when the size is further reduced. It is an object of the present invention to provide a chip-type electronic component and a chip-type capacitor that can prevent cracks.

【0013】[0013]

【課題を解決するための手段】本発明に係るチップ型電
子部品は、長手方向寸法が略0.6mm以下、幅方向寸
法が略0.3mm以下、厚み方向寸法が略0.3mm以
下であり、長さ方向両端に位置する第1,第2の端面を
有する電子部品素体と、前記電子部品素体の第1,第2
の端面を覆い、かつ電子部品素体の端面に隣接する他の
面に至る電極被り部を有するように、第1,第2の外部
電極が形成されており、各外部電極が、焼結金属層と、
焼結金属層上に形成されたNiメッキ層とを備えるチッ
プ型電子部品において、前記長さ方向及び厚み方向と平
行であり、幅方向と直交する方向に断面視した場合に、
電子部品素体の端面と、隣接する他の面とのエッジ部に
おける前記焼結金属層の最も薄い部分の厚みT1が10
μm以下であり、該部分上のNiメッキ層の厚みT2が
6μm以下であり、T2>T1×0.25であることを
特徴とする。
The chip-type electronic component according to the present invention has a longitudinal dimension of about 0.6 mm or less, a width dimension of about 0.3 mm or less, and a thickness dimension of about 0.3 mm or less. An electronic component body having first and second end faces located at both ends in the length direction, and first and second electronic component bodies.
The first and second external electrodes are formed so as to cover an end surface of the electronic component body and have an electrode covering portion extending to another surface adjacent to the end surface of the electronic component body. Layers and
In a chip-type electronic component including a Ni plating layer formed on a sintered metal layer, when viewed in a cross section in a direction parallel to the length direction and the thickness direction and orthogonal to the width direction,
The thickness T1 of the thinnest portion of the sintered metal layer at the edge between the end face of the electronic component body and the other adjacent face is 10
μm or less, the thickness T2 of the Ni plating layer on the portion is 6 μm or less, and T2> T1 × 0.25.

【0014】本発明に係るチップ型電子部品の特定の局
面では、前記電子部品素体のエッジ部が丸められてお
り、前記断面視した場合のエッジ部の曲率半径が30μ
m以下であり、上記断面視した場合のエッジ部における
焼結金属層の外表面の曲率半径が60μm以下である。
In a specific aspect of the chip-type electronic component according to the present invention, the edge of the electronic component body is rounded, and the edge has a radius of curvature of 30 μm when viewed in cross section.
m or less, and the radius of curvature of the outer surface of the sintered metal layer at the edge when viewed in cross section is 60 μm or less.

【0015】本発明に係るチップ型コンデンサは、長手
方向寸法が略0.6mm以下、幅方向寸法が略0.3m
m以下、厚み方向寸法が略0.3mm以下であり、長さ
方向両端に位置する第1,第2の端面を有するコンデン
サ素体と、前記コンデンサ素体の第1,第2の端面を覆
い、かつコンデンサ素体の端面に隣接する他の面に至る
電極被り部を有するように、第1,第2の外部電極が形
成されており、各外部電極が、焼結金属層と、焼結金属
層上に形成されたNiメッキ層とを備えるチップ型コン
デンサにおいて、前記長さ方向及び厚み方向と平行であ
り、幅方向と直交する方向に断面視した場合に、コンデ
ンサ素体の端面と、隣接する他の面とのエッジ部におけ
る前記焼結金属層の最も薄い部分の厚みT1が10μm
以下であり、該部分上のNiメッキ層の厚みT2が6μ
m以下であり、T2>T1×0.25であることを特徴
とする。
The chip type capacitor according to the present invention has a longitudinal dimension of about 0.6 mm or less and a width dimension of about 0.3 m.
m, a thickness in the thickness direction of about 0.3 mm or less, and a capacitor body having first and second end faces located at both ends in the length direction, and covering the first and second end faces of the capacitor body. And first and second external electrodes are formed so as to have an electrode covering portion extending to another surface adjacent to the end face of the capacitor body, and each external electrode is formed of a sintered metal layer and a sintered metal layer. In a chip-type capacitor including a Ni plating layer formed on a metal layer, the end face of the capacitor body is parallel to the length direction and the thickness direction and viewed in cross section in a direction orthogonal to the width direction. The thickness T1 of the thinnest portion of the sintered metal layer at the edge with the adjacent other surface is 10 μm
And the thickness T2 of the Ni plating layer on the portion is 6 μm
m or less, and T2> T1 × 0.25.

【0016】本発明に係るチップ型電子部品及びチップ
型コンデンサでは、好ましくは、前記Niメッキ層上に
形成されており、かつSn、Pb及びSn−Pbのうち
1種からなるメッキ層がさらに備えられる。
The chip-type electronic component and the chip-type capacitor according to the present invention preferably further comprise a plating layer formed on the Ni plating layer and made of one of Sn, Pb and Sn-Pb. Can be

【0017】[0017]

【発明の実施の形態】以下、図面を参照しつつ本発明に
係るチップ型電子部品及びチップ型コンデンサとしての
積層コンデンサを具体的に説明することにより、本発明
を明らかにする。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be clarified by specifically describing a chip type electronic component and a multilayer capacitor as a chip type capacitor according to the present invention with reference to the drawings.

【0018】図1(a)及び(b)は、本発明の一実施
例に係る積層コンデンサの縦断面図及び(a)における
円Aを拡大して示す部分切欠拡大断面図である。積層コ
ンデンサ1は、セラミック焼結体2を用いて構成されて
いる。本実施例では、上記積層コンデンサ1は、長さ方
向寸法が略0.6mm以下、幅方向寸法が略0.3mm
以下、厚み方向寸法が略0.3mm以下の寸法を有す
る。なお、長さ方向とは、セラミック焼結体2の対向し
合う第1,第2の端面2a,2bを結ぶ方向をいい、厚
み方向とは、セラミック焼結体2の上面2cと下面2d
とを結ぶ方向をいい、幅方向とは、長さ方向及び幅方向
と直交する方向をいうものとする。
FIGS. 1A and 1B are a longitudinal sectional view of a multilayer capacitor according to an embodiment of the present invention and a partially cutaway enlarged sectional view showing a circle A in FIG. The multilayer capacitor 1 is configured using a ceramic sintered body 2. In this embodiment, the multilayer capacitor 1 has a length dimension of about 0.6 mm or less and a width dimension of about 0.3 mm.
Hereinafter, the thickness direction dimension has a dimension of about 0.3 mm or less. Note that the length direction refers to a direction connecting the opposed first and second end faces 2a and 2b of the ceramic sintered body 2, and the thickness direction refers to the upper surface 2c and the lower surface 2d of the ceramic sintered body 2.
And the width direction refers to a direction orthogonal to the length direction and the width direction.

【0019】セラミック焼結体2は、例えばチタン酸バ
リウム系セラミックスのような誘電体セラミックスによ
り構成されている。セラミック焼結体2内には、セラミ
ック焼結体層を介して重なり合うように、複数の内部電
極3a〜3dが形成されている。内部電極3a,3c
は、端面2aに引き出されており、内部電極3b,3d
は端面2bに引き出されている。
The ceramic sintered body 2 is made of a dielectric ceramic such as a barium titanate ceramic. In the ceramic sintered body 2, a plurality of internal electrodes 3a to 3d are formed so as to overlap with the ceramic sintered body layer interposed therebetween. Internal electrodes 3a, 3c
Are drawn out to the end face 2a, and the internal electrodes 3b, 3d
Is drawn out to the end face 2b.

【0020】端面2aを覆うように第1の外部電極4が
形成されている。第1の外部電極4は、端面2aだけで
なく、端面2aに隣接する他の面、すなわち上面2c、
下面2d及び一対の側面にも至るように形成されてい
る。この端面2aに隣接している面に至っている外部電
極部分を電極被り部4Aとする。
A first external electrode 4 is formed to cover the end face 2a. The first external electrode 4 includes not only the end face 2a but also another face adjacent to the end face 2a, that is, the upper face 2c,
It is formed so as to reach the lower surface 2d and the pair of side surfaces. The external electrode portion reaching the surface adjacent to the end surface 2a is referred to as an electrode covering portion 4A.

【0021】第2の端面2bにも、外部電極4と同様に
第2の外部電極5が形成されている。第2の外部電極5
もまた、電極被り部5Aを有する。第1,第2の外部電
極4,5は、それぞれ、端面2a,2b側から導電ペー
ストを塗布し、焼き付けることにより形成された焼結金
属層4a,5aを有する。焼結金属層を構成するための
上記導電ペーストとしては、銀ペースト、銅ペースト、
銀−パラジウム合金ペーストなど、適宜の導電性に優れ
た金属粉末含有導電ペーストを用いることができる。
A second external electrode 5 is also formed on the second end face 2b, similarly to the external electrode 4. Second external electrode 5
Also has an electrode covering portion 5A. The first and second external electrodes 4 and 5 have sintered metal layers 4a and 5a formed by applying and baking a conductive paste from the end surfaces 2a and 2b, respectively. As the conductive paste for forming the sintered metal layer, silver paste, copper paste,
A suitable metal powder-containing conductive paste having excellent conductivity, such as a silver-palladium alloy paste, can be used.

【0022】また、焼結金属層4a,5aの外表面に
は、湿式メッキ法により、半田喰われを防止するために
Niメッキ層4b,5bが形成されている。さらに、最
外側表面には、すなわちNiメッキ層4b,5bの外側
表面には、同じく湿式メッキ法により、半田付け性を高
めるために、Snメッキ層4c,5cが形成されてい
る。
On the outer surfaces of the sintered metal layers 4a and 5a, Ni plating layers 4b and 5b are formed by wet plating to prevent solder erosion. Further, Sn plating layers 4c and 5c are formed on the outermost surface, that is, on the outer surfaces of the Ni plating layers 4b and 5b by the same wet plating method in order to enhance solderability.

【0023】上記Niメッキ層4b,5bが、上記のよ
うに半田喰われ防止層として機能し、Snメッキ層4
c,5cが易半田付け性層として作用する。なお、本実
施例では、易半田付け性層としてSnメッキ膜を形成し
たが、Snメッキ膜に変えて、Sn−Pb合金メッキ膜
やPbメッキ膜など他の半田付け性に優れた材料からな
るメッキ膜を形成してもよい。
The Ni plating layers 4b and 5b function as solder erosion prevention layers as described above,
c and 5c function as an easily solderable layer. In this embodiment, the Sn plating film is formed as the solderable layer. However, instead of the Sn plating film, the Sn plating film is made of another material having excellent solderability such as a Sn—Pb alloy plating film or a Pb plating film. A plating film may be formed.

【0024】本実施例の積層コンデンサ1の特徴は、長
さ方向寸法と厚み方向に平行な断面、すなわち図1に示
されている断面において、エッジ部上の焼結金属層4
a,5aの最も薄い部分の厚みT1が10μm以下であ
り、かつNiメッキ層4b,5bの同じくエッジ部上に
おける厚みが6μm以下とされており、T2>T1×
0.25とされていることにある。
The feature of the multilayer capacitor 1 of this embodiment is that the sintered metal layer 4 on the edge portion in the cross section parallel to the length dimension and the thickness direction, that is, the cross section shown in FIG.
The thickness T1 of the thinnest portion of the a and 5a is 10 μm or less, and the thickness of the Ni plating layers 4b and 5b on the edge portion is also 6 μm or less, and T2> T1 ×
0.25.

【0025】前述したように、積層コンデンサの小型化
に伴って、ツームストーン現象が生じ易くなっている。
従って、上記ツームストーン現象を抑制するには、セラ
ミック焼結体2のエッジ部、すなわち端面2a,2b
と、上面2c、下面2d及び一対の側面とのなす端縁部
分を丸める加工量を小さくする必要がある。このエッジ
部の加工量を、図1に示した断面、すなわち長さ方向及
び厚み方向に平行な断面におけるエッジ部の曲率半径R
に基づき、以下、R量とする。このR量が小さいほど、
曲率半径Rが小さく、従って丸みが少なく、R量が大き
いほど、エッジ部が大きく丸められていることになる。
As described above, the tombstone phenomenon is likely to occur with the miniaturization of the multilayer capacitor.
Therefore, in order to suppress the tombstone phenomenon, the edges of the ceramic sintered body 2, that is, the end faces 2 a and 2 b
In addition, it is necessary to reduce a processing amount for rounding an edge portion formed by the upper surface 2c, the lower surface 2d, and the pair of side surfaces. The amount of processing of the edge portion is determined by the radius of curvature R of the edge portion in the cross section shown in FIG. 1, that is, the cross section parallel to the length direction and the thickness direction.
Based on the above, the amount is hereinafter referred to as R amount. The smaller the R amount, the more
The smaller the radius of curvature R is, the smaller the roundness is, and the larger the amount of R is, the more rounded the edge is.

【0026】上記のように、ツームストーン現象を抑制
する場合、積層コンデンサ全体、すなわち外部電極4,
5を形成した後におけるエッジ部におけるR量を小さく
する必要がある。外部電極、特に焼結金属層4a,4b
を構成するための導電ペースト塗布厚みが多い場合に
は、最終的な積層コンデンサ1におけるエッジ部におけ
るR量が大きくなる。
As described above, when the tombstone phenomenon is suppressed, the entire multilayer capacitor, that is, the external electrodes 4,
It is necessary to reduce the amount of R at the edge portion after forming No. 5. External electrodes, especially sintered metal layers 4a, 4b
When the thickness of the conductive paste applied to configure the multilayer capacitor 1 is large, the R amount at the edge portion in the final multilayer capacitor 1 increases.

【0027】従って、焼結金属層4a,5aを形成する
ための導電ペーストが、可能なかぎり薄くかつ均一に塗
布し、さらにセラミック焼結体2のエッジ部のR量自体
も小さくする必要がある。
Therefore, it is necessary to apply the conductive paste for forming the sintered metal layers 4a and 5a as thinly and uniformly as possible, and to further reduce the R amount itself at the edge of the ceramic sintered body 2. .

【0028】しかしながら、セラミック焼結体2のエッ
ジ部のR量が小さくなると、導電ペーストのエッジ部上
の塗布厚みが薄くなり、半田喰われが生じ易くなる。そ
こで、本願発明者らは、上記ツームストーン現象の抑制
と、半田喰われの防止の双方を果たすために、種々検討
した結果、上記のように、略0.6mm以下×略0.3
mm以下×略0.3mm以下のセラミック焼結体2を用
いた場合、焼結金属層の最も薄い部分の厚みT1を10
μm以下とし、Niメッキ層の厚みT2を6μm以下と
し、T2>T1×0.25とすればよいことを見い出し
た。これを、具体的な実験例に基づき説明する。
However, when the R amount at the edge of the ceramic sintered body 2 is reduced, the thickness of the conductive paste applied on the edge is reduced, and solder erosion is likely to occur. The inventors of the present application have conducted various studies to achieve both the suppression of the tombstone phenomenon and the prevention of solder erosion, and as a result, as described above, about 0.6 mm or less × about 0.3 mm.
mm or less and about 0.3 mm or less, when the thickness T1 of the thinnest portion of the sintered metal layer is 10
μm or less, the thickness T2 of the Ni plating layer should be 6 μm or less, and T2> T1 × 0.25 should be satisfied. This will be described based on specific experimental examples.

【0029】長さ方向寸法が0.57mm、幅方向寸法
が0.27mm、厚み方向寸法が0.27mmのセラミ
ック焼結体2を用い、セラミック焼結体2のエッジ部の
上記R量を示す曲率半径が20〜25μmである積層コ
ンデンサを種々作製した。この場合、焼結金属層4a,
5aの厚みを4μmあるいは6μmとし、Niメッキ層
4b,5bの厚みを0.7、1.0、1.5及び2μm
と変化させた。
Using the ceramic sintered body 2 having a length dimension of 0.57 mm, a width dimension of 0.27 mm, and a thickness dimension of 0.27 mm, the above R amount at the edge of the ceramic sintered body 2 is shown. Various multilayer capacitors having a radius of curvature of 20 to 25 μm were produced. In this case, the sintered metal layers 4a,
The thickness of 5a is 4 μm or 6 μm, and the thickness of Ni plating layers 4b and 5b is 0.7, 1.0, 1.5 and 2 μm.
Was changed.

【0030】上記のようにして得られた各積層コンデン
サについて、プリント回路基板上に250℃の温度で6
0秒間の条件で半田付けを行い、焼結金属層4a,5a
の半田喰われ発生率を調査した。結果を下記の表1に示
す。
Each of the multilayer capacitors obtained as described above was placed on a printed circuit board at a temperature of 250 ° C. for 6 hours.
Soldering is performed under the condition of 0 second, and the sintered metal layers 4a, 5a
The incidence of solder erosion was investigated. The results are shown in Table 1 below.

【0031】[0031]

【表1】 [Table 1]

【0032】なお、表1において、半田喰われ発生率
は、直径5μm以上の半田喰われが存在する場合に半田
喰われが発生したものとし、各積層コンデンサ50個あ
たりの半田喰われ発生率を示す。これまで、焼結金属層
の厚み及びNiメッキ層の厚みが厚いほど、焼結金属層
に直径5μm以上の半田喰われが生じ難いと考えられて
いた。
In Table 1, the rate of occurrence of solder erosion is defined as the rate of occurrence of solder erosion when solder erosion having a diameter of 5 μm or more is present. Show. Heretofore, it has been considered that the thicker the thickness of the sintered metal layer and the thickness of the Ni plating layer, the less likely it is for the sintered metal layer to suffer solder erosion with a diameter of 5 μm or more.

【0033】しかしながら、このように非常に小さなチ
ップ型積層コンデンサにおいて、導電ペーストをディッ
ピング法により付与する場合、該導電ペーストの塗布厚
みを制御するのは非常に難しい。すなわち、同じ導電ペ
ーストを用いる場合、セラミック焼結体2のエッジ部の
R量を変化させねばならない。
However, in such a very small chip-type multilayer capacitor, when applying a conductive paste by a dipping method, it is very difficult to control the applied thickness of the conductive paste. That is, when the same conductive paste is used, the R amount at the edge of the ceramic sintered body 2 must be changed.

【0034】この場合、図2(a)に示すように、R量
が非常に小さい場合には、エッジ部において、導電ペー
スト11の塗布厚みが非常に薄くなる。また、図2
(b)に示すように、R量が大き過ぎる場合には、薄い
部分の面積が大きくなるため半田喰われが発生し易くな
ったり、また実装上ではツームストーン等が起き易くな
る。
In this case, as shown in FIG. 2A, when the R amount is very small, the applied thickness of the conductive paste 11 at the edge becomes very small. FIG.
As shown in (b), when the R amount is too large, the area of the thin portion becomes large, so that solder erosion easily occurs, and tombstones and the like easily occur in mounting.

【0035】これに対して、表1から明らかなように、
半田喰われ発生率は、焼結金属層4a,5aの厚みと、
Niメッキ層4b,5bの厚みの比によっても変化する
ことがわかる。すなわち、T2>T1×0.25とすれ
ば、半田喰われを効果的に防止し得ることが確かめられ
た。
On the other hand, as is apparent from Table 1,
The rate of solder erosion depends on the thickness of the sintered metal layers 4a and 5a,
It can be seen that it also changes depending on the ratio of the thickness of the Ni plating layers 4b, 5b. That is, it was confirmed that if T2> T1 × 0.25, solder erosion can be effectively prevented.

【0036】従って、本実施例のように長さ方向寸法が
略0.6mm以下、幅方向寸法が略0.3mm以下、及
び厚み方向寸法が0.3mm以下の電子部品素体を用い
たチップ型積層コンデンサにおいて、焼結金属層のエッ
ジ部における最も薄い部分の厚みT1を10μm以下、
該エッジ部におけるNiメッキ層の厚みをT2を6μm
以下とした場合、T2>T1×0.25とすることによ
り、半田喰われを確実に防止することができる。
Accordingly, a chip using an electronic component element having a length dimension of about 0.6 mm or less, a width dimension of about 0.3 mm or less, and a thickness dimension of 0.3 mm or less as in this embodiment. In the multilayer capacitor, the thickness T1 of the thinnest portion at the edge of the sintered metal layer is 10 μm or less,
The thickness of the Ni plating layer at the edge portion was set to T2 of 6 μm.
In the following cases, by setting T2> T1 × 0.25, solder erosion can be reliably prevented.

【0037】また、Niメッキ層4b,5bの厚みをT
2が6μm以下であるため、セラミック焼結体2のNi
メッキ層4b,5bからの締め付け応力によるクラック
も生じ難い。さらに、メッキに際しメッキ電流を大きく
する必要がないため、Niメッキ層4b,5bの厚みば
らつきやピットと称されている凹凸の発生も抑制するこ
とができる。
The thickness of the Ni plating layers 4b, 5b is set to T
2 is 6 μm or less, the Ni
Cracks due to tightening stress from the plating layers 4b and 5b are unlikely to occur. Furthermore, since it is not necessary to increase the plating current during plating, it is possible to suppress the unevenness of the thickness of the Ni plating layers 4b and 5b and the occurrence of irregularities called pits.

【0038】加えて、焼結金属層4a,5aの最も薄い
部分の厚みT1が10μm以下とされているので、ツー
ムストーンを抑制することができる。なお、上記積層コ
ンデンサ1において、図1に示した断面から見た場合の
エッジ部の曲率半径が30μmを超えると、素体のエッ
ジ部上での外部電極の膜厚を十分に確保し難くなる。ま
た、エッジ部における焼結金属層の外表面の曲率半径が
60μmを超えると、上記のような小型のチップ型積層
コンデンサ1のツームストーン現象が生じ易くなる。
In addition, since the thickness T1 of the thinnest portions of the sintered metal layers 4a and 5a is set to 10 μm or less, tombstone can be suppressed. In the multilayer capacitor 1, when the radius of curvature of the edge portion when viewed from the cross section shown in FIG. 1 exceeds 30 μm, it is difficult to sufficiently secure the film thickness of the external electrode on the edge portion of the element body. . On the other hand, when the radius of curvature of the outer surface of the sintered metal layer at the edge portion exceeds 60 μm, the tombstone phenomenon of the small chip type multilayer capacitor 1 described above tends to occur.

【0039】上記実施例では、積層コンデンサについて
説明したが、本発明に係るチップ型電子部品は、積層コ
ンデンサだけでなく、長さ方向寸法が略0.6mm以
下、幅方向寸法が略0.3mm以下、厚み方向寸法略
0.3mm以下の電子部品素体を有し、該電子部品素体
の第1,第2の全面を覆うように外部電極が形成されて
いる様々なチップ型電子部品に適用することができる。
例えば、チップ型サーミスタ、チップ型抵抗素子、チッ
プ型バリスタなどにも適用することができる。
In the above embodiment, the multilayer capacitor is described. However, the chip-type electronic component according to the present invention is not limited to the multilayer capacitor, but has a length dimension of about 0.6 mm or less and a width dimension of about 0.3 mm. Hereinafter, various chip-type electronic components having an electronic component body having a dimension in the thickness direction of about 0.3 mm or less, and having external electrodes formed so as to cover the first and second entire surfaces of the electronic component body. Can be applied.
For example, the present invention can be applied to a chip thermistor, a chip resistor, a chip varistor, and the like.

【0040】[0040]

【発明の効果】本発明に係るチップ型電子部品では、長
さ方向寸法が略0.6mm以下、幅方向寸法が略0.3
mm以下、及び厚み方向寸法が略0.3mm以下である
非常に小さい電子部品素体を用いたチップ型電子部品に
おいて、長さ方向及び厚み方向と平行であり、幅方向と
直交する方向に断面視した場合に、電子部品素体の端面
と、隣接する他の面とのエッジ部における焼結金属層の
最も薄い部分の厚みT1が10μm以下であり、該部分
上のNiメッキ層の厚みT2が6μmであり、T2>T
1×0.25とされているので、ツームストーン現象の
発生を抑制し得るとともに、焼結金属層の半田喰われを
効果的に抑制することができる。
The chip-type electronic component according to the present invention has a length dimension of about 0.6 mm or less and a width dimension of about 0.3 mm.
mm or less, and in a chip-type electronic component using a very small electronic component body having a thickness dimension of approximately 0.3 mm or less, a cross section in a direction parallel to the length direction and the thickness direction and orthogonal to the width direction. When viewed, the thickness T1 of the thinnest portion of the sintered metal layer at the edge between the end surface of the electronic component element body and another adjacent surface is 10 μm or less, and the thickness T2 of the Ni plating layer on the portion is not more than 10 μm. Is 6 μm, and T2> T
Since it is 1 × 0.25, the occurrence of the tombstone phenomenon can be suppressed, and the solder erosion of the sintered metal layer can be effectively suppressed.

【0041】また、特に、上記断面視した場合の電子部
品素体のエッジ部の曲率半径が30μm以下であり、エ
ッジ部における焼結金属層の外表面の曲率半径が60μ
m以下の場合には、外部電極の素体エッジ部上における
膜厚を十分な大きさとすることができ、かつツームスト
ーン現象をより確実に抑制することができる。
In particular, when viewed from the cross section, the radius of curvature of the edge of the electronic component body is 30 μm or less, and the radius of curvature of the outer surface of the sintered metal layer at the edge is 60 μm.
When it is less than m, the film thickness of the external electrode on the element edge can be made sufficiently large, and the tombstone phenomenon can be suppressed more reliably.

【0042】本発明に係るチップ型コンデンサでは、長
さ方向寸法が略0.6mm以下、幅方向寸法が略0.3
mm以下、及び厚み方向寸法が略0.3mm以下である
非常に小さいコンデンサ素体を用いたチップ型コンデン
サにおいて、長さ方向及び厚み方向と平行であり、幅方
向と直交する方向に断面視した場合に、コンデンサ素体
の端面と、隣接する他の面とのエッジ部における焼結金
属層の最も薄い部分の厚みT1が10μm以下であり、
該部分上のNiメッキ層の厚みT2が6μmであり、T
2>T1×0.25とされているので、ツームストーン
現象の発生を抑制し得るとともに、焼結金属層の半田喰
われを効果的に抑制することができる。
In the chip type capacitor according to the present invention, the length dimension is about 0.6 mm or less and the width dimension is about 0.3 mm.
mm or less, and in a chip type capacitor using a very small capacitor body having a thickness dimension of about 0.3 mm or less, the cross section was viewed in a direction parallel to the length direction and the thickness direction and orthogonal to the width direction. In this case, the thickness T1 of the thinnest portion of the sintered metal layer at the edge between the end face of the capacitor body and the other adjacent face is 10 μm or less,
The thickness T2 of the Ni plating layer on this portion is 6 μm,
Since 2> T1 × 0.25, it is possible to suppress the occurrence of the tombstone phenomenon and effectively suppress the solder erosion of the sintered metal layer.

【0043】また、特に、上記断面視した場合のコンデ
ンサ素体のエッジ部の曲率半径が30μm以下であり、
エッジ部における焼結金属層の外表面の曲率半径が60
μm以下の場合には、エッジ部上の外部電極の膜厚を十
分な大きさとすることができ、かつツームストーン現象
をより確実に抑制することができる。
In particular, the radius of curvature of the edge portion of the capacitor element when viewed in cross section is 30 μm or less,
The radius of curvature of the outer surface of the sintered metal layer at the edge is 60
In the case of μm or less, the thickness of the external electrode on the edge portion can be made sufficiently large, and the tombstone phenomenon can be suppressed more reliably.

【0044】本発明において、Niメッキ層上に、S
n、PbまたはSn−Pbからなるメッキ層が形成され
ている場合には、外部電極の半田付け性が高められる。
In the present invention, the S
When the plating layer made of n, Pb or Sn-Pb is formed, the solderability of the external electrodes is improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)及び(b)は、本発明の一実施例に係る
チップ型電子部品としてのチップ型積層コンデンサの縦
断面図及び(a)中の円Aで示した部分の拡大断面図。
FIGS. 1A and 1B are a longitudinal sectional view of a chip-type multilayer capacitor as a chip-type electronic component according to an embodiment of the present invention, and an enlarged sectional view of a portion indicated by a circle A in FIG. FIG.

【図2】(a)及び(b)は、それぞれ、セラミック焼
結体のエッジ部のR量が小さい場合及び大きい場合の焼
結金属層の膜厚の変化を示す各部分切欠断面図。
FIGS. 2A and 2B are partial cutaway cross-sectional views showing changes in the thickness of a sintered metal layer when the R amount at the edge of the ceramic sintered body is small and large, respectively.

【図3】(a)及び(b)は、従来の積層コンデンサの
一例を示す縦断面図及び(a)中の円Aで示した部分の
拡大図。
3A and 3B are a longitudinal sectional view showing an example of a conventional multilayer capacitor and an enlarged view of a portion indicated by a circle A in FIG.

【符号の説明】[Explanation of symbols]

1…積層コンデンサ 2…セラミック焼結体 2a,2b…第1,第2の端面 2c…上面 2d…下面 3a〜3d…内部電極 4,5…第1,第2の外部電極 4A,5A…電極被り部 4a,5a…焼結金属層 4b,5b…Niメッキ層 4c,5c…Snメッキ層 DESCRIPTION OF SYMBOLS 1 ... Multilayer capacitor 2 ... Ceramic sintered body 2a, 2b ... 1st, 2nd end surface 2c ... Upper surface 2d ... Lower surface 3a-3d ... Internal electrode 4, 5 ... 1st, 2nd external electrode 4A, 5A ... Electrode Covering portion 4a, 5a: sintered metal layer 4b, 5b: Ni plating layer 4c, 5c: Sn plating layer

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01G 4/12 361 H01G 4/30 301F 4/30 301 1/14 V Fターム(参考) 5E001 AB03 AC04 AD03 AE02 AE03 AF00 AF06 AH01 AH07 AH08 AJ03 5E033 BB09 BG03 BH02 5E034 DA07 DC01 DC05 DC09 DE07 5E082 AA01 AB03 BC40 FG26 FG27 FG52 GG10 GG11 GG26 GG28 JJ03 JJ05 JJ12 JJ21 JJ23 MM24 PP09 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01G 4/12 361 H01G 4/30 301F 4/30 301 1/14 VF term (Reference) 5E001 AB03 AC04 AD03 AE02 AE03 AF00 AF06 AH01 AH07 AH08 AJ03 5E033 BB09 BG03 BH02 5E034 DA07 DC01 DC05 DC09 DE07 5E082 AA01 AB03 BC40 FG26 FG27 FG52 GG10 GG11 GG26 GG28 JJ03 JJ05 JJ12 JJ21 JJ23 MM23

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 長手方向寸法が略0.6mm以下、幅方
向寸法が略0.3mm以下、厚み方向寸法が略0.3m
m以下であり、長さ方向両端に位置する第1,第2の端
面を有する電子部品素体と、 前記電子部品素体の第1,第2の端面を覆い、かつ電子
部品素体の端面に隣接する他の面に至る電極被り部を有
するように、第1,第2の外部電極が形成されており、
各外部電極が、焼結金属層と、焼結金属層上に形成され
たNiメッキ層とを備えるチップ型電子部品において、 前記長さ方向及び厚み方向と平行であり、幅方向と直交
する方向に断面視した場合に、電子部品素体の端面と、
隣接する他の面とのエッジ部における前記焼結金属層の
最も薄い部分の厚みT1が10μm以下であり、該部分
上のNiメッキ層の厚みT2が6μm以下であり、T2
>T1×0.25であることを特徴とする、チップ型電
子部品。
1. A longitudinal dimension is about 0.6 mm or less, a width dimension is about 0.3 mm or less, and a thickness dimension is about 0.3 m.
m, and an electronic component body having first and second end faces located at both ends in the length direction, and an end face covering the first and second end faces of the electronic component body, and First and second external electrodes are formed so as to have an electrode covering portion reaching another surface adjacent to the
In a chip-type electronic component in which each external electrode includes a sintered metal layer and a Ni plating layer formed on the sintered metal layer, a direction parallel to the length direction and the thickness direction and orthogonal to the width direction. When viewed in cross section, the end face of the electronic component body,
The thickness T1 of the thinnest portion of the sintered metal layer at the edge with the adjacent other surface is 10 μm or less, and the thickness T2 of the Ni plating layer on the portion is 6 μm or less;
> T1 × 0.25, a chip-type electronic component.
【請求項2】 前記電子部品素体のエッジ部が丸められ
ており、前記断面視した場合のエッジ部の曲率半径が3
0μm以下であり、上記断面視した場合のエッジ部にお
ける焼結金属層の外表面の曲率半径が60μm以下であ
る、請求項1に記載のチップ型電子部品。
2. An electronic component element according to claim 1, wherein an edge portion of the electronic component body is rounded, and a radius of curvature of the edge portion when viewed in a sectional view is three.
2. The chip-type electronic component according to claim 1, wherein the radius of curvature of the outer surface of the sintered metal layer at the edge portion when viewed in cross section is 60 μm or less.
【請求項3】 前記Niメッキ層上に形成されており、
かつSn、Pb及びSn−Pbのうち1種からなるメッ
キ層をさらに備える、請求項1または2に記載のチップ
型電子部品。
3. It is formed on the Ni plating layer,
The chip-type electronic component according to claim 1, further comprising a plating layer made of one of Sn, Pb, and Sn—Pb.
【請求項4】 長手方向寸法が略0.6mm以下、幅方
向寸法が略0.3mm以下、厚み方向寸法が略0.3m
m以下であり、長さ方向両端に位置する第1,第2の端
面を有するコンデンサ素体と、 前記コンデンサ素体の第1,第2の端面を覆い、かつコ
ンデンサ素体の端面に隣接する他の面に至る電極被り部
を有するように、第1,第2の外部電極が形成されてお
り、各外部電極が、焼結金属層と、焼結金属層上に形成
されたNiメッキ層とを備えるチップ型コンデンサにお
いて、 前記長さ方向及び厚み方向と平行であり、幅方向と直交
する方向に断面視した場合に、コンデンサ素体の端面
と、隣接する他の面とのエッジ部における前記焼結金属
層の最も薄い部分の厚みT1が10μm以下であり、該
部分上のNiメッキ層の厚みT2が6μm以下であり、
T2>T1×0.25であることを特徴とする、チップ
型コンデンサ。
4. A longitudinal dimension is about 0.6 mm or less, a width dimension is about 0.3 mm or less, and a thickness dimension is about 0.3 m.
m, and a capacitor body having first and second end faces located at both ends in the length direction; and covering the first and second end faces of the capacitor body and adjacent to the end faces of the capacitor body. First and second external electrodes are formed so as to have an electrode covering portion extending to another surface, and each external electrode is formed of a sintered metal layer and a Ni plating layer formed on the sintered metal layer. In a chip-type capacitor comprising: an end face of the capacitor element body, which is parallel to the length direction and the thickness direction, and when viewed in a cross-section in a direction orthogonal to the width direction, at an edge portion between another adjacent face. The thickness T1 of the thinnest portion of the sintered metal layer is 10 μm or less, the thickness T2 of the Ni plating layer on the portion is 6 μm or less,
A chip-type capacitor, wherein T2> T1 × 0.25.
【請求項5】 前記Niメッキ層上に形成されており、
かつSn、Pb及びSn−Pbのうち1種からなるメッ
キ層をさらに備える、請求項4に記載のチップ型コンデ
ンサ。
5. The semiconductor device according to claim 1, wherein said second plating layer is formed on said Ni plating layer.
The chip-type capacitor according to claim 4, further comprising a plating layer made of one of Sn, Pb, and Sn-Pb.
JP2000017427A 2000-01-26 2000-01-26 Chip-type electronic components and chip-type capacitors Expired - Lifetime JP3630056B2 (en)

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