JPH06195611A - Static image recorder and amplifier circuit - Google Patents

Abstract

PURPOSE:To enable phase adjustment to be conducted with good accuracy by adding a reference signal for resample phase adjustment separately from a reference signal for waveform equalization. CONSTITUTION:A reference signal adding section 5 forms the pulse of the same phase as the phase of an image sample value and of the pulse width equal to its sampling interval as the reference signal for waveform equalization at the time of reproduction to the analog sample value array of the image signal outputted from a camera signal processing section 3. The reference signal for phase adjustment at the time of resample is added separately. The reference signal for waveform euqualization and the reference signal for resample phase adjustment are supplied from an SSG processor 4 to the reference signal adding section 5 at this time. A staircase signal is used as the reference signal for resample phase adjustment and the resample phase is so adjusted as to include the peak point of the reference signal for resample phase adjustment in which the point to be resampled is reproduced by a resample clock. The influence of S/N is lessened as the inclination near the peak point is fairly steep.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a still image recording apparatus for recording a sample value sequence of an image signal on a recording medium, and an amplifier circuit.

[0002]

2. Description of the Related Art An SV (still video) system is a system for recording an NTSC still image on a 2-inch magnetic disk (hereinafter referred to as an SV floppy). Recently, CHSV (format compatibility) has been developed as a method capable of recording an image quality of about 1000 pixels (vertical) × 1300 pixels (horizontal) on this SV floppy and being compatible with the conventional SV system.
The ble High definition SV) system has been proposed.

The CHSV system utilizes a technique called sampled value analog transmission. This is a technique also used in the MUSE system proposed by NHK as a transmission system of HDTV, and a sample value string (set as a time interval T) using an analog transmission line with a predetermined band limitation.
Is intended to be transmitted correctly.

There are the following two conditions for realizing this sampled value analog transmission. (1) The frequency characteristic of the analog transmission line is a linear phase and has a target roll-off characteristic centered on a frequency of (1 / 2T) (Nyquist condition). (2) Re-sampling the correct sampling point on the receiving side (during playback). In the CHSV system, after satisfying these two conditions, a sample value sequence of a video (image) signal is basically recorded on an SV floppy in accordance with the recording format of a conventional SV system and reproduced ( (See FIG. 10).

FIGS. 11A to 11C respectively show CH.
Y (luminance) recorded on SV floppy in SV system
Signals and sample points of C1 and C2 (color difference) signals are shown. Here, the color difference signals C1 and C2 are (R-
The Y) signal and the (BY) signal are shown, but the symbols C1 and C2 are used as the symbols for classifying how to take the sample points. Therefore, in the case of C1 = (RY),
C2 = (BY), and conversely, if C1 = (BY), then C2 = (RY). Then, in the CHSV method, the Y signal, C1 signal, and C2 signal of the sample pattern shown in FIG. 11 are divided into four and recorded on four tracks of the SV floppy.

As shown in FIG. 11, the method of division is Y
The signal, the C1 signal, and the C2 signal are different from each other. For example, the Y signal is (4n + 0) line, (4n +)
The Y signals, the YA signals, the YB signals, the YC signals, and the YD signals sampled on the 1) line, the (4n + 2) line, and the (4n + 3) line, respectively, are distributed and recorded on four tracks. The C1 signal is (8th n +
0) line, (8n + 2) line, (8n + 4) line, (n + 6) line, respectively sampled C1 signal, C1A signal, C1B signal, C1C signal,
The C1D signal is distributed to four tracks and recorded. C
The two signals are the C2 signal, the C2A signal, and the C2 signal sampled on the (8n + 1) th line, the (8n + 3) th line, the (8n + 5) th line, and the (nth + 7) th line, respectively.
The B signal, the C2C signal, and the C2D signal are distributed to four tracks and recorded.

In the recording format of the conventional SV system, FM-modulated Y signal and FM-modulated C1 / C2 are used.
The (color difference line sequential) signal is frequency-multiplexed and recorded (see FIG. 12).

In the CHSV system, in accordance with this recording format, as shown in FIG. 13, for YA signal to YD signal, C1A signal to C1D signal, C1A signal to C2 are provided.
The D signal is frequency-multiplexed with the FM-modulated signal in the following combinations, distributed to four tracks, and recorded on an SV floppy. : YA, C1A / C2C: YB, C2A / C1C: YC, C1B / C2C: YD, C2B / C1D

Therefore, the S recorded by the CHSV system is recorded.
When playing a V floppy with a conventional SV player,
At least the field reproduction is completely compatible, and the frame reproduction can be compatible when the second and third tracks of FIG. 5 are frame-reproduced.

Also, during CHSV reproduction, the original sample values are completely restored by re-sampling the sample value sequence recorded on the four tracks at correct sample points. They are stored in the memory at the time of reproduction, and then, by interpolating pixels other than the sample points shown in FIG.
A still image of about 000 × 1300 is reproduced.

In such a CHSV system, it is very important to satisfy the "Nyquist condition of the transmission line" and the "correct re-sampling phase" as described above. For this reason,
In the conventional CHSV system, an isolated HIT as shown in FIG. 14 is used as a phase reference signal for re-sampling.
(Horizonqal Interval Test
) The signal (pulse) was added in the same phase as the image sample value. However, the pulse width of the HIT signal (pulse) is the same as the interval between the image sample values. In this case, the waveform that has passed through the transmission line L during reproduction is as shown on the right side of FIG.

Therefore, the resample clock CLK
As shown in FIG. 15, the point resampled by (see FIG. 14) is adjusted so as to include the peak point (S point in FIG. 14) of the reproduced HIT pulse, so that the correct resampled point can be obtained. The condition can be satisfied. That is, since the peak point S of the reproduced HIT pulse becomes the reference point, this peak point is hereinafter referred to as the reference point S.

Further, waveform equalization for correcting the deviation from the Nyquist condition of the transmission line can be performed on the data resampled correctly in this way as follows. That is, the response of the HIT pulse after passing through the transmission line is
It can be regarded as an impulse response of the transmission line. Therefore, find the difference between this response and the desired reference response,
In order to reduce this difference, the number of taps of the FIR filter is determined and filtering is performed. If the above process is repeated and converged, the allowable range is reached at a certain stage, and the waveform equalization ends.

As such an amplifier circuit for video (image) signals, a base-grounded amplifier circuit having a high cut-off frequency and excellent high frequency characteristics as shown in FIG. 17 has been conventionally used. It was

[0015]

However, as a first problem, in the above HIT signal for re-sampling phase reference, the inclination near the reference point S point in FIGS. 14 and 15 is almost "0". However, the accuracy of detecting the correct sampling point cannot be so high that the re-sampling phase adjustment cannot be performed with high accuracy, which adversely affects the reproduced image quality.

The first invention has been made under such circumstances, and its object is to perform re-sampling phase adjustment with high accuracy in recording a sample value sequence of an image signal on a magnetic disk by the CHSV system. Record as you can.

There is also the following second problem.
That is, in the HIT signal for re-sampling phase reference, the HIT addition period W is set at the beginning of the video signal effective period for each horizontal scanning period, as shown in FIG. It was added to the center of the HIT addition period W.

However, the response waveform of the HIT pulse after passing through the transmission line is the LPF (low pass filter) of the transmission line.
Due to the characteristics, the ringing spreads as shown in FIG. 16B, and thus the ringing in the latter half overlaps with the response waveform from the video signal. Such overlapping is not preferable because the response waveform of the HIT pulse is used not only as a reference for the reproduction sample position during reproduction but also as a reference waveform for transmission line equalization as described above.

The second invention has been made under such circumstances, and an object thereof is to record a sampled value sequence of an image signal on a magnetic disk by the CHSV method, and to resample a phase after passing through a transmission line. This is to record in such a manner that the response waveform of the reference signal and the response waveform of the image signal do not overlap.

Further, there is the following third problem. That is, the response waveform of the HIT pulse spreads like a ringing as shown in FIG. 16B due to the LPF characteristic of the transmission line. Therefore, as shown in FIG. 16A, the HIT addition period W
Since a certain size is required, a part of the video signal effective section in the original video signal standard is
It was used as an additional period W.

By the way, there are some CHSV type cameras which can perform not only the CHSV type recording but also the conventional SV type recording. However, in the conventional camera of this type, when the SV type recording is performed, it is originally HIT. Although it is not necessary to add a pulse, the HIT pulse is added even when recording by the SV method. For this reason, the video in the HIT addition period W, which is a part of the video signal effective section, is not only wasted, but also appears black on the TV monitor during reproduction.

The third invention has been made under such circumstances, and an object thereof is to record a still image by the SV system in a still image recording apparatus for recording the CHSV system and the SV system. In doing so, it is necessary to record in a form that improves the quality of the reproduced image.

Further, the conventional amplifying circuit for amplifying the video signal shown in FIG. 17 has the following fourth problem.

That is, when an image signal is input to the amplifier circuit, the resistance value of the resistor R4 in FIG. 17 may be increased to increase the amplification degree, particularly for improving the sensitivity. For example, there is a case where a dark part is photographed in a backlit state. As described above, when the amplification degree of the amplifier circuit is set to be extremely high, when a signal (negative polarity) like “Vin” shown in FIG. 18 is input, an output like “Vout” is obtained. That is, the bright part is clipped because the amplification degree is too high.

However, since this is originally a bright portion at the time of backlighting, it is crushed by the γ correction circuit, the Knee correction circuit, and the white clip circuit in the subsequent stage, so that there is no problem in the end.

However, at the steep rising portion (signal of the changing portion from the bright portion to the dark portion of the image) shown by "Vout" in FIG. 18, a large waveform blunting occurs. This is because the amplifying transistor Q2 in FIG. 17 is completely saturated during the amplification of the bright portion, and then it takes time to return to the transistor active region when the dark portion is changed. This dullness of the waveform causes a large waveform distortion in shooting in backlight, and the reproduced image is disturbed. The same problem has occurred in the grounded-emitter amplifier circuit.

The fourth invention has been made under such circumstances, and an object thereof is to prevent an amplification transistor from being saturated even when the amplification degree is increased in a grounded base type or grounded emitter type amplification circuit. To do so.

[0028]

In order to achieve the above first object, the first invention is a still image recording apparatus for recording a sample value sequence of an image signal on a magnetic disk. The non-signal portion is provided with an adding means for adding a reference pulse for waveform equalization used at the time of reproduction and a re-sampled phase reference signal which makes the waveform steep after passing through the transmission path.

In order to achieve the above second object, a second invention is a still image recording apparatus for recording a sample value sequence of an image signal on a magnetic disk, which is used when reproducing the sample value sequence of the image signal. In adding the re-sampled phase reference pulse, the interval between the re-sampled phase reference pulse and the end of the horizontal blanking pulse is
Additional control means is provided to add the resampled phase reference pulse so as to be shorter than the interval between the sampled value sequence of the image signal.

In order to achieve the above-mentioned third object, a third aspect of the present invention includes a first image signal processing circuit for performing image signal processing for recording a sampled value sequence of image signals on a magnetic disk and sampling. In a still image recording device including a second image signal processing circuit for performing an image signal processing for recording a non-existing image signal on a magnetic disk, the video signal processed by the first image signal processing circuit Additional control means for controlling so as to add a re-sample phase reference pulse used during reproduction only to the sample value sequence,
During image signal processing, a wide horizontal blanking pulse is supplied to the first image signal processing circuit, and a narrow horizontal blanking pulse is supplied to the second image signal processing circuit. And a switching control means for controlling switching.

In order to achieve the above-mentioned fourth object, the fourth invention is an amplifier circuit having an amplifier transistor whose base is grounded or whose emitter is grounded, and which has, for example, a diode and a reference voltage section. Under a structure in which the cathode of is connected to the collector of the amplifying transistor and the anode is connected to the reference voltage unit,
A saturation prevention circuit configured to prevent the amplification transistor from being saturated by turning on the diode when a large signal is input and starting current supply to the collector of the amplification transistor. It is provided.

[0032]

According to the first aspect of the present invention, in the still image recording apparatus for recording a sample value sequence of an image signal on a magnetic disk, the adding means includes a non-signal portion of the image signal sample value sequence.
In addition to the waveform equalization reference pulse used during playback and this waveform equalization reference pulse, a resampled phase reference signal such as a staircase that makes the waveform steep after passing through the transmission path Add.

In this way, by making the re-sampled phase reference signal stepwise, the slope at the point where this signal is used as the re-sampled phase reference point on the waveform after passing through the transmission line is steep. Therefore, the phase can be adjusted with high accuracy.

According to a second aspect of the invention, in a still image recording apparatus for recording a sample value sequence of an image signal on a magnetic disk,
The addition control means adds the re-sampling phase reference pulse used at the time of reproduction to the sample value sequence of the image signal, and determines the interval between the re-sampling phase reference pulse and the end of the horizontal blanking pulse. Is added so as to be shorter than the interval between the re-sampling phase reference pulse and the sample value sequence of the image signal.

With this configuration, the position of the re-sampling phase reference pulse is far from the sample value train of the image signal, so that the response waveform of the re-sampling phase reference pulse after passing through the transmission line, The response waveform of the sample value sequence of the image signal (pixels other than the sample points are interpolated during reproduction) does not overlap.

In the third invention, the first image signal processing circuit for performing the image signal processing for recording the sample value sequence of the image signal on the magnetic disk and the non-sampled image signal for recording on the magnetic disk. And a second image signal processing circuit for performing the image signal processing, the addition control means adds a sample value sequence of the video signal processed by the first image signal processing circuit. Control is performed so that a re-sampling phase reference pulse used at the time of reproduction is added. The switching control means is wider than the first image signal processing circuit that generates the sample value sequence of the image signal to which the re-sampling phase reference pulse should be added during the image signal processing. A narrow horizontal blanking pulse is supplied to the second image signal processing circuit which supplies the horizontal blanking pulse and generates the image signal to which the re-sampling phase reference pulse is not added. Switch control to.

As a result, the effective portion of the video signal generated by the second image signal processing circuit will not be unnecessarily truncated, and will not appear black on the TV monitor during reproduction.

According to a fourth aspect of the present invention, in the amplification circuit having the amplification transistor whose base is grounded or whose emitter is grounded, the saturation prevention circuit has, for example, a diode and a reference voltage section, and the cathode of the diode is the It is connected to the collector of the amplifying transistor, and the anode is connected to the reference voltage section. When a large signal is input, the diode turns on and the current to the collector of the amplifying transistor. By starting the supply, the amplification transistor is prevented from being saturated.

By providing such a saturation prevention circuit, when an image is captured with an increased amplification degree, even if the input signal changes from a bright image signal to a dark image signal, the waveform becomes dull. Disappears.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the first to fourth inventions will be described with reference to the drawings.

[First Invention] FIG. 1 shows first to third inventions.
FIG. 3 is a block diagram showing a schematic configuration of a still image recording apparatus according to an embodiment of the invention of FIG. In the present invention, at least in the third aspect of the invention, the SV recording mode for recording a still image for one field on one track and the CHSV for recording a still image for one field on four tracks in a divided manner.
The recording mode is configured to be switchably set. In this case, the system controller 1 sends the SV mode signal or the CHSV mode signal to the camera signal processing unit 3,
The signal is supplied to the SSG processor 4, the reference signal adding unit 5, and the recording signal processing unit 7. Further, in the first and second inventions, at least CHSV recording is configured to be performed.
When only the recording function is provided and the SV recording function is not provided, the system controller 1 does not output the above mode signal.

The image pickup section 2 includes an optical lens system (not shown),
It has an amplifier circuit 2 in addition to a CCD and the like, and an optical image incident from an optical lens system is photoelectrically converted by the CCD,
The signal is amplified by the amplifier circuit 2 and output to the camera signal processing unit 3. The camera signal processing unit 3 forms a video signal (still image signal) from the amplifier circuit 2 into a luminance signal Y, color difference signals RY and BY based on the image signal system of the NTSC system, and a horizontal synchronization signal. HD and the vertical synchronizing signal VD are added and output. In this case, when performing CHSV recording, an analog sample value sequence of the image signal as described in the section of the conventional example is formed. For this camera signal processing unit 3, SS
The G processor 4 supplies the horizontal blanking pulse BLK under the control of the system controller 1.

The reference signal adding section 5 is a camera signal processing section 3
The HIT pulse (signal) or the like supplied from the SSG processor 4 is added to the analog sampled value sequence of the image signal output from, that is, the image signal for CHSV recording. However, the SV output from the camera signal processing unit 3
Nothing is added to the recording image signal, and the image signal for recording is free-passed.

The threshold circuit 6 thresholds the image signal output from the reference signal adding section 5 based on a clock having a cycle equal to the sampling interval of the sample value sequence. Then, the recording signal processing unit 7 performs predetermined recording signal processing such as emphasis, FM modulation, addition of an ID signal, etc. on the signal from the threshold hold circuit 6 and outputs it to the recording head 9, S
The V floppy 8 is recorded. The recording head 9 is
It is a 2-channel head, and when SV recording is performed, recording is performed twice for each track by the 2-channel head. When performing CHSV recording, 2-track simultaneous recording is performed twice by the 2-channel head. The recording signal processing unit 7 controls so as to record a total of four tracks.

Next, the structure and operation peculiar to the first invention will be described with reference to FIGS. 2 and 3.

In the first aspect of the invention, the reference signal adding section 5 operates on the analog sampled value sequence of the image signal output from the camera signal processing section 3 by the pulse of FIG. That is, a pulse having the same phase as the image sample value and a pulse width equal to the sampling interval is used as a waveform equalization reference signal during reproduction, and a reference signal for phase adjustment during re-sampling is added separately. It has a feature. At this time, the waveform equalization reference signal and the re-sampling phase adjustment reference signal are supplied from the SSG processor 4 to the reference signal adding section 5.

As the reference signal for re-sampling phase adjustment,
For example, a stepwise signal like S1 to S3 shown in FIG. 2 is used. By doing so, the re-sampling phase is adjusted so that the points re-sampled by the re-sampling clock CLK include the peak points (reference points) S of the reproduced re-sampling phase adjustment reference signals S1 to S3 in FIG. Can be adjusted (see FIG. 15). Further, at this time, the slope near the reference point S is considerably steep, and the sensitivity for detecting the reference point S of the re-sampling phase adjustment reference signals S1 to S3 is improved. Also less.

FIG. 3 is a diagram showing an example in which such a waveform equalization reference signal and a re-sampling phase adjustment reference signal are added. That is, FIG. 3D is an example in which the waveform equalization reference signal S6 of FIG. 3A and the re-sampling phase adjustment reference signal S4 of FIG. 3B are added, and FIG. 3 is an example in which the waveform equalization reference signal S6 of FIG. 3A and the re-sampling phase adjustment reference signal S5 of FIG. 3C are added.

3 (d) and 3 (e) are examples of reference signal addition for 1H (horizontal period), these need to be added to all H (horizontal period) of one field period. Alternatively, as shown in FIGS. 3F and 3G, only a part of H (horizontal period) may be used. In addition, FIG.
The scale of (g) is reduced by 1/2 of the number of scanning lines from the scale of FIGS. 3 (a) to 3 (e). Also,
In FIGS. 3F and 3G, the sample train of the video signal is not shown. The re-sampling phase adjustment reference signals S1 to S5 shown in FIGS. 2 and 3 may be combined in any manner within one field period {see FIGS. 3 (f) and 3 (g)}. further,
Reference signals S1 to S5 for re-sampling phase adjustment in FIGS.
Even if the reference signal is of a type (shape) other than
Any shape is acceptable as long as the inclination after passing through is steep.

[Second Invention] Next, the structure and operation peculiar to the second invention will be described with reference to FIG.

In the second aspect of the invention, the reference signal adding section 5 applies the HIT pulse S to the analog sampled value sequence of the image signal output from the camera signal processing section 3 in the following manner.
Add 6. That is, as shown in FIG. 4A, the end of the horizontal blanking pulse and the HIT pulse S6.
The interval a between the HIT pulse S6 and the start end of the image (video) signal is smaller than the interval b between
Pulse S6 is added. The image (video) referred to here
The signal is an image signal in which pixels other than the sample points are interpolated in the sample value sequence, but actually, the sample values from the camera signal processing unit 3 in which the pixels other than the sample points are not interpolated. The HIT pulse S6 is added to the column.

By doing so, it is possible to prevent the response waveforms of the HIT pulse S6 after passing through the transmission line and the start end portion of the image (video) signal from overlapping, and the reproduced image is not disturbed. The end of the horizontal blanking pulse and HI
The distance a between the T pulse S6 and the horizontal blanking pulse H after passing through the transmission line is set to have a certain magnitude.
It goes without saying that the response waveform of the IT pulse S6 does not overlap.

[Third Invention] Next, the structure and operation peculiar to the third invention will be described with reference to FIGS. 5 and 6.

In the third invention, the camera signal processing section 3 is
Based on the mode signal from the system controller 1,
It has a function of performing both SV recording and CHSV recording. Then, the SSG processor 4 supplies the HIT signal S6 to the reference signal adding section 5 only in the CHSV recording mode to add the HIT signal S6 (see FIG. 5A), and does not supply the HIT signal S6 in the SV recording mode. Further, in the CHSV recording mode, the SSG processor 4 supplies the HIT signal S6 to add the HIT signal S6, and thus the horizontal blanking pulse having a wide width corresponding to the combined period of the horizontal blanking period and the HIT addition period. Is supplied to the camera signal processing unit 3 (see FIG. 5B), but since the HIT signal S6 is not supplied in the SV mode, a narrow horizontal blanking pulse corresponding to only the horizontal blanking period is supplied. (See FIG. 5C).

As described above, during SV recording which originally does not need to add the HIT signal S6, the HIT signal S6 is not added and a narrow horizontal blanking pulse corresponding to only the horizontal blanking period is supplied. As a result, the valid image signal, which is conventionally truncated as shown by the broken line in FIG. 6, is not truncated as shown by the solid line at 6, and the discarded portion may appear black on the TV monitor. Disappear.

[Fourth Invention] Next, the structure and operation peculiar to the fourth invention will be described with reference to FIGS.

A fourth invention is an invention relating to a grounded base type amplifier circuit for amplifying a high frequency signal such as a video signal,
In this embodiment, the amplifier circuit 2a in the image pickup unit 2 shown in FIG.
It corresponds to.

FIG. 7 is a circuit diagram of an amplifier circuit according to the first embodiment of the fourth aspect of the invention.
1, Q2, Q3, diode D1, first reference voltage unit 4
It has first and second reference voltage sections 42.

The transistor Q1 constitutes an emitter follower and matches the input impedance of the transistor Q2. The base of the transistor Q2 is grounded via the first reference voltage unit 41, and acts as an amplifying transistor. Transistor Q3 also
A transistor Q for amplification that constitutes an emitter follower
It is matched with the output impedance of 2. The anode of the diode D1 is connected to the second reference voltage section 42, and the cathode is connected to the collector of the amplifying transistor Q2. The reference voltage V of the first reference voltage unit 41
REF1 is equal to or lower than the reference voltage VREF2 of the second reference voltage section 42, that is, VREF1 ≦ VREF2.

Next, the operation when the value of the biasing resistor R4 of the amplifying transistor Q2 is increased to increase the amplification degree will be described.

When the value of the biasing resistor R4 of the amplifying transistor Q2 is increased to increase the amplification degree, and when a small signal voltage Vin is input to the base of the transistor Q1, the current I flowing through the biasing resistor R4 is Since it is small and the voltage drop due to the bias resistor R4 is also small,
The voltage of the cathode of the diode D1 is relatively high. Therefore, the reverse voltage is applied to the diode D1, that is, the diode D1 is in the off state. At this time, the collector-emitter voltage VCE of the amplifying transistor Q2 has a relatively large value, and the amplifying transistor Q2 is in an active state.

On the other hand, when a large signal voltage Vin is input to the base of the transistor Q1, the current I flowing through the bias resistor R4 becomes large and the voltage drop due to the bias resistor R4 also becomes large, so that the diode D
1 cathode voltage, that is, the amplifying transistor Q2
Of the amplifier transistor Q2 becomes small, and the collector-emitter voltage VCE of the amplifying transistor Q2 becomes small.

In this case, however, as described above, the cathode voltage of the diode D1 becomes low, so that the diode D1 is turned on with the forward voltage applied. As a result, the reference voltage VREF2 from the second reference voltage section 42 is applied to the collector of the amplifying transistor Q2, the current from the diode D1 flows, and the decrease of the collector-emitter voltage VCE is prevented. The amplifying transistor Q2 is maintained in the active state without being saturated.

As a result, even if a large signal Vin (negative polarity) as shown in FIG. 8A is input, as shown in FIG. 8B, a steep rising portion (bright portion of the image). Signal from the dark part to the dark part), the output waveform is not blunted and the reproduced image is not disturbed. If a high-speed switch diode such as a Schottky barrier diode is used as the diode D1, the characteristics will be further improved.

Further, instead of the diode D1 of FIG.
The transistor Q4 as shown in FIG. 9 is provided, and the base of the transistor Q4 is grounded via the second reference voltage section 42.
Even when the emitter is connected to the collector of the amplifying transistor Q2, the saturation of the amplifying transistor Q2 can be prevented by the same principle.

The fourth invention is not limited to the above embodiment, but can be applied to, for example, a grounded-emitter amplifier circuit.

[0067]

As described in detail above, according to the first invention, the reference signal for re-sampling phase adjustment is added separately from the waveform equalization reference signal (HIT pulse),
Further, since the slope of the reference signal for re-sampling phase adjustment at the reference point is steep, it is possible to perform accurate phase adjustment.

According to the second aspect of the invention, the recording can be performed in such a manner that the response waveforms of the HIT pulse and the video signal after passing through the transmission path do not overlap each other, and there is no fear of image distortion.

According to the third aspect of the invention, since the effective video signal is saved without being truncated in the SV mode, a black portion on the TV monitor does not appear during reproduction.

Further, according to the fourth invention, in the base-grounded type or grounded-emitter type amplifier circuit, it is possible to prevent the amplifying transistor from being saturated when the amplification degree is increased, so that the output waveform The reproduced image will not be disturbed by the dullness.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a still image recording apparatus according to an embodiment of the first invention to the third invention.

FIG. 2 is a diagram showing a reference signal for re-sampling phase adjustment in the embodiment of the first invention.

FIG. 3 is a diagram showing an example in which a re-sampling phase adjustment reference signal and a waveform equalization reference signal are added to a sample value sequence of an image signal in the embodiment of the first invention.

FIG. 4 is a diagram showing how to add a re-sampling phase adjustment reference signal in the embodiment of the second invention.

FIG. 5 is a diagram showing a state in which a re-sampling phase adjustment reference signal is added in the CHSV mode and the width of the horizontal blanking pulse in the CHSV mode and the SV mode in the embodiment of the third invention.

FIG. 6 is a diagram showing a state of a reproduction signal in an SV mode in an embodiment of the third invention.

FIG. 7 is a circuit diagram showing a base-grounded amplifier circuit according to a first embodiment of the fourth invention.

FIG. 8 is a diagram showing input / output signal examples in the first and second embodiments of the fourth invention.

FIG. 9 is a circuit diagram showing a base-grounded amplifier circuit according to a second embodiment of the fourth invention.

FIG. 10 is a diagram for explaining the principle of the CHSV recording method.

FIG. 11 is a diagram for explaining sampling points of a video signal in the CHSV recording system.

FIG. 12 is a diagram showing frequency allocation of a recording signal in the SV format.

FIG. 13 is a diagram showing a recording pattern on four tracks in the CHSV recording method.

FIG. 14 is a diagram showing a reference signal for re-sampling phase adjustment and a response waveform after passing through the transmission path.

FIG. 15 is a diagram for explaining a phase adjustment method using a re-sampling phase adjustment reference signal.

FIG. 16 is a diagram for explaining second and third problems of the conventional still image recording apparatus.

FIG. 17 is a circuit diagram showing a conventional amplifier circuit for image signals.

FIG. 18 is a diagram showing a problem of a conventional amplifier circuit for image signals.

[Explanation of symbols]

 1: System controller 2: Imaging unit 2a: Amplifying circuit 3: Camera signal processing unit 4: SSG processor 5: Reference signal adding unit 6: Threshold hold circuit 7: Recording signal processing unit 8: SV floppy 9: Recording head

Claims (6)

[Claims] 1. A still image recording apparatus for recording a sample value sequence of an image signal on a magnetic disk, wherein a waveform equalization reference pulse used during reproduction and a transmission line are provided in a non-signal portion of the image signal sample value sequence. A still image recording apparatus, comprising: an addition unit for adding a re-sampling phase reference signal such that the slope of the waveform after passing becomes steep. 2. A still image recording apparatus for recording a sample value sequence of an image signal on a magnetic disk, wherein a re-sampling phase reference pulse used during reproduction is added to the sample value sequence of the image signal. An additional control unit is added so that the interval between the resample phase reference pulse and the end of the horizontal blanking pulse is shorter than the interval between the resample phase reference pulse and the start end of the sample value sequence of the image signal. A still image recording device characterized by being provided. 3. A first image signal processing circuit for performing an image signal processing for recording a sample value sequence of an image signal on a magnetic disk, and an image signal processing for recording an unsampled image signal on a magnetic disk. And a second image signal processing circuit for performing a re-sampling used for reproduction only on a sample value sequence of the video signal processed by the first image signal processing circuit. Addition control means for controlling to add a phase reference pulse, and a wide horizontal blanking pulse are supplied to the first image signal processing circuit at the time of image signal processing, and the second image signal is supplied. A still image recording apparatus, comprising: switching control means for switching control so that a horizontal blanking pulse having a narrow width is supplied to the processing circuit. 4. An amplifying circuit having an amplifying transistor whose base is grounded or whose emitter is grounded, which is turned on when a large signal is input to start current supply to the collector of the amplifying transistor.
An amplification circuit comprising a saturation prevention circuit configured to prevent the amplification transistor from being saturated. 5. The saturation prevention circuit has a diode and a reference voltage unit, the cathode of the diode is connected to the collector of the amplifying transistor, and the anode is connected to the reference voltage unit. The amplifier circuit according to claim 4, wherein 6. The saturation prevention circuit has a transistor and a reference voltage unit, the emitter of the transistor is connected to the collector of the amplifying transistor, and the base is connected to the reference voltage unit. Claim 4
The described amplifier circuit.