JPH06188415A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide an MOS-type semiconductor device on a semiconductor substrate with a sharp impurity profile and a manufacturing method for creating an element while maintaining the profile. CONSTITUTION:When forming an MOS transistor on a substrate 1 where an impurity region with a sharp profile called a delta dope layer 6 inside it, element isolation regions are formed in MOS structures 4, 9, and 10 or an impurity layer with a sharp profile is formed after an element isolation oxide film is formed to form an MOS transistor, thus forming an MOS element without collapsing the sharp concentration distribution of a punch-through stopper and hence extremely suppressing the punch-through phenomenon while reducing the impurity concentration near a channel. Namely, channel characteristics can be drastically improved while preventing reduction in threshold voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS (Metal-Oxide-Semiconductor) type field effect semiconductor device composed of a metal-oxide film-semiconductor, and particularly, it becomes remarkable when the element size is miniaturized. (EN) A semiconductor device capable of effectively suppressing a performance deterioration phenomenon such as a decrease in threshold voltage and punch through, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Miniaturization of semiconductor devices has been achieved not only by simply reducing the size, but also by causing undesirable phenomena such as a short channel effect and a punch through phenomenon which become remarkable as the size is reduced. It is also the result of effective suppression. The guideline in this case was the proportional reduction rule, and accordingly, as the dimensions were reduced, the substrate concentration was increased, the gate oxide film was thinned, and the impurity layer forming the source / drain was made shallow. It was Semiconductor elements,
In particular, in order to miniaturize the MOS type field effect element, it is known that if this guideline is followed, there are the following factors for inhibiting miniaturization. This is because as the substrate concentration increases, the width of the source / drain depletion layer decreases, and punch through can be suppressed. Therefore, the short channel characteristics are improved. However, on the other hand, an increase in substrate concentration causes an increase in threshold voltage. Therefore, as shown in the schematic diagram of the impurity profile in FIG. 4 (6 ″ in the figure), when the impurities are ion-implanted into the substrate, a condition that the peak concentration position exists inside the substrate, not on the surface, is set. This is because the concentration in the vicinity of the surface of the substrate forming the channel of the MOS type field effect element is made small to prevent the rise of the threshold voltage, and the inside of the substrate is made to have a high concentration to suppress punch through. To obtain a substrate having such conditions, specifically, when the substrate is p-type, boron is about 20 KeV,
In the case of n-type, arsenic is about 100 KeV and 1x
About 10 ¹³ / cm ² is implanted into the substrate. As a result, the peak concentration position is about 50 nm, and the peak concentration (1x1
The surface concentration can be reduced to about half as compared with the case of 0 ¹⁸ / cm ³ . Since the surface concentration is low, the punch-through can be suppressed by the layer having the peak concentration without increasing the threshold voltage. Hereinafter, the layer having the peak concentration will be referred to as a punch through stopper layer.

A semiconductor device having such a punch through stopper layer is shown in FIG. In this example, complementary MOS (CMOS: Complimentary MO)
S) A semiconductor device is shown. In a CMOS, a p-type well (4) and an n-type well (5) are provided on the same semiconductor substrate (1) surface, and an n-type channel and a p-type channel MOS element are produced in each semiconductor region. is doing. 6 "is p
Showing the punch through stopper layer of the mold, as described above,
It is formed by implanting boron ions. Reference numeral 13 is an n-type punch through stopper, which is ion-implanted with arsenic.

In FIG. 3, 1 is a semiconductor substrate and 4 is a semiconductor substrate.
Is a p-type well region, 5 is an n-type well region, 6 ″ is a p-type punch-through stopper layer, 11 ′ is an element isolation oxide film,
13 is an n-type punch-through stopper layer, 14 is a gate oxide film, 15 is a gate electrode, 16 is an n-type source / drain impurity layer, 17 is a p-type source / drain impurity layer,
18 is an interlayer insulating film, 19 is a metal for filling a contact, 2
0 is a wiring metal.

[0005]

In the conventional semiconductor device shown in FIG. 3, the source / drain impurity layer (16) of the n-type channel MOS element formed in the p-type well (4) is formed.
Is usually formed by ion implantation of arsenic. But,
Since the punch-through stopper layer (6 ″) is formed by boron implantation and has a spread in the depth direction of the substrate, as shown in FIG. 4, the n-type source / drain impurity layer ends are formed. The concentration of the p-type punch-through stopper layer (6 ″) becomes as high as 1 × 10 ¹⁸ / cm ³ . Generally, the larger the concentration at the junction between the n-type impurity layer and the p-type impurity layer, the larger the junction capacitance. In this case, the source-drain junction capacitance increases, which hinders the performance improvement of the CMOS device.

On the other hand, in the p-type channel MOS element formed in the n-type well (5), the punch-through stopper layer (13) is formed by arsenic implantation. The spread of arsenic distribution due to ion implantation is smaller than that of boron, and in the case of a p-type channel MOS element, since the source / drain impurity layers (17) are formed by boron ion implantation, the concentration distribution is large. The n-type punch-through stopper layer (1) at the end of the p-type impurity layer (17).
The concentration of 3) can be made quite small. As described above, with respect to the p-type channel MOS element, it is possible to use the conventional ion implantation method to fabricate a fine MOS element having a small source / drain junction capacitance and excellent short channel characteristics. However, in CMOS, n
Since it is also necessary to improve the performance of the type channel MOS device, a method capable of realizing a steeper profile than that of ion implantation is necessary for forming the p-type punch through stopper.

Regarding the formation of this p-type punch-through stopper, as disclosed in Japanese Patent Laid-Open No. 4-28149, the molecular beam epitaxial method is used to grow the impurities in the atomic layer and to make the impurity distribution uniform. A technology for controlling with several tens of nanometers has been devised.

The molecular beam epitaxial method has an advantage that a steep profile can be formed, but since it is a method of growing a crystal on the entire surface of a semiconductor substrate, regions having different conductivity types are formed on the same semiconductor substrate like a CMOS device. It has the drawback that it cannot be made. Furthermore, even if a steep impurity profile is formed, M
In the OS element manufacturing method, a steep profile cannot be maintained due to the effect of heat treatment during element formation.

More specifically, in the molecular beam epitaxial method, an impurity layer having a very steep profile is formed inside the semiconductor substrate as shown by line 6'shown in FIG. 850 in the manufacturing process
Since it is subjected to heat treatment at a temperature of ℃ or more, impurity diffusion occurs and the profile becomes gentle. There is also a problem that the steeper the profile before heat treatment, the larger the profile spread.

The element isolation oxide film growth step has the greatest effect as a heat treatment step for increasing the spread of the profile. The element isolation oxide film is essential for electrically isolating each element on the semiconductor substrate, and a thermal oxidation method is usually used. Unlike the gate oxide film, this element isolation oxide film requires a film thickness of 200 nm or more, and therefore high temperature oxidation of 1000 ° C. or more is usually used in the thermal oxidation method. Since the growth of the element isolation oxide film is performed after the punch-through stopper is formed, it is impossible to keep the concentration profile at several tens of nm or less immediately after the epitaxial growth at such a high temperature.

[0011]

According to the first manufacturing method of the present invention, a metal-based method is used instead of the method of growing an oxide film on the substrate having the steep profile as the element isolation method.
Forming an element isolation region of a MOS structure (10, 9, 4) composed of an oxide film-semiconductor, and performing insulation isolation between elements by a method using an accumulation layer at the interface between the oxide film (9) and the semiconductor (4). Is characterized by.

Further, in the second manufacturing method of the present invention, a p-type punch-through stopper layer (6) is formed by a molecular beam epitaxial method in a region where an n-type channel MOS is formed, and p
By implanting arsenic in the region where the type channel MOS is formed, an n-type punch-through stopper layer (13) is formed, and an element isolation region having a MOS structure composed of metal-oxide film-semiconductor is formed. It is characterized in that the device is manufactured.

Further, according to the third manufacturing method of the present invention, a CMOS element in which an impurity layer having a steep profile is formed after forming an element isolation oxide film is manufactured.

[0014]

In the first manufacturing method, the thickness of the oxide film is considerably smaller than that of the normal element isolation oxide film, so that the oxide film can be formed at a low temperature. Further, since polycrystalline silicon can be adopted as the metal of the MOS structure, the deposition temperature of polycrystalline silicon in that case is as low as 600 ° C. or lower. By adopting such an element isolation structure, it is possible to avoid the element isolation oxide film growing step, which is the highest temperature and longest in the MOS element manufacturing process. Therefore, the element isolation region can be formed without breaking the profile of the channel stopper layer.

In the second manufacturing method, an n-type channel MOS is used.
Metal-oxide film-for separating element and p-channel MOS element
By forming an element isolation region of a MOS structure made of a semiconductor, a p-type channel MOS element is formed.
Since the inversion layer is not formed at the interface between the well and the element isolation region, the element isolation characteristic becomes excellent.

In the third manufacturing method, since the impurity layer having a steep profile is formed after the element isolation oxide film is formed, the steep profile is not destroyed by the high temperature at the time of forming the element isolation oxide film.

[0017]

EXAMPLE A first example of the present invention will be described below with reference to FIG.
~ It demonstrates using FIG. First, the n-type channel MOS
An example in which an element is created will be described.

As shown in FIG. 5A, a silicon substrate of the first conductivity type (specifically, boron of 1 × 10 ¹⁵ / cm 3 is used).
^An oxide film (2) is grown to a thickness of about 20 nm on the surface of a silicon substrate (10 Ωcm including about ³ ) (1) and boron of 60K
Ion implantation was carried out at a dose of eV, 5 × 10 ¹² to 1 × 10 ¹³ / cm ² . Hereinafter, examples using boron will be described, but the present invention is effective even if a trivalent substance is used instead of boron.

Next, heat treatment was performed at 1000 ° C. to diffuse the impurities introduced by ion implantation into the substrate to form a p-type well (4) having a depth of about 3 μm (FIG. 5).
(B)).

Next, the oxide film (2) is removed to expose a clean silicon surface, and then an oxide film is formed again on the exposed silicon surface.

A silicon substrate having an oxide film grown on its surface is loaded into a molecular beam epitaxial apparatus and heated at 850 ° C. for 20 minutes in an ultrahigh vacuum. As a result, the oxide film is sublimated and the clean silicon surface is exposed. A silicon layer called a buffer layer (not shown) is grown on this clean silicon surface by about 10 to 20 nm.
Then, boron is evaporated from an evaporator called a K-cell. The substrate temperature at this time is 500 ° C. or lower. 1
Boron (6) is adsorbed on the buffer layer with an areal density of 0 ¹³ / cm ² . This buffer layer is called delta doping because the boron concentration sharply increases. And
A silicon film (7) is epitaxially grown to a thickness of about 50 nm on this buffer layer. The substrate temperature was 700 ° C. to improve crystallinity. (FIG. 5C) After taking out the silicon substrate from the molecular beam epitaxial device,
An oxide film (9) is grown as shown in (d). Then, in order to enhance the element isolation capability, that is, to prevent the silicon surface in the element isolation region from being inverted and forming a conductive layer, boron is ion-implanted into the surface. Since this oxide film (9) becomes a gate oxide film of a MOS structure that forms an element isolation region, it must have excellent insulation and reliability. Further, at this time, since the substrate is already delta-doped with boron, the oxidation temperature should be lowered as much as possible. Therefore, in the present invention, a high pressure oxidation method that can lower the oxidation temperature is used. The oxidizing atmosphere is water vapor, the pressure is 9 atm, and the temperature is 800 ° C. Under this condition, an oxide film of 20 to 30 nm is grown.

Next, as shown in FIG. 6 (a), polycrystalline silicon (10) defining the element isolation region is deposited on this oxide film (9) by a known vapor deposition method. The gas used is disilane (Si ₂ H ₆ ) and is thermally decomposed at about 520 ° C. As a result, an amorphous silicon film is deposited on the substrate. The film thickness is 100 nm. Further, in the present invention, a method of simultaneously mixing foshin (PH ₃ ) is adopted. As a result, the number of steps and the number of thermal cycles are reduced as compared with the method of introducing impurities by ion implantation. Although the polycrystalline silicon (10) is made n-type using fossine here, it is needless to say that boron can be introduced to make it p-type. When the p-type is used, the work function difference between the polycrystalline silicon (10) and the semiconductor substrate becomes small, so that the interface between the oxide film and the semiconductor becomes difficult to invert, and the element isolation characteristic is improved. Further, an oxide film (11) was deposited on this polycrystalline silicon. Since this oxide film (11) is a film that insulates the polycrystalline silicon (10) and has a relatively large film thickness of 100 nm, in this embodiment, a deposition method using plasma discharge was adopted. In this method, a gas containing silicon and a gas containing oxygen are mixed in a vacuum container, and the gas is discharged to deposit an oxide film. The oxidation temperature is about 450 ° C.

Next, as shown in FIG. 6B, a desired organic film pattern (8) is formed by using a known photolithography method. Then, the underlying oxide film (11) and polycrystalline silicon film (10) are processed by using this organic film (resist) as a mask. Then, the organic film serving as a processing mask is removed, and the substrate surface is washed.

Next, when an oxide film is again deposited on the surface of the substrate by the plasma oxide film deposition method and anisotropic etching is performed by the known dry etching method, as shown in FIG. 6 (c). The sidewall oxide film (12) remains only on the sidewalls of the polycrystalline silicon (10) and the oxide film (11), and the polycrystalline silicon (10) is insulated. At this time, the oxide film (9) on the surface not covered with polycrystalline silicon is also removed, and the substrate surface is exposed.

Next, as shown in FIG.
The gate oxide film (14) of the device was formed by using a known thermal oxidation method. Since the gate oxide film is as thin as 5 nm,
Delta-doped boron does not diffuse much even if a thermal oxidation method at 800 ° C. is used for its formation. On top of this,
A silicon film containing the above impurities was deposited and processed into a desired gate electrode shape (15).

Next, as shown in FIG. 7A, the gate electrode (15) is used as a mask to ion-implant the impurities forming the source / drain impurity layers of the MOS device. The impurity is arsenic, the implantation energy is 10 to 20 KeV, and the dose is 5 × 10 ¹⁴ to 5 × 10 ^15.
/ Cm ² . Under this implantation condition, as shown in the figure, it was possible to form the impurity layer (16) having the tip at a position deeper than the delta-doped layer (6).

Finally, as shown in FIG. 7B, an interlayer insulating film (18) is deposited to a thickness of about 500 nm, a contact hole is opened, and this is backfilled with a metal (19) such as tungsten. Wiring metal (20) is formed to complete the MOS device. An oxide film containing a large amount of phosphorus was used as the interlayer insulating film (18). The formation temperature is 450 ° C.

In this embodiment, in order to simplify the explanation,
Although a so-called single drain structure was adopted as the MOS element, a known L-D-D structure (LDD:
It goes without saying that Lightly Doped Drain) can be adopted. Further, although the n-type channel MOS element has been described, if the conductivity type of the substrate is reversed, a p-type channel MO element is formed.
The S element can be produced by the same process. When the conductivity type of the substrate is reversed, a pentavalent substance such as antimony may be used as an impurity to be delta-doped to form the punch-through stopper layer.

In the second embodiment, an example in which the present patent application is applied to the fabrication of a CMOS device will be described. In a CMOS device, since semiconductor regions having different conductivity types exist inside the same substrate, a punch through stopper layer of a MOS device must be formed separately. However, it is practically impossible to make different layers not only by the molecular beam epitaxial method but also by the method of growing silicon on the entire surface of the substrate. Therefore, in this embodiment, as described above, the punch-through stopper for the p-type channel MOS element is formed by utilizing the fact that arsenic having a small distribution can be used, so that the punch-through stopper for the n-type channel MOS element is formed. We have devised a realistic CMOS device process that utilizes the molecular beam epitaxial method only in the above.

First, semiconductor regions having different conductivity types are formed inside the semiconductor substrate. For this, a known process for forming a double well structure was adopted. First, as shown in FIG. 8A, a silicon substrate of the first conductivity type (specifically, 10 Ωcm containing boron of about 1 × 10 ¹⁵ / cm ^3).
On the silicon substrate), an oxide film is grown to about 10 nm,
Further, a silicon nitride film having a thickness of about 200 nm is deposited by a known vapor deposition method.

Next, as shown in FIG. 8B, a part of the nitride film is removed by the known lithography method and dry etching method. To form an n-type well in this region, phosphorus is added at an accelerating voltage of 125 KeV to about 1 × 10 ¹³ /
I hit about cm ² . At this time, since the remaining nitride film (3) serves as a mask, phosphorus ions are not implanted into the region where the nitride film exists.

Next, as shown in FIG. 8C, when the substrate is oxidized using the nitride film (3) as a mask, oxygen does not pass through the nitride film, so that the oxide film ( 2 ') grows. The film thickness is 100 nm.

Next, as shown in FIG. 8D, after selectively removing the nitride film, boron was implanted at an acceleration voltage of 60 KeV to about 7 × 10 ¹² / cm ² to form a p-type well. . At this time, since the region to be the n-type well is covered with the oxide film (2 ′), boron ions are not implanted.

Next, as shown in FIG. 9A, 100
Heat treatment was performed at 0 ° C. to diffuse the impurities introduced by ion implantation into the inside of the substrate to form a p-type well (4) and an n-type well (5) having a depth of about 3 μm.

Further, as shown in FIG. 9B, 2 '
The second oxide film is removed so that the second oxide film is left. A hydrofluoric acid solution was used to remove the oxide film, but since the film thickness of 2'is 10 times or more thicker than the oxide film of 2, the 2'oxide film can be left by controlling the etching time.

Next, as shown in FIG. 9C, a boron delta-doped layer (6) and a silicon epitaxial layer (7) are formed on the surface of this semiconductor substrate by the procedure described in the first embodiment. Form. At this time, the silicon film formed on the oxide film (2 ′) becomes an amorphous silicon film.

Since an element cannot be formed on the amorphous silicon film, a step of removing only this amorphous silicon film is performed. Therefore, as shown in FIG. 9D, an organic film mask covering the p-type well region (4) is formed and the amorphous silicon film is removed. When the amorphous silicon film is removed, the n-type well region (5) is not affected by etching because the oxide film (2 ′) serves as a base (FIG. 1).
0 (a)). Next, after removing the organic film (8) used as a mask, the oxide film (2 ′) is removed with a hydrofluoric acid solution,
As shown in 0 (b), the substrate surface is exposed. As shown in the figure, the delta-doped p-type well region (4) is higher than the n-type well region (5) by the epitaxially grown silicon film (7). However, the height is about 100 nm at most.

Now, as described above, the MOS element is prepared. The difference from the above-described embodiment is that the n-type and p
This is the point that ion implantation using a mask is necessary to form a MOS device of the mold channel. First, Fig. 1
As shown in 0 (c), a 20 nm oxide film (9) is grown on the surface. The high-pressure oxidation method described above was used to grow the oxide film. Then, the p-type well region (4) is covered, and impurities are ion-implanted into the surface of the n-type well region. The purpose is to improve the element isolation characteristics as described above. Here, phosphorus is 20 KeV and 5 × 10 ¹¹
I hit about / cm ² . Next, as shown in FIG. 10D, boron is ion-implanted so as to cover the n-type well region. Accelerating voltage is 20 KeV and dose is 5x10.
It is about ¹¹ / cm ² . These ion implantations prevent the threshold voltage of the MOS structure from rising and prevent the MOS interface from being inverted.

Next, as shown in FIG. 11A, an impurity (specifically, phosphorus is contained in a high concentration) silicon film (10) is deposited on the oxide film (9) and further oxidized. Membrane (11)
To form.

Next, as shown in FIG. 11B, the oxide film (11) and the silicon film (10) are separated into a desired shape by a known lithography method and a dry etching method, and the element is separated. Determine the separation area.

Further, as shown in FIG. 11C, a side wall insulating film (12) is formed on the side wall of the silicon film (10) to insulate the silicon film (10). At the time of electrical element isolation, the potential of polycrystalline silicon is set to 0V. Due to the above-mentioned ion implantation, the concentration on the silicon surface is increased, and as a result, the threshold voltage of the MOS structure is also increased.
In this case, the inversion layer is not formed, and no current flows in the region covered with polycrystalline silicon. In particular, in the n-type well region (5), since the polycrystalline silicon (10) and the substrate have the same conductivity type, a state in which the threshold voltage is essentially high can be realized, so that the element isolation characteristics are excellent. .

Next, as shown in FIG. 11 (d), the p-type well region (4) is covered with the organic film mask (8), and the n-type well region (5) is punched with arsenic as a punch-through stopper. (13) is formed. Implantation energy is 100 Ke
The V and dose amounts are about 1 × 10 ¹³ / cm ² .

Next, as shown in FIG. 12A, a gate oxide film (14) and a gate electrode (15) are formed.
Here again, polycrystalline silicon containing a high concentration of phosphorus was used.
As described above, the gate electrode structure may be an LDD structure, or may be a stacked film of a silicide film which is a compound of polycrystalline silicon and silicon. Furthermore, by forming the gate electrode of the p-type channel MOS element from p-type polycrystalline silicon, it is possible to form a surface channel type element.

Next, in order to form the source / drain impurity layer of the MOS element, as shown in FIGS. 12C and 12D, one conductivity type region is masked and ion implantation is performed. To do. In the case of an n-type channel MOS element, arsenic is implanted under the conditions of ¹⁵ KeV and 2 × 10 ¹⁵ / cm ² to form an impurity layer (16) serving as a source / drain. In the case of a p-type channel MOS element, BF ₂
Is applied under the conditions of ¹⁵ KeV, 2 × 10 ¹⁵ / cm ² ,
An impurity layer (17) to be a source / drain was formed.

Finally, the formation of the interlayer insulating film (18), the opening of the contact hole, and the metal (19) of the contact hole.
Backfilling was performed to form a wiring metal, thus completing a CMOS device having a delta-doped layer.

As described above, polycrystalline silicon (1
0) is used, but in this method, a wide area called an element isolation region is covered only by the gate insulating film under the polycrystalline silicon (10). There is a problem that the probability of causing it is high. Therefore, if the conventional element isolation oxide film can be used, it is preferable. Therefore, in the next embodiment, an example of forming a CMOS device adopting the known selective epitaxial growth method will be described. The selective epitaxial growth method is a technique in which a single crystal film of silicon is grown only in a region where the surface of a silicon substrate is exposed and growth is not caused in a region covered with an insulating film such as an oxide film. However, since the growth temperature is 800 ° C. or higher, which is higher than the growth temperatures of the epitaxial films described in the above examples, there is a drawback that it is difficult to maintain a steep doping profile. A MOSFET using this selective epitaxial growth method is disclosed in JP-A-63-2116.
79 and Japanese Patent Laid-Open No. 4-179160, the examples use a high-concentration substrate, and there is no mention of using a steep impurity profile as in the present invention. Hereinafter, the third embodiment will be described with reference to FIGS.
Use to explain.

FIG. 13A shows the first conductivity type semiconductor substrate (1) in the same manner as the steps up to FIG. 9A of the second embodiment.
It is a figure which shows a place where well regions (4, 5) are formed.

The surface of the substrate on which the well region is formed is shown in FIG.
As shown in (b), a nitride film (3) serving as a mask at the time of selective oxidation is deposited and processed into a desired shape.

When this substrate is placed in a high temperature oxidizing atmosphere, an oxide film (2) grows in a region not covered with the nitride film, and the cross section becomes as shown in FIG. 13 (c). Specifically, 1100
An oxide film having a thickness of 400 nm was grown in an oxidizing atmosphere at 0 ° C.

Next, as shown in FIG. 13D, the surface of the p-type well region (4) is removed by masking the n-type well region (5) after removing the nitride film (3). Only the n-type well region (5) is covered with the oxide film.

Next, this substrate is loaded into an epitaxial growth furnace. The epitaxial device used in this example is adapted to introduce a gas containing silicon.
This is the difference from the device using the evaporation source described in the second embodiment. First, as shown in FIG. 14A, a gas containing boron, specifically diborane, is introduced to deposit boron (6) on the entire surface of the substrate. Further, a gas containing silicon, specifically disilane, is introduced and the growth temperature is set to 800.
When the temperature is maintained at about ° C, the silicon single crystal film (7) grows only on the surface of the silicon substrate having no oxide film. Boron is deposited on the entire surface of the substrate, but its surface density is low, so
It does not hinder the growth of the silicon single crystal film.

Next, as shown in FIG. 14B, the boron (6) on the oxide film on the n-well region 5 is removed. For removing the boron (6), there is a method of using a mask or cleaning the surface. Then, the oxide film on the n-type well region (5) is further removed to expose the surface of the silicon substrate.

Then, as shown in FIG. 14C, p
Only the type well region (4) is covered with a mask, and a punch through stopper (13) is formed in the n type well region (5) with arsenic. The implantation energy is 100 KeV and the dose is about 1 × 10 ¹³ / cm ² .

Next, as shown in FIG. 14D, a gate oxide film (14) and a gate electrode (15) are formed.
Here again, polycrystalline silicon containing a high concentration of phosphorus was used.
As described above, the gate electrode structure may be an LDD structure, or may be a stacked film of a silicide film which is a compound of polycrystalline silicon and silicon. Furthermore, by forming the gate electrode of the p-type channel MOS element from p-type polycrystalline silicon, it is possible to form a surface channel type element.

Next, as shown in FIG. 15A, source / drain impurity layers (16, 17) of the p-type channel and n-type channel MOS devices are formed. In the case of n-type channel MOS element, arsenic is 15 KeV, 2
Implanted under the condition of x10 ¹⁵ / cm ² , impurity layer (16)
In the case of a p-type channel MOS element, BF ₂ was implanted under the conditions of ¹⁵ KeV and 2 × 10 ¹⁵ / cm ² to form an impurity layer (17).

Finally, as shown in FIG. 15B, an inter-layer insulating film (18) is formed, contact holes are opened, and the contact holes are backfilled with a metal (19) to form a wiring metal. And CM with delta-doped layer
The OS element was completed.

FIG. 16 is a plan view of a CMOS type inverter using the semiconductor device formed in the second embodiment of the present invention. Although it is almost the same as the conventional CMOS, a contact for supplying power to the element isolation pattern made of polycrystalline silicon (10) in FIG. 2 is required.
Here, 30 is a pattern for forming an n-type well, the region surrounded by this becomes an n-type well, and the other region becomes a p-type well. Reference numeral 31 defines an element isolation pattern. The region surrounded by this becomes an active region of the element, and an impurity layer and a channel are formed. Three
2 is a gate electrode. 33 is a pattern for implanting impurities into respective regions when forming a p-type channel MOS element and an n-type channel MOS element. 34
Indicates a contact hole, and 35 indicates a wiring metal pattern.

[0058]

As described above, according to the method of manufacturing a semiconductor device of the present invention, a punch-through stopper having a very rapid concentration distribution can be formed, so that the impurity concentration near the channel can be reduced. The punch-through phenomenon can be significantly suppressed. As a result, the short channel characteristics could be significantly improved without lowering the threshold voltage. Specifically, it was possible to obtain stable operation up to a MOS element having a channel length of 0.1 μm. Further, although it has been considered that the epitaxial method is not suitable for the fabrication of the CMOS device so far, according to the present invention, the CMOS device having the delta-doped layer can be realized by a practical method using the conventional semiconductor process. Became. Therefore, the performance of the CMOS device is significantly improved. By using the delta doping technique, the depth of the punch-through stopper layer and the impurity layer of the MOS element can be controlled, so that the capacitance of the junction formed by them can be reduced.

As a result of the above, MO of 0.1 micron level
S element was realized.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a conventional semiconductor device.

FIG. 4 is a schematic diagram showing an impurity distribution inside a semiconductor substrate.

FIG. 5 is a manufacturing process diagram (1) of the semiconductor device according to the first embodiment of the invention.

FIG. 6 is a manufacturing process diagram (2) of the semiconductor device according to the first embodiment of the invention.

FIG. 7 is a manufacturing process diagram (3) of the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a manufacturing process diagram (1) of a semiconductor device according to a second embodiment of the present invention.

FIG. 9 is a manufacturing process diagram (2) of the semiconductor device according to the second embodiment of the present invention.

FIG. 10 is a manufacturing process diagram (3) of the semiconductor device according to the second embodiment of the present invention.

FIG. 11 is a manufacturing process diagram (4) of the semiconductor device according to the second embodiment of the present invention.

FIG. 12 is a manufacturing process diagram (5) of a semiconductor device according to a second embodiment of the present invention.

FIG. 13 is a manufacturing process diagram (1) of a semiconductor device according to a third embodiment of the present invention.

FIG. 14 is a manufacturing process diagram (2) of a semiconductor device according to the third embodiment of the present invention.

FIG. 15 is a manufacturing process diagram (3) of a semiconductor device according to a third embodiment of the present invention.

FIG. 16 is a plan view of a CMOS inverter using the semiconductor device of the present invention.

[Explanation of symbols]

1-semiconductor substrate, 2, 2'-oxide film, 3-nitride film, 4-
p-type well region, 5-n-type well region, 6-delta doped layer, 7-silicon epitaxial film, 8-organic film mask, 9-oxide film, 10-silicon film, 11-oxide film, 1
2-side wall oxide film, 13-punch through stopper layer by arsenic implantation, 14-gate oxide film, 15-gate electrode, 16-n type impurity layer, 17-p type impurity layer, 18-
Interlayer insulating film, 19-metal, 20-metal wiring, 30-n type well region forming pattern, 31-element isolation film forming pattern, 32-gate electrode forming pattern, 33-impurity ion implantation pattern, 34-contact pattern, Three
5-Wiring pattern.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/092

Claims (8)

[Claims] 1. A first surface of a first conductivity type is formed on a main surface of a semiconductor substrate.
Forming a first impurity layer having an impurity concentration of
Of the first impurity concentration formed on the impurity layer of
A second of the first conductivity type having a second concentration more than twice as high
And forming a third impurity layer of the first conductivity type having a third concentration 10 times or more lower than the second impurity concentration formed on the second impurity layer. First
And the step of forming a first insulating film on the third impurity layer, forming a first conductive film on the first insulating film,
A second insulating film is formed on the conductive film, and the second insulating film and the first conductive film are formed into a desired pattern, and a sidewall insulating film is formed on the exposed side wall of the first conductive film. By forming, a second step of forming the element isolation region mainly composed of the first conductive film, and forming a gate electrode, a source impurity region and a drain impurity region in the active region surrounded by the element isolation region And a third step of: forming the source impurity region and the drain impurity region from the third impurity layer to the inside of the first impurity layer. 2. The first conductivity type is formed as a p-type, the second impurity layer contains boron, and the thickness thereof is formed between 1 nanometer and 20 nanometers inclusive, and the third impurity layer is formed.
The method for manufacturing a semiconductor device according to claim 1, wherein the impurity layer is formed to have a thickness of 30 nanometers or more and 50 nanometers or less. 3. The first conductivity type is formed as an n-type, the second impurity layer contains antimony, and the thickness thereof is formed between 1 nanometer and 20 nanometers inclusive, and the third impurity is formed. The method of manufacturing a semiconductor device according to claim 1, wherein the layer is formed to have a thickness of 30 nanometers or more and 50 nanometers or less. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductive film is made of polycrystalline silicon. 5. A device isolation oxide film is formed on the main surface of a semiconductor substrate by oxidation, and a first conductivity type first impurity concentration is provided on a first active region surrounded by the device isolation oxide film. Forming a first impurity layer and forming a second impurity layer of the first conductivity type having a second concentration 10 times or more higher than the first impurity concentration formed on the first impurity layer; A first step of forming a third impurity layer of the first conductivity type having a third concentration 10 times or more lower than the concentration of the second impurity formed on the second impurity layer. And a second step of forming a gate electrode, a source impurity region and a drain impurity region in the first active region, wherein the source impurity region and the drain impurity region are formed from the third impurity layer to the first impurity region. Semiconductor device characterized by being formed in the impurity layer of The method of production. 6. The first conductivity type is formed as a p-type, the second impurity layer contains boron, and the thickness thereof is formed between 1 nanometer and 20 nanometers inclusive, and the third impurity layer is formed.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the impurity layer is formed to have a thickness of 30 nanometers or more and 50 nanometers or less. 7. The first conductivity type is formed as an n-type, the second impurity layer contains antimony, and the thickness thereof is formed between 1 nanometer and 20 nanometers inclusive, and the third impurity is formed. The method for manufacturing a semiconductor device according to claim 5, wherein the layer is formed to have a thickness of 30 nanometers or more and 50 nanometers or less. 8. The method of manufacturing a semiconductor device according to claim 5, wherein the first conductive film is made of polycrystalline silicon.