JPH06188383A - Semiconductor memory and manufacture thereof - Google Patents
Semiconductor memory and manufacture thereofInfo
- Publication number
- JPH06188383A JPH06188383A JP5166751A JP16675193A JPH06188383A JP H06188383 A JPH06188383 A JP H06188383A JP 5166751 A JP5166751 A JP 5166751A JP 16675193 A JP16675193 A JP 16675193A JP H06188383 A JPH06188383 A JP H06188383A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- insulating film
- charge storage
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 238000003860 storage Methods 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 claims abstract description 29
- 239000003990 capacitor Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 239000010408 film Substances 0.000 description 81
- 239000010409 thin film Substances 0.000 description 9
- 230000002093 peripheral effect Effects 0.000 description 6
- 238000009413 insulation Methods 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体記憶装置およびそ
の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and its manufacturing method.
【0002】なお、本明細書の記述は本件出願の優先権
の基礎たる大韓民国特許出願第1992−12085号
の明細書の記載に基づくものであって、当該大韓民国特
許出願の番号を参照することによって当該大韓民国特許
出願の明細書の記載内容が本明細書の一部分を構成する
ものとする。The description of this specification is based on the description of the specification of Korean Patent Application No. 1992-12085, which is the basis of the priority of the present application. By referring to the number of the Korean patent application, The content of the description of the Korean patent application constitutes a part of the present specification.
【0003】[0003]
【従来の技術】一般的に、メモリ素子のうち最も多くの
消費を占めているDRAMの集積化において最も問題に
なる事項はセルの電荷貯蔵容量の確保である。2. Description of the Related Art Generally, the most problematic factor in integration of DRAM, which is the most consuming memory device, is to secure the charge storage capacity of the cell.
【0004】DRAMセルの電荷貯蔵容量に最も重要な
変数として電荷貯蔵電極の表面の広さと誘電膜の厚さを
挙げることができる。The most important variables for the charge storage capacity of the DRAM cell are the surface area of the charge storage electrode and the thickness of the dielectric film.
【0005】従来のDRAMにおいては、半導体基板の
表面にMOSFETを形成して周辺とセル回路を構成
し、トレンチ(trench)型や積層型構造を用いて
セルキャパシタ有効面積を増大させる方法を取ってい
る。In a conventional DRAM, a method of increasing the effective area of a cell capacitor by forming a MOSFET on the surface of a semiconductor substrate to form a cell circuit with the periphery and using a trench type or laminated type structure is adopted. There is.
【0006】しかし、上記従来のDRAMはトポロジ
(topology)増大に伴う工程の複雑性とその限
界点に到達する問題点があった。However, the above-mentioned conventional DRAM has a problem that the process complexity and the limit point thereof are reached due to the increase in the topology.
【0007】[0007]
【発明が解決しようとする課題】本発明は上記問題点を
解決するために案出されたもので、フィールド酸化膜の
段差による有効面積増大および並列構造のキャパシタを
形成することにより、電荷貯蔵電極の充分なキャパシタ
ンスを確保できる半導体記憶装置およびその製造方法を
提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been devised to solve the above-mentioned problems, and a charge storage electrode is formed by increasing the effective area due to the step of the field oxide film and forming a capacitor having a parallel structure. It is an object of the present invention to provide a semiconductor memory device capable of ensuring a sufficient capacitance and a manufacturing method thereof.
【0008】[0008]
【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体記憶装置は、単位セルに形成された
キャパシタを有する半導体記憶装置において、半導体基
板1;前記半導体基板1上に一定間隔で形成されたフィ
ールド酸化膜2とキャパシタが形成される前記半導体基
板1上に形成された第1絶縁膜4;前記第1絶縁膜4上
に形成され、かつ多数のフィールド酸化膜2に亘って形
成された第1プレート電極6;前記第1プレート電極6
上に形成された第1誘電膜8;前記第1誘電膜8上に形
成され、かつ隣接した二つのフィールド酸化膜に亘って
形成された第1電荷貯蔵電極9;前記第1電荷貯蔵電極
9および第1プレート電極6を覆う第2絶縁膜10;前
記フィールド酸化膜2および第2プレート電極4が形成
されていない半導体基板1の所定部位にコンタクトを成
し、前記第2絶縁膜10上部の一定部位に亘って形成さ
れたポリシリコン基板12;前記ポリシリコン基板12
に形成されたゲート絶縁膜13,ゲート電極14および
活性領域16;前記ゲート電極14,ワード線15およ
び活性領域16を覆う第3絶縁膜17;前記第3絶縁膜
17を覆い前記第1電荷貯蔵電極9と接続し、かつ前記
活性領域16に接続された第2電荷貯蔵電極18;前記
第2電荷貯蔵電極18上に蒸着された第2誘電膜19;
前記第2誘電膜19上に形成され、かつ別のワードライ
ンの形成部位上部まで拡張された第2プレート電極2
0;前記第2プレート電極20を覆う第4絶縁膜21;
および前記活性領域16にコンタクトされて前記第4絶
縁膜21上に形成されたビットライン22を具備したこ
とを特徴とする。In order to achieve the above object, a semiconductor memory device of the present invention is a semiconductor memory device having a capacitor formed in a unit cell, a semiconductor substrate 1; A field insulating film 2 formed at intervals and a first insulating film 4 formed on the semiconductor substrate 1 on which a capacitor is formed; formed on the first insulating film 4 and extending over a large number of field oxide films 2. Formed first plate electrode 6; the first plate electrode 6
A first dielectric film 8 formed thereon; a first charge storage electrode 9 formed on the first dielectric film 8 and extending over two adjacent field oxide films; the first charge storage electrode 9 And a second insulating film 10 covering the first plate electrode 6; a contact is made with a predetermined portion of the semiconductor substrate 1 where the field oxide film 2 and the second plate electrode 4 are not formed, Polysilicon substrate 12 formed over a certain portion; Polysilicon substrate 12
Formed on the gate insulating film 13, the gate electrode 14 and the active region 16; the third insulating film 17 covering the gate electrode 14, the word line 15 and the active region 16; the first charge storage covering the third insulating film 17; A second charge storage electrode 18 connected to the electrode 9 and connected to the active region 16; a second dielectric film 19 deposited on the second charge storage electrode 18;
A second plate electrode 2 formed on the second dielectric film 19 and extended to an upper portion of another word line formation portion.
0; fourth insulating film 21 covering the second plate electrode 20;
And a bit line 22 contacting the active region 16 and formed on the fourth insulating layer 21.
【0009】さらに、本発明による半導体記憶装置の製
造方法は、単位セルに形成されたキャパシタを有する半
導体記憶装置の製造方法において、半導体基板1にフィ
ールド酸化膜2を形成し、第1絶縁膜4を薄く形成し、
第1プレート電極6を形成し、前記第1プレート電極6
上に第1誘電膜8を形成する工程と;前記第1誘電膜8
上に第1電荷貯蔵電極9を形成した後、第2絶縁膜10
を形成する工程と;前記フィールド酸化膜2が形成され
ていない所定部位の前記半導体基板1を露出させ、ポリ
シリコン膜を前記第1電荷貯蔵電極9上に形成されてい
る第2絶縁膜10上に亘って形成してポリシリコン基板
12を形成する工程と、;前記ポリシリコン基板12に
活性領域16,ゲート絶縁膜13およびゲート電極14
を有するFETを形成し、かつポリシリコン基板12に
形成される前記ゲート電極13と前記第2絶縁膜10上
に形成されるワード線15を同時に形成する工程と;全
体構造上部に第3酸化膜17を形成し、前記第1電荷貯
蔵電極9上に接続される第2電荷貯蔵電極18を前記活
性領域16と接続するよう形成する工程;第2誘電膜1
9を前記第2電荷貯蔵電極18上に形成し、次いで前記
第2誘電膜19上にプレート電極20を形成する工程
と;全体構造上部に第4絶縁膜21を形成し、前記活性
領域16とビット線22をコンタクトさせる工程を有す
ることを特徴とする。Further, the method of manufacturing a semiconductor memory device according to the present invention is the same as the method of manufacturing a semiconductor memory device having a capacitor formed in a unit cell, in which a field oxide film 2 is formed on a semiconductor substrate 1 and a first insulating film 4 is formed. Thinly,
The first plate electrode 6 is formed, and the first plate electrode 6 is formed.
Forming a first dielectric film 8 thereon; the first dielectric film 8
After forming the first charge storage electrode 9 on the second insulating film 10
Forming a polysilicon film on the second insulating film 10 formed on the first charge storage electrode 9 by exposing the semiconductor substrate 1 at a predetermined portion where the field oxide film 2 is not formed. Forming a polysilicon substrate 12 over the entire surface of the polysilicon substrate 12, the active region 16, the gate insulating film 13, and the gate electrode 14 on the polysilicon substrate 12.
And a word line 15 formed on the second insulating film 10 and the gate electrode 13 formed on the polysilicon substrate 12, and a third oxide film is formed on the entire structure. Forming a second charge storage electrode 18 connected to the active region 16 and forming a second charge storage electrode 18 on the first charge storage electrode 9;
9 is formed on the second charge storage electrode 18, and then a plate electrode 20 is formed on the second dielectric film 19; a fourth insulating film 21 is formed on the entire structure, and the active region 16 is formed. The method is characterized by including a step of contacting the bit line 22.
【0010】[0010]
【作用】本発明においては、半導体基板表面とフィール
ド酸化膜の段差で生じた面積を第1次有効キャパシタ面
積として使用してセル当り電荷貯蔵容量を増加させ、こ
れをさらに電荷貯蔵コンタクトホールを利用して電荷貯
蔵電極と薄膜MOSFETの活性領域を電荷貯蔵電極と
同時に接続させて第2次有効キャパシタ面積でキャパシ
タ容量を増加させることができる。In the present invention, the area generated by the step between the surface of the semiconductor substrate and the field oxide film is used as the primary effective capacitor area to increase the charge storage capacity per cell, and this is further utilized as the charge storage contact hole. Then, the charge storage electrode and the active region of the thin film MOSFET can be connected simultaneously with the charge storage electrode to increase the capacitance of the secondary effective capacitor area.
【0011】[0011]
【実施例】以下、添付された図1および図2〜図6を参
照して本発明による一実施例のDRAMの構造とその製
造方法を詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a DRAM according to an embodiment of the present invention and a method of manufacturing the same will be described in detail below with reference to the accompanying drawings FIG. 1 and FIGS.
【0012】図面において、便宜上左側には周辺部の基
板MOSFETの断面を、右側にはビット線と平行した
方向のセルの断面を示し、図2〜図6ではビット線形成
工程までのみを示す。In the drawings, for convenience, the cross section of the peripheral substrate MOSFET is shown on the left side, and the cross section of the cell in the direction parallel to the bit line is shown on the right side, and only the bit line forming step is shown in FIGS.
【0013】先ず、本発明による一実施例のDRAM構
造を図1を参照して詳細に説明する。First, a DRAM structure of an embodiment according to the present invention will be described in detail with reference to FIG.
【0014】図1に示す通り、周辺回路として半導体基
板1に活性領域7,ゲート酸化膜3,ゲート電極5を有
する一般的なトランジスタの一種であるMOSFETが
示されている。そして、セルは並列キャパシタ構造を形
成している。As shown in FIG. 1, there is shown a MOSFET which is a kind of general transistor having an active region 7, a gate oxide film 3 and a gate electrode 5 on a semiconductor substrate 1 as a peripheral circuit. The cells then form a parallel capacitor structure.
【0015】先ず、半導体基板1とこの半導体基板1上
に一定間隔でフィールド酸化膜2を形成して、このフィ
ールド酸化膜2上に酸化膜4が形成される。First, the semiconductor substrate 1 and the field oxide film 2 are formed on the semiconductor substrate 1 at regular intervals, and the oxide film 4 is formed on the field oxide film 2.
【0016】キャパシタ形成のためのプレート電極6
は、多数のフィールド酸化膜2を経て酸化膜4上に形成
され、誘電膜8が上記プレート電極6上に形成される。Plate electrode 6 for forming a capacitor
Is formed on the oxide film 4 through a large number of field oxide films 2, and a dielectric film 8 is formed on the plate electrode 6.
【0017】そして、電荷貯蔵電極9は誘電膜8上に形
成され、隣接する二つのフィールド酸化膜2に亘って形
成される。The charge storage electrode 9 is formed on the dielectric film 8 and extends over the two adjacent field oxide films 2.
【0018】酸化膜10が電荷貯蔵電極9およびプレー
ト電極6上を覆うように形成され、フィールド酸化膜2
およびプレート電極6が形成されていない半導体基板1
の所定部位にコンタクトを形成し、酸化膜10上部の一
定部位に亘ってポリシリコン基板12(ポリシリコン
膜)が形成される。The oxide film 10 is formed so as to cover the charge storage electrode 9 and the plate electrode 6, and the field oxide film 2 is formed.
And the semiconductor substrate 1 on which the plate electrode 6 is not formed
Then, a contact is formed at a predetermined portion of, and a polysilicon substrate 12 (polysilicon film) is formed over a certain portion above the oxide film 10.
【0019】ポリシリコン基板12にゲート酸化膜1
3,ゲート電極14,活性領域16が形成される。さら
に、酸化膜17はゲート電極14と活性領域16を覆っ
ており、電荷貯蔵電極18は上記酸化膜17上に形成さ
れ、かつ電荷貯蔵電極9および上記活性領域16に接続
された形態を有する。A gate oxide film 1 is formed on the polysilicon substrate 12.
3, the gate electrode 14 and the active region 16 are formed. Further, the oxide film 17 covers the gate electrode 14 and the active region 16, and the charge storage electrode 18 is formed on the oxide film 17 and connected to the charge storage electrode 9 and the active region 16.
【0020】並列型キャパシタを形成するために、誘電
膜19が電荷貯蔵電極18上に形成され、プレート電極
20が誘電膜19上に形成されて、別のワードライン形
成部位の上部まで拡張される。そして、プレート電極2
0の絶縁のために酸化膜21がプレート電極20と酸化
膜17上に形成され、ビットライン22が活性領域16
にコンタクトされながら酸化膜21上に形成される。To form a parallel type capacitor, a dielectric film 19 is formed on the charge storage electrode 18, and a plate electrode 20 is formed on the dielectric film 19 and extended to the upper part of another word line formation site. . And the plate electrode 2
An oxide film 21 is formed on the plate electrode 20 and the oxide film 17 for 0 insulation, and the bit line 22 is connected to the active region 16
Is formed on the oxide film 21 while being in contact with.
【0021】本発明によるDRAM製造方法の一実施例
を図2〜図6を参照して詳細に説明する。One embodiment of the DRAM manufacturing method according to the present invention will be described in detail with reference to FIGS.
【0022】先ず、図2の通り、半導体基板1に周辺回
路の素子間の絶縁とセルキャパシタ有効面積増大のため
のフィールド酸化膜2を形成し、周辺部の半導体基板M
OSFETのゲート酸化膜3であると共に、セルの半導
体基板1を絶縁させる酸化膜4を成長させる。次いで、
周辺回路の基板1とセルに形成されているゲート酸化膜
3および酸化膜4上にポリシリコンを蒸着して不純物注
入を行いMOSFETのゲート電極5およびプレート電
極6を所定の寸法に形成する。このとき、上述した周辺
回路のMOSFETは電気的特性を向上させるためにス
ペーサ酸化膜3Aと活性領域7を有するLDD(Lig
htly Doped Drain)構造を有するよう
に形成する。First, as shown in FIG. 2, a field oxide film 2 is formed on a semiconductor substrate 1 for insulation between elements of a peripheral circuit and for increasing an effective area of a cell capacitor.
An oxide film 4 is grown that is the gate oxide film 3 of the OSFET and also insulates the semiconductor substrate 1 of the cell. Then
Polysilicon is vapor-deposited on the gate oxide film 3 and the oxide film 4 formed on the substrate 1 and the cells of the peripheral circuit and impurities are implanted to form the gate electrode 5 and the plate electrode 6 of the MOSFET in predetermined dimensions. At this time, the MOSFET of the peripheral circuit described above has an LDD (Lig) having a spacer oxide film 3A and an active region 7 in order to improve electric characteristics.
It is formed so as to have an htly doped drain) structure.
【0023】図3に示す通り、プレート電極6上にON
O(酸化物・窒化物・酸化物)またはNO(窒化物・酸
化物)の複合構造キャパシタ誘電膜8を成長した後、ポ
リシリコンで第1の電荷貯蔵電極9を誘電膜8上に形成
し、層間絶縁のための酸化膜10を蒸着する。そして、
プレート電極6が形成されていない半導体基板1の表面
を露出するための感光膜11パターンを形成する。ON as shown in FIG.
After growing the composite structure capacitor dielectric film 8 of O (oxide / nitride / oxide) or NO (nitride / oxide), a first charge storage electrode 9 is formed on the dielectric film 8 with polysilicon. , An oxide film 10 for interlayer insulation is deposited. And
A pattern of the photosensitive film 11 for exposing the surface of the semiconductor substrate 1 where the plate electrode 6 is not formed is formed.
【0024】次いで、図4に示す通り、図3のマスクパ
ターンの現像後に酸化膜10を選択エッチしてポリシリ
コン膜を所定の寸法に蒸着する。そして、ポリシリコン
膜を薄膜MOSFETの基板として利用するために再結
晶(または熱処理)工程を施して、再結晶化されたポリ
シリコン基板12を作り不純物注入工程を行った後に薄
膜MOSFETのゲート酸化膜13を成長させ、所定の
寸法のゲート電極14よびワード線15用ポリシリコン
を蒸着し、不純物注入工程を行った後、所定の寸法でパ
ターンを形成し、薄膜MOSFET活性領域16を作る
ために高濃度イオン注入および熱的工程を施す。このと
き、形成されるFETはLDD構造を有する。Next, as shown in FIG. 4, after the mask pattern of FIG. 3 is developed, the oxide film 10 is selectively etched to deposit a polysilicon film in a predetermined size. Then, a recrystallization (or heat treatment) process is performed to use the polysilicon film as a substrate of the thin film MOSFET, a recrystallized polysilicon substrate 12 is formed, and an impurity implantation process is performed. 13 is grown, a gate electrode 14 of a predetermined size and polysilicon for a word line 15 are vapor-deposited, an impurity implantation process is performed, and then a pattern is formed with a predetermined size to form a thin film MOSFET active region 16. Concentrated ion implantation and thermal steps are performed. At this time, the formed FET has an LDD structure.
【0025】図5の通り、素子の絶縁のために一定の厚
さの第3酸化膜17を蒸着した後、選択エッチして、第
1の電荷貯蔵電極9と薄膜MOSFET活性領域16を
同時に接続する不純物がドーピングされたポリシリコン
膜を蒸着して第2の電荷貯蔵電極18を形成する。この
とき、図3において用いた第1の電荷貯蔵電極9のマス
クと同一のマスクでエッチング工程を施して、第2の電
荷貯蔵電極18を形成する。As shown in FIG. 5, a third oxide film 17 having a constant thickness is vapor-deposited to insulate the device and then selectively etched to simultaneously connect the first charge storage electrode 9 and the thin film MOSFET active region 16. A second charge storage electrode 18 is formed by depositing a polysilicon film doped with impurities. At this time, the second charge storage electrode 18 is formed by performing an etching process with the same mask as the mask of the first charge storage electrode 9 used in FIG.
【0026】最後に、図6に示す通り、第2の電荷貯蔵
電極18形成後に、ONOまたはNOの誘電膜19を第
2の電荷貯蔵電極18に蒸着し、誘電膜19上に不純物
イオン注入されたポリシリコンを蒸着して、所定の寸法
をもつプレート電極20を形成する。そして、ビット線
との絶縁のためにBPSG膜21を蒸着した後、薄膜M
OSFET活性領域16とビット線を接続させるために
BPSG膜21,酸化膜17を順次にエッチし、不純物
イオン注入されたポリシリコン膜を蒸着してビット線2
2コンタクトを活性領域16に形成する。このとき、ビ
ット線22は上述したポリシリコンの不純物注入後にシ
リサイドを追加蒸着してポリサイドを形成することもで
きる。Finally, as shown in FIG. 6, after forming the second charge storage electrode 18, an ONO or NO dielectric film 19 is vapor-deposited on the second charge storage electrode 18, and impurity ions are implanted on the dielectric film 19. Polysilicon is vapor-deposited to form a plate electrode 20 having a predetermined size. Then, after depositing a BPSG film 21 for insulation from the bit line, a thin film M
In order to connect the OSFET active region 16 and the bit line, the BPSG film 21 and the oxide film 17 are sequentially etched, and the impurity ion-implanted polysilicon film is evaporated to form the bit line 2.
Two contacts are formed in the active region 16. At this time, the bit line 22 may be formed with polycide by additionally depositing silicide after the above-described impurity implantation of polysilicon.
【0027】以上説明したように、本発明は、周辺回路
にのみ半導体基板MOSFET移動トランスファーゲー
トを採用し、セルでは半導体基板表面とフィールド酸化
膜の段差で生じた面積を第1次有効キャパシタ面積とし
て使用してセル当り電荷貯蔵容量を増加させ、これをさ
らに電荷貯蔵コンタクトホールを利用して電荷貯蔵電極
と薄膜MOSFETの活性領域を電荷貯蔵電極と同時に
接続させて第2次有効キャパシタ面積でキャパシタ容量
を増加させることができる。さらに、基板コンタクトホ
ールを使用して半導体基板と薄膜MOSFETの基板を
接続させて薄膜構造MOSFETの電気的特性を制御す
ることができる。As described above, the present invention employs the semiconductor substrate MOSFET transfer gate only in the peripheral circuit, and in the cell, the area generated by the step between the semiconductor substrate surface and the field oxide film is taken as the primary effective capacitor area. The charge storage capacity per cell is increased by using the charge storage contact hole to connect the charge storage electrode and the active area of the thin film MOSFET at the same time as the charge storage electrode to obtain the capacitor capacity in the secondary effective capacitor area. Can be increased. Further, the substrate contact hole can be used to connect the semiconductor substrate and the substrate of the thin film MOSFET to control the electrical characteristics of the thin film structure MOSFET.
【0028】従って、上述した本発明の一実施例のDR
AMセルを製造する場合、既存のセル構造より増大され
たキャパシタ有効面積を確保できるので高集積によって
セル面積が減少しても、より大きいセル電荷貯蔵容量を
確保することができ、工程の難易度の面からみても高集
積半導体製作工程に最も障害要因になるフォトマスクと
エッチング工程において既存の設備や技術によっても充
分に製作が可能である。Therefore, the DR of one embodiment of the present invention described above.
In the case of manufacturing an AM cell, an increased capacitor effective area can be secured as compared with the existing cell structure, so that even if the cell area is reduced due to high integration, a larger cell charge storage capacity can be secured, and the process difficulty level is increased. From the viewpoint of the above, the photomask and the etching process, which are the most disturbing factors in the highly integrated semiconductor manufacturing process, can be sufficiently manufactured by the existing equipment and technology.
【0029】図7に本発明による製造方法の他の実施例
を示す。この実施例は上記図2〜図6に示した実施例に
おける図3の酸化膜10を厚く形成して平坦化工程を実
施する場合である。それ以外の全ての工程は先に示した
実施例と同一である。FIG. 7 shows another embodiment of the manufacturing method according to the present invention. In this embodiment, the oxide film 10 of FIG. 3 in the embodiment shown in FIGS. 2 to 6 is thickly formed and the flattening process is performed. All other steps are the same as in the previously described embodiment.
【0030】従って、図7に示した実施例のDRAM製
造方法においては、電荷貯蔵容量確保と共に薄膜MOS
FETのトランスファーゲート活性領域の屈曲に因り電
気的に生じ得る寄生変数を最小化させる効果がある。Therefore, in the DRAM manufacturing method of the embodiment shown in FIG. 7, the thin film MOS is formed while ensuring the charge storage capacity.
This has the effect of minimizing the parasitic variables that can be electrically generated due to the bending of the transfer gate active region of the FET.
【0031】[0031]
【発明の効果】以上説明したように、本発明によれば、
高集積によってセル面積が減少しても、容易な製造工程
によってセルのキャパシタ容量を増加させることができ
る。As described above, according to the present invention,
Even if the cell area is reduced due to high integration, the capacitance of the cell can be increased by a simple manufacturing process.
【図1】本発明による一実施例のDRAMの構造を示す
断面図である。FIG. 1 is a sectional view showing the structure of a DRAM according to an embodiment of the present invention.
【図2】本発明による一実施例のDRAM製造工程を示
す断面図である。FIG. 2 is a cross-sectional view showing a DRAM manufacturing process of an embodiment according to the present invention.
【図3】本発明による一実施例のDRAM製造工程を示
す断面図である。FIG. 3 is a cross-sectional view showing a DRAM manufacturing process of one embodiment according to the present invention.
【図4】本発明による一実施例のDRAM製造工程を示
す断面図である。FIG. 4 is a cross-sectional view showing a DRAM manufacturing process of an embodiment according to the present invention.
【図5】本発明による一実施例のDRAM製造工程を示
す断面図である。FIG. 5 is a cross-sectional view showing a DRAM manufacturing process of an example according to the present invention.
【図6】本発明による一実施例のDRAM製造工程を示
す断面図である。FIG. 6 is a cross-sectional view showing a process of manufacturing a DRAM according to an embodiment of the present invention.
【図7】本発明による他の実施例の工程の一部を示す断
面図である。FIG. 7 is a cross-sectional view showing a part of the process of another embodiment according to the present invention.
1 半導体基板 2 フィールド酸化膜 3,13 ゲート酸化膜 4,10,17 酸化膜 5,14 ゲート電極 6,20 プレート電極 7,16 活性領域 8,19 誘電膜 9 電荷貯蔵電極 11 感光膜 12 ポリシリコン基板 15 ワード線 21 BPSG膜 22 ビット線 1 Semiconductor Substrate 2 Field Oxide Film 3,13 Gate Oxide Film 4,10,17 Oxide Film 5,14 Gate Electrode 6,20 Plate Electrode 7,16 Active Area 8,19 Dielectric Film 9 Charge Storage Electrode 11 Photosensitive Film 12 Polysilicon Substrate 15 Word line 21 BPSG film 22 Bit line
Claims (7)
る半導体記憶装置において、 半導体基板1;前記半導体基板1上に一定間隔で形成さ
れたフィールド酸化膜2とキャパシタが形成される前記
半導体基板1上に形成された第1絶縁膜4;前記第1絶
縁膜4上に形成され、かつ多数のフィールド酸化膜2に
亘って形成された第1プレート電極6;前記第1プレー
ト電極6上に形成された第1誘電膜8;前記第1誘電膜
8上に形成され、かつ隣接した二つのフィールド酸化膜
に亘って形成された第1電荷貯蔵電極9;前記第1電荷
貯蔵電極9および第1プレート電極6を覆う第2絶縁膜
10;前記フィールド酸化膜2および第2プレート電極
4が形成されていない半導体基板1の所定部位にコンタ
クトを成し、前記第2絶縁膜10上部の一定部位に亘っ
て形成されたポリシリコン基板12;前記ポリシリコン
基板12に形成されたゲート絶縁膜13,ゲート電極1
4および活性領域16;前記ゲート電極14,ワード線
15および活性領域16を覆う第3絶縁膜17;前記第
3絶縁膜17を覆い前記第1電荷貯蔵電極9と接続し、
かつ前記活性領域16に接続された第2電荷貯蔵電極1
8;前記第2電荷貯蔵電極18上に蒸着された第2誘電
膜19;前記第2誘電膜19上に形成され、かつ別のワ
ードラインの形成部位上部まで拡張された第2プレート
電極20;前記第2プレート電極20を覆う第4絶縁膜
21;および前記活性領域16にコンタクトされて前記
第4絶縁膜21上に形成されたビットライン22を具備
したことを特徴とする半導体記憶装置。1. A semiconductor memory device having a capacitor formed in a unit cell, comprising: a semiconductor substrate 1; a field oxide film 2 formed on the semiconductor substrate 1 at regular intervals, and a capacitor formed on the semiconductor substrate 1. A first insulating film 4 formed on the first insulating film 4; a first plate electrode 6 formed on the first insulating film 4 and formed over a large number of field oxide films 2; formed on the first plate electrode 6. A first dielectric film 8; a first charge storage electrode 9 formed on the first dielectric film 8 and extending over two adjacent field oxide films; the first charge storage electrode 9 and a first plate A second insulating film 10 covering the electrode 6; a contact is made with a predetermined portion of the semiconductor substrate 1 on which the field oxide film 2 and the second plate electrode 4 are not formed, and a predetermined upper portion of the second insulating film 10 is formed. Position polysilicon is formed over the substrate 12; the polysilicon substrate 12 which is formed on the gate insulating film 13, the gate electrode 1
4 and active region 16; third insulating film 17 covering the gate electrode 14, word line 15 and active region 16; covering the third insulating film 17 and connecting to the first charge storage electrode 9;
And a second charge storage electrode 1 connected to the active region 16
8; a second dielectric film 19 deposited on the second charge storage electrode 18; a second plate electrode 20 formed on the second dielectric film 19 and extended to an upper portion of another word line formation region; A semiconductor memory device comprising: a fourth insulating film (21) covering the second plate electrode (20); and a bit line (22) formed on the fourth insulating film (21) in contact with the active region (16).
る半導体記憶装置の製造方法において、 半導体基板1にフィールド酸化膜2を形成し、第1絶縁
膜4を薄く形成し、第1プレート電極6を形成し、前記
第1プレート電極6上に第1誘電膜8を形成する工程
と;前記第1誘電膜8上に第1電荷貯蔵電極9を形成し
た後、第2絶縁膜10を形成する工程と;前記フィール
ド酸化膜2が形成されていない所定部位の前記半導体基
板1を露出させ、ポリシリコン膜を前記第1電荷貯蔵電
極9上に形成されている第2絶縁膜10上に亘って形成
してポリシリコン基板12を形成する工程と、;前記ポ
リシリコン基板12に活性領域16,ゲート絶縁膜13
およびゲート電極14を有するFETを形成し、かつポ
リシリコン基板12に形成される前記ゲート電極13と
前記第2絶縁膜10上に形成されるワード線15を同時
に形成する工程と;全体構造上部に第3酸化膜17を形
成し、前記第1電荷貯蔵電極9上に接続される第2電荷
貯蔵電極18を前記活性領域16と接続するよう形成す
る工程と;第2誘電膜19を前記第2電荷貯蔵電極18
上に形成し、次いで前記第2誘電膜19上にプレート電
極20を形成する工程と;全体構造上部に第4絶縁膜2
1を形成し、前記活性領域16とビット線22をコンタ
クトさせる工程を有することを特徴とする半導体記憶装
置の製造方法。2. A method of manufacturing a semiconductor memory device having a capacitor formed in a unit cell, wherein a field oxide film 2 is formed on a semiconductor substrate 1, a first insulating film 4 is formed thin, and a first plate electrode 6 is formed. And forming a first dielectric film 8 on the first plate electrode 6; forming a first charge storage electrode 9 on the first dielectric film 8 and then forming a second insulating film 10. And; exposing the semiconductor substrate 1 at a predetermined portion where the field oxide film 2 is not formed, and forming a polysilicon film over the second insulating film 10 formed on the first charge storage electrode 9. To form the polysilicon substrate 12, the active region 16 and the gate insulating film 13 are formed on the polysilicon substrate 12.
And forming a FET having a gate electrode 14 and simultaneously forming the gate electrode 13 formed on the polysilicon substrate 12 and the word line 15 formed on the second insulating film 10; Forming a third oxide film 17 and forming a second charge storage electrode 18 on the first charge storage electrode 9 to connect to the active region 16; and forming a second dielectric film 19 on the second charge storage electrode 18. Charge storage electrode 18
Forming a plate electrode 20 on the second dielectric film 19, and forming a plate electrode 20 on the second dielectric film 19;
1. A method of manufacturing a semiconductor memory device, comprising the step of forming 1 and contacting the active region 16 with the bit line 22.
形成されることを特徴とする請求項2に記載の半導体記
憶装置の製造方法。3. The method for manufacturing a semiconductor memory device according to claim 2, wherein the active region 16 is formed by an LDD process.
化物・酸化物または窒化物・酸化物膜複合構造のうちい
ずれか一つであることを特徴とする請求項2に記載の半
導体記憶装置の製造方法。4. The first and second dielectric films have one of an oxide / nitride / oxide or a nitride / oxide film composite structure. Manufacturing method of semiconductor memory device.
に、該第2絶縁膜を厚い厚膜で形成し平坦化する工程を
さらに含むことを特徴とする請求項2に記載の半導体記
憶装置の製造方法。5. The semiconductor memory according to claim 2, further comprising the step of forming the second insulating film with a thick film and planarizing the second insulating film to planarize the second insulating film. Device manufacturing method.
貯蔵電極18のパターン形成マスクが同一であることを
特徴とする請求項2に記載の半導体記憶装置の製造方
法。6. The method of manufacturing a semiconductor memory device according to claim 2, wherein the pattern forming masks of the first charge storage electrode 9 and the second charge storage electrode 18 are the same.
物を注入した後にシリサイドを蒸着してポリシリサイド
を形成する工程をさらに含むことを特徴とする請求項2
に記載の半導体記憶装置の製造方法。7. The bit line 22 further comprises a step of depositing an impurity into polysilicon and then depositing silicide to form polysilicide.
A method for manufacturing a semiconductor memory device according to claim 1.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1992-12085 | 1992-07-07 | ||
KR1019920012085A KR960013508B1 (en) | 1992-07-07 | 1992-07-07 | Semiconductor device having thin film transistor & method of manufacturing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH06188383A true JPH06188383A (en) | 1994-07-08 |
JPH0828479B2 JPH0828479B2 (en) | 1996-03-21 |
Family
ID=19335979
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5166751A Expired - Fee Related JPH0828479B2 (en) | 1992-07-07 | 1993-07-06 | Semiconductor memory device and manufacturing method thereof |
Country Status (3)
Country | Link |
---|---|
US (1) | US5296402A (en) |
JP (1) | JPH0828479B2 (en) |
KR (1) | KR960013508B1 (en) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2796249B2 (en) * | 1993-07-02 | 1998-09-10 | 現代電子産業株式会社 | Method for manufacturing semiconductor memory device |
KR0124393B1 (en) * | 1994-03-18 | 1997-12-11 | 김주용 | Capacitor manufacturing method |
JP3802942B2 (en) * | 1994-09-01 | 2006-08-02 | 株式会社ルネサステクノロジ | Semiconductor device, semiconductor memory device, and method of manufacturing semiconductor memory device |
US5696405A (en) * | 1995-10-13 | 1997-12-09 | Lucent Technologies Inc. | Microelectronic package with device cooling |
JP3402029B2 (en) * | 1995-11-30 | 2003-04-28 | 三菱電機株式会社 | Method for manufacturing semiconductor device |
US5895962A (en) * | 1996-06-13 | 1999-04-20 | Micron Technology, Inc. | Structure and a method for storing information in a semiconductor device |
US6194738B1 (en) | 1996-06-13 | 2001-02-27 | Micron Technology, Inc. | Method and apparatus for storage of test results within an integrated circuit |
US6100486A (en) | 1998-08-13 | 2000-08-08 | Micron Technology, Inc. | Method for sorting integrated circuit devices |
US5927512A (en) * | 1997-01-17 | 1999-07-27 | Micron Technology, Inc. | Method for sorting integrated circuit devices |
US5844803A (en) * | 1997-02-17 | 1998-12-01 | Micron Technology, Inc. | Method of sorting a group of integrated circuit devices for those devices requiring special testing |
US5915231A (en) | 1997-02-26 | 1999-06-22 | Micron Technology, Inc. | Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC's mis-processed during their manufacture |
US5856923A (en) | 1997-03-24 | 1999-01-05 | Micron Technology, Inc. | Method for continuous, non lot-based integrated circuit manufacturing |
US7120513B1 (en) * | 1997-06-06 | 2006-10-10 | Micron Technology, Inc. | Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergone, such as repairs, to select procedures the ICS will undergo, such as additional repairs |
US5907492A (en) * | 1997-06-06 | 1999-05-25 | Micron Technology, Inc. | Method for using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's will undergo, such as additional repairs |
US6049624A (en) | 1998-02-20 | 2000-04-11 | Micron Technology, Inc. | Non-lot based method for assembling integrated circuit devices |
US5858831A (en) * | 1998-02-27 | 1999-01-12 | Vanguard International Semiconductor Corporation | Process for fabricating a high performance logic and embedded dram devices on a single semiconductor chip |
US6829737B1 (en) * | 2000-08-30 | 2004-12-07 | Micron Technology, Inc. | Method and system for storing device test information on a semiconductor device using on-device logic for determination of test results |
US6943575B2 (en) * | 2002-07-29 | 2005-09-13 | Micron Technology, Inc. | Method, circuit and system for determining burn-in reliability from wafer level burn-in |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5219781A (en) * | 1988-12-08 | 1993-06-15 | Mitsubishi Denki Kabushiki Kaisha | Method for manufacturing semiconductor memory device having a stacked type capacitor |
US5006481A (en) * | 1989-11-30 | 1991-04-09 | Sgs-Thomson Microelectronics, Inc. | Method of making a stacked capacitor DRAM cell |
US5104822A (en) * | 1990-07-30 | 1992-04-14 | Ramtron Corporation | Method for creating self-aligned, non-patterned contact areas and stacked capacitors using the method |
KR920003461A (en) * | 1990-07-30 | 1992-02-29 | 김광호 | Method for forming contact region and manufacturing method of semiconductor device using same |
US5057888A (en) * | 1991-01-28 | 1991-10-15 | Micron Technology, Inc. | Double DRAM cell |
-
1992
- 1992-07-07 KR KR1019920012085A patent/KR960013508B1/en not_active IP Right Cessation
-
1993
- 1993-07-06 US US08/088,188 patent/US5296402A/en not_active Expired - Lifetime
- 1993-07-06 JP JP5166751A patent/JPH0828479B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR960013508B1 (en) | 1996-10-05 |
US5296402A (en) | 1994-03-22 |
JPH0828479B2 (en) | 1996-03-21 |
KR940003021A (en) | 1994-02-19 |
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