JPH0618601A - Fault-point orienting apparatus - Google Patents

Fault-point orienting apparatus

Info

Publication number
JPH0618601A
JPH0618601A JP20050692A JP20050692A JPH0618601A JP H0618601 A JPH0618601 A JP H0618601A JP 20050692 A JP20050692 A JP 20050692A JP 20050692 A JP20050692 A JP 20050692A JP H0618601 A JPH0618601 A JP H0618601A
Authority
JP
Japan
Prior art keywords
terminal
current
fault
voltage
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20050692A
Other languages
Japanese (ja)
Other versions
JP3183957B2 (en
Inventor
Hiroshi Shimonaga
弘 下永
Ryoichi Matsunaga
良一 松永
Yasuhiro Kurosawa
保広 黒沢
Shigenori Mizuguchi
重則 水口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Kyushu Electric Power Co Inc
Original Assignee
Toshiba Corp
Kyushu Electric Power Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Kyushu Electric Power Co Inc filed Critical Toshiba Corp
Priority to JP20050692A priority Critical patent/JP3183957B2/en
Publication of JPH0618601A publication Critical patent/JPH0618601A/en
Application granted granted Critical
Publication of JP3183957B2 publication Critical patent/JP3183957B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Locating Faults (AREA)

Abstract

PURPOSE:To obtain the stable and highly accurate orientation by separating an input circuit for synchronous control and an input circuit for operating the point for orienting a fault point, and always obtaining the orientation input under the synchronized state. CONSTITUTION:A current testing plug 1A and a voltage testing plug 2A, which are provided for the current transformer and the transformer at a terminal A, are separated from the secondary side with the primary sides being shorted or released in the test. The current, which is inputted from the plug 1A, is converted into the digital quantities in an A/D converter circuit 5A through an input converting circuits 2A1 and 3A2. The voltage, which is inputted from the plug 2A, is converted into the digital quantities in the A/D converter 5A through input converting circuits 4A1 and 4A2. The results are operated in a operating circuit 6A. The results of the operations and the data are sent into the corresponding terminals through an interface 7A. The data of the corresponding terminals are received. A terminal B is constituted as the terminal B, and only the contents of the operations in the operating circuits 6A and 6B are different. The terminal B acquires the data, sends the data into the terminal A, receives the synchronized control amount from the terminal A and performs the control so as to obtain a specified sampling timing. The operation circuit 6A continues the synchronous control operation when there is no fault. When a fault is detected, the operation is switched to a fault-point orienting operation. Thus, the sampling synchronization is continued to the time immediately before the occurrence of fault. Therefore, the stable orientation test can be performed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、送電線の各端子の電
圧,電流を収集して故障点を標定する故障点標定装置に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault point locating device for locating a fault point by collecting voltage and current at each terminal of a transmission line.

【0002】[0002]

【従来の技術】従来、送電線の故障点標定方式としては
サージ受信方式,パルスレーダ測定方式あるいはインピ
ーダンス測定方式等がある。前二者は高価な通信装置を
必要とする。これに対して後者のインピーダンス測定方
式は変成器及び変流器より得られる電圧,電流により直
接標定するものであるため、入力量を得るために新たな
設備を必要としない。しかし、故障点抵抗がある場合、
故障点には自端子の電流のみでなく相手端子からも流れ
込む電流があるため、必ずしも双方の電流位相角が同相
になることはなく、測距誤差を生じる要因になり得る。
このため送電線の全端子の電圧,電流を取り込み、キル
ヒホッフの法則を使って故障点抵抗の影響を受けない標
定方式が注目されており、例えば特公昭57−5026
2号が提案されている。
2. Description of the Related Art Conventionally, there are a surge receiving method, a pulse radar measuring method, an impedance measuring method, etc. as a fault point locating method for a transmission line. The former two require expensive communication equipment. On the other hand, the latter impedance measurement method does not require new equipment to obtain the input amount because it directly measures the voltage and current obtained from the transformer and the current transformer. However, if there is a fault resistance,
Since there is not only the current of its own terminal but also the current flowing from the other terminal at the failure point, the current phase angles of both do not necessarily become the same phase, which may cause a distance measurement error.
For this reason, the orientation method that takes in the voltage and current of all terminals of the transmission line and is not affected by the resistance of the fault point by using Kirchhoff's law is drawing attention, for example, Japanese Examined Patent Publication No. 57-5026.
No. 2 is proposed.

【0003】[0003]

【発明が解決しようとする課題】上記した従来方式は、
途中に事故が無い時は分岐点の電圧が等しいこと、及び
同送電線の分岐点につながる全端子の電圧,電流は同期
がとれていることを利用して、各端子の電圧,電流を同
時にサンプリングするよう制御することを前提としてい
る。従って常時の事故が無い状態での分岐点電圧の算出
精度は、かなり高いレベルが要求されることは明らかで
ある。そのためには故障点標定装置の電流入力のフルス
ケールは当該送電線の負荷電流レベルを想定しておく必
要がある。しかし当該送電線に事故が発生した場合には
当然負荷電流を越える事故電流が流れ、そのまま故障点
標定演算に使用すると大きな誤差を生じることになる。
更に、故障点標定用と前記同期制御用の電流入力を共用
すると、各端子のサンプリング同期をとるには、同期の
とれた送電線の電圧,電流を入力しておく必要があり、
現場等で試験を行なう時に外部から試験電気量を入れる
ことが非常に難しい。即ち、非同期の入力が各端子に入
力されて同期が外れてしまうことになる。だからといっ
て試験をしない訳にはいかない。本発明は上記事情に鑑
みてなされたものであり、同期のとれた系統の電気量を
用いて各端子の電気量を同時にサンプリングするように
制御する故障点標定装置において、大きな事故電流が流
れても標定精度を確保でき、かつ安定にサンプリング同
期をとりながら標定試験の可能な故障点標定装置を提供
することを目的としている。
The above-mentioned conventional method is
When there is no accident on the way, the voltage at each branch point is the same, and the voltage and current at all terminals connected to the branch point of the same transmission line are synchronized. It is premised on controlling to sample. Therefore, it is clear that the calculation accuracy of the branch point voltage in the state where there is no accident at all times requires a considerably high level. For that purpose, the full scale of the current input of the fault locator must assume the load current level of the transmission line. However, if an accident occurs in the power transmission line, a fault current that exceeds the load current naturally flows, and if it is used as it is for the fault location calculation, a large error will occur.
Furthermore, if the current input for fault location and the current input for the synchronous control are shared, it is necessary to input the voltage and current of the synchronized transmission line in order to synchronize the sampling of each terminal.
It is very difficult to input the amount of test electricity from the outside when conducting a test on site. That is, the asynchronous input is input to each terminal and the synchronization is lost. But that doesn't mean that you don't test. The present invention has been made in view of the above circumstances, in a fault point locating device that controls to simultaneously sample the electrical quantities of the terminals using the electrical quantities of the synchronized system, a large fault current flows. Also aims to provide a fault point locator capable of securing orientation accuracy and capable of orientation test with stable sampling synchronization.

【0004】[0004]

【課題を解決するための手段】上記目的を達成するた
め、本発明は送電線の複数の端子の電圧,電流を収集
し、各端子から分岐点迄の電圧降下分を算出して、求め
た分岐点電圧が当該区間に故障がなければ等しいことを
利用して、前記分岐点電圧が等しくなるように各端子の
電圧,電流の収集タイミングを自動的に合せるよう構成
した故障点標定装置において、故障点を算出するための
電圧,電流を取り込む第1の手段と、前記電圧,電流の
収集タイミングを制御するための電圧,電流を取り込む
第2の手段と、前記第1の手段にて取り込んだ電圧,電
流にて故障を検出したとき前記第2の手段によるタイミ
ング制御を阻止する第3の手段とから構成した。
In order to achieve the above object, the present invention collects voltages and currents at a plurality of terminals of a transmission line and calculates and calculates a voltage drop from each terminal to a branch point. In the fault point locating device configured to automatically adjust the voltage and current collecting timings of the terminals so that the branch point voltages are equal by utilizing the fact that the branch point voltages are equal if there is no fault in the section, The first means for fetching the voltage and current for calculating the failure point, the second means for fetching the voltage and current for controlling the timing of collecting the voltage and current, and the first means for fetching And a third means for preventing the timing control by the second means when a failure is detected by voltage and current.

【作用】同期制御用の入力回路と故障点標定演算用の入
力回路とを分けるようにしたため、標定精度を高めると
同時に、同期のとれば状態での標定機能の試験入力が得
られ、その結果同期が外れないようになった。
[Function] Since the input circuit for synchronous control and the input circuit for fault point location calculation are separated, it is possible to improve the orientation accuracy and at the same time obtain the test input of the orientation function under the condition of synchronization. I can't get out of sync.

【0005】[0005]

【実施例】以下図面を参照して実施例を説明する。図1
は本発明による故障点標定装置の一実施例の構成図であ
る。図において、1AはA端子の変流器から取り込まれ
る電流用試験プラグで、試験時に1次側を短絡して2次
側と切り離すことができるようにしてある。2AはA端
子の変成器から取り込まれる電圧用試験プラグで、試験
時に1次側を開放し、2次側と切り離せるようにしてあ
る。試験用プラグ1Aを介して入力される電流は入力変
換回路3A1,3A2を介し、又、試験用プラグ2Aを
介して入力される電圧は入力変換回路4A1,4A2を
介して、各々がアナログ−ディジタル変換回路5A(以
後DAUと記す)に入力される。ディジタル量に変換さ
れたデータは演算回路6Aに入力され、所定の演算を実
行する。6Aの演算結果、又、演算途中のデータを通信
インターフェース7Aを介して相手端子に送り、逆に相
手端子のデータを受けるように構成されている。B端子
についても構成は同じで添え字AをBに置き換えればよ
い。但し、6A,6Bの演算回路においては演算内容が
両端子間で異なっている。本発明では同期制御演算,標
定演算処理を司る親端子をA端子として以下説明する。
B端子はデータを取得して、A端子にデータを送り、A
端子からの同期制御量を受けて所定のサンプリングタイ
ミングになるよう制御する構成としている。この点につ
いての基本原理は特開平3−282377号に示されて
いるが、本発明のものには直接関係ないため、詳細につ
いては省略する。
Embodiments will be described below with reference to the drawings. Figure 1
FIG. 1 is a configuration diagram of an embodiment of a fault point locating device according to the present invention. In the figure, 1A is a current test plug taken in from a current transformer having an A terminal, and the primary side can be short-circuited and disconnected from the secondary side during a test. 2A is a voltage test plug taken in from the transformer of the A terminal, and is designed so that the primary side can be opened and disconnected from the secondary side during the test. The current input through the test plug 1A is input through the input conversion circuits 3A1 and 3A2, and the voltage input through the test plug 2A is input through the input conversion circuits 4A1 and 4A2. It is input to the conversion circuit 5A (hereinafter referred to as DAU). The data converted into the digital amount is input to the arithmetic circuit 6A and executes a predetermined arithmetic operation. The calculation result of 6A and the data in the middle of the calculation are sent to the partner terminal via the communication interface 7A, and conversely the data of the partner terminal is received. The configuration of the B terminal is the same, and the subscript A may be replaced with B. However, in the arithmetic circuits 6A and 6B, the arithmetic contents are different between both terminals. In the present invention, the parent terminal which controls the synchronous control calculation and the orientation calculation processing will be described as the A terminal.
The B terminal acquires data, sends the data to the A terminal, and
It is configured to receive the synchronization control amount from the terminal and control so as to reach a predetermined sampling timing. The basic principle of this point is shown in Japanese Patent Laid-Open No. 3-282377, but since it is not directly related to the present invention, its details are omitted.

【0006】図は2端子の例で示しているため、送電線
8の仮想の分岐点Jを中間点として説明する。なお、一
般的には2端子の場合、任意に予め定めた位置に設定し
ておけば目的は達成できる。又、Fは故障点を示し、X
はA端子から故障点までの距離である。IA1,VA1
はA端子の同期制御用入力回路から取り込まれた電流,
電圧である。IA2,VA2は故障点標定用入力回路か
らの電流,電圧である。添え字AはA端子でB端子はB
とする。入力変換回路3A1,3A2(3B1,3B
2)は変流器から、4A1,4A2(4B1,4B2)
は変成器からの出力を適当なレベルに変換し、更に高域
の周波数成分を除去するための前置フィルターを経て出
力を生じる。これは通常用いられている手法であり、特
に内部構成図を掲げない。アナログ−ディジタル変換回
路5A(5B)は入力を一定間隔でサンプリングし、デ
ィジタル出力を演算出力回路6A(6B)へ印加する。
演算出力回路6A(6B)は後に図2による演算を実施
する。なお、ここで入力変換回路3A1,3A2(3B
1,3B2)、4A1,4A2(4B1,4B2)の出
力は、特に混乱のない限り、アナログ−ディジタル変換
回路5A(5B)の出力と同様にIA1,IA2(IB
1,IB2)、VA1,VA2(VB1,VB2)とし
て表すものとする。
Since the figure shows an example of two terminals, the virtual branch point J of the power transmission line 8 will be described as an intermediate point. In general, in the case of two terminals, the purpose can be achieved by arbitrarily setting it at a predetermined position. Also, F indicates a failure point, X
Is the distance from the A terminal to the failure point. IA1, VA1
Is the current fetched from the A terminal synchronous control input circuit,
Voltage. IA2 and VA2 are current and voltage from the fault point locating input circuit. Subscript A is A terminal and B terminal is B
And Input conversion circuits 3A1, 3A2 (3B1, 3B
2) is a current transformer, 4A1, 4A2 (4B1, 4B2)
Converts the output from the transformer to an appropriate level, and outputs the output through a prefilter for removing high frequency components. This is a commonly used method, and no internal block diagram is given. The analog-digital conversion circuit 5A (5B) samples the input at regular intervals and applies the digital output to the operation output circuit 6A (6B).
The operation output circuit 6A (6B) later executes the operation shown in FIG. Here, here, the input conversion circuits 3A1, 3A2 (3B
The outputs of 1, 3B2), 4A1, 4A2 (4B1, 4B2) are the same as those of the analog-digital conversion circuit 5A (5B) unless otherwise confused.
1, IB2) and VA1, VA2 (VB1, VB2).

【0007】図2は図1の演算回路6Aの機能を説明す
るブロック図である。本発明は同期制御用と標定演算用
の入力回路を分離することを骨子とするものである。従
って前記したようにA端子とB端子の演算内容が異なる
が、親端子としたA端子の機能を説明すれば本発明の主
旨は良い尽くせる。基本的な同期制御計算,標定計算に
ついては既知の方式であるので、ここでは簡単に記すに
止める。図2において201は送電線8につながる系統
に故障が発生したか否かを検出する手段である。事故が
発生していない場合は電流IA1,VA1及び通信イン
ターフェース7Aを介してB端子から受信したIB1,
VB1から、J点(送電線の中間点)の分岐点電圧VJ
A,VJBを分岐点算出手段202で下式に基づいて算
出する。 Z:端子AとB間の送電線インピーダンスで整定値とし
て入力されるか予め定数として設定させるものである。
FIG. 2 is a block diagram for explaining the function of the arithmetic circuit 6A shown in FIG. The gist of the present invention is to separate input circuits for synchronous control and for orientation calculation. Therefore, although the calculation contents of the A terminal and the B terminal are different as described above, the gist of the present invention can be fulfilled if the function of the A terminal as the parent terminal is described. Since the basic synchronization control calculation and orientation calculation are known methods, they will be briefly described here. In FIG. 2, 201 is a means for detecting whether or not a failure has occurred in the system connected to the power transmission line 8. If no accident has occurred, the current IA1, VA1 and IB1, received from the B terminal via the communication interface 7A
The branch point voltage VJ from VB1 to the point J (intermediate point of the transmission line)
A and VJB are calculated by the branch point calculation means 202 based on the following formula. Z: The impedance of the transmission line between the terminals A and B, which is input as a set value or is preset as a constant.

【0008】算出された電圧量VJAとVJBはA−B
端子間に故障がなければ理想的には等しくなることは明
らかである。この理想的な状態が成立するとした時、両
者の電圧量が等しくならないのは両端子間のサンプリン
グが同時刻になっていないためである。その差がどの程
度の値かを算出する方式については本発明の主旨でない
ため詳述しないが、概略は下記の通りである。即ち、位
相角算出手段203で下記手順で位相角を求め、通信イ
ンターフェース7Aを介してB端子に相当の量を送出手
段204から送出する。 (A).各端子で付けたサンプリング番号を相互に送っ
て、下記(2) 式で求めた位相角θがサンプリング周期相
当の位相角(2π・交流電気量の基本周波数/サンプリ
ング周波数)になる迄サンプリング番号を合せる。 (B).(A)の後、θ相当の量をB端子に送り、B端
子でθが零になるようにサンプリング時刻を変化させる
ように制御する。故障検出手段201で故障が有りと判
定され、送電線区間に故障が有るか否かを区間内故障判
定手段205にて、標定演算用入力回路から得られた電
流量IA1,IB2を用いて、例えば下記(3) 式に基づ
いて判定する。下式は単に電流差動方式を基本としてい
る。 IA2+IB2≧IK(設定値) …………………(3)
The calculated voltage amounts VJA and VJB are AB
Obviously, if there is no failure between the terminals, they would be ideally equal. When this ideal state is established, the voltage amounts of both terminals are not equal because the sampling between both terminals is not the same time. The method of calculating the value of the difference will not be described in detail because it is not the gist of the present invention, but the outline is as follows. That is, the phase angle calculation means 203 obtains the phase angle by the following procedure, and the corresponding amount is sent from the sending means 204 to the B terminal via the communication interface 7A. (A). Send the sampling numbers assigned to each terminal to each other, and keep the sampling numbers until the phase angle θ obtained by the following equation (2) becomes the phase angle corresponding to the sampling cycle (2π / basic frequency of AC electricity / sampling frequency). Can match. (B). After (A), an amount equivalent to θ is sent to the B terminal, and the sampling time is controlled so that θ becomes zero at the B terminal. The failure detection unit 201 determines that there is a failure, and the intra-section failure determination unit 205 determines whether or not there is a failure in the transmission line section by using the current amounts IA1 and IB2 obtained from the orientation calculation input circuit. For example, the judgment is made based on the following formula (3). The following formula is simply based on the current differential method. IA2 + IB2 ≧ IK (setting value) …………………… (3)

【0009】(3) 式を満足した場合は送電線区間に事故
有りと判定し、標定値算出手段206にて下記(4) 式に
基づいて標定値X(A端子からの距離)を算出する。 *:共役複素数 Im:虚数部を表す Z:送電線の単位長当たりのインピーダンス なお、同上式は基本原理式を記述しているが、短絡故
障,一線地絡故障の場合には上記の電気量は各々使い分
けねばならない。これらの諸量については本発明の趣旨
を説明する上では必ずしも必要はなく、特公昭58−2
9471号公報に詳述されている。以上説明した通り、
一旦故障を検出したら同期制御が停止されるが、高々電
力系統の故障継続時間は低位系統では1〜2分程度であ
り(超高圧系統では数秒オーダ)、現状の水晶発振器の
精度(10-6)からして、60〜120μs程度のズレ
しか生じない。従って本発明では故障復帰時に一定の保
護時間を設けて、同期制御を開始しても実用上全く問題
がないことを前提としている。図3に故障発生前後の電
流,電圧波形の例を示す。入力変換回路のダイナミック
レンジが大きくオーバーしない場合と、小さくてオーバ
ーして飽和した場合の波形を示す。波形を見て分かるよ
うに、その分電流は小さく見られ標定誤差となって生じ
る。従って故障検出後ダイナミックレンジの広い電気量
(IA2,IB2及びVA2,VB2)を使用すれば本
問題は解決できることは明らかであり、この点が本発明
の骨子である。
When the equation (3) is satisfied, it is determined that there is an accident in the transmission line section, and the orientation value calculating means 206 calculates the orientation value X (distance from the A terminal) based on the following equation (4). . *: Conjugate complex number Im: Represents imaginary part Z: Impedance per unit length of transmission line Although the above formula describes the basic principle formula, in the case of short-circuit fault and one-line ground fault, the above-mentioned electric quantity Must be used properly. These various amounts are not always necessary for explaining the gist of the present invention, and are described in JP-B-58-2.
This is described in detail in Japanese Patent No. 9471. As explained above,
Once a failure is detected, the synchronous control is stopped, but the failure duration of the power system is at most 1-2 minutes in the low-order system (on the order of several seconds in the ultrahigh-voltage system), and the accuracy of the current crystal oscillator (10 -6 Therefore, only a deviation of about 60 to 120 μs occurs. Therefore, in the present invention, it is premised that there is no problem in practice even if the synchronous control is started by providing a certain protection time at the time of failure recovery. Figure 3 shows examples of current and voltage waveforms before and after a failure. The waveforms are shown when the dynamic range of the input conversion circuit does not greatly exceed and when it is small and exceeds the saturated range. As can be seen from the waveform, the current is seen to be small by that amount, which causes a localization error. Therefore, it is clear that this problem can be solved by using the electric quantities (IA2, IB2 and VA2, VB2) having a wide dynamic range after the failure detection, and this point is the essence of the present invention.

【0010】図4は本発明の他の実施例の構成図であ
る。図において、1A1,1A2は各々A端子の変流器
から取り込まれる電流用試験プラグで、試験時に1次側
を短絡して2次側と切り離すことができるようにしてあ
る。前者の試験プラグは同期制御用、後者は故障点標定
用である。又、2A1,2A2は各々A端子の変成器か
ら取り込まれる電圧用試験プラグで試験時に1次側を開
放し、2次側と切り離せるようにしてある。試験プラグ
1A1,1A2を介して入力される電流は入力変換回路
3A1,3A2を介し、試験プラグ2A1,2A2を介
して入力される電圧は入力変換回路4A1,4A2を経
てアナログ−ディジタル変換回路5Aに入力される。試
験時には第2の手段の試験プラグ1A2,2A2によっ
て、試験用電流源9A、試験用電圧源10Aに切り換え
て所望の電流,電圧を入力する。第2の手段により試験
電気量を印加して、図2に示すように故障を発生し検出
する直前迄、第1の手段により同期制御用の送電線8か
ら入力されている電気量(IA1,VA1,IB1,V
B1)を使用し、検出した後は前記電気量を使用しな
い、即ち、同期制御を行なわないようにするものであ
る。図5に試験電気量印加前後の同期制御用入力回路の
電気量(IA1,VA1)と標定用入力回路の電気量
(IA2,VA2)及び同期制御信号を示す。同図にお
いてt=toの時点で故障発生用の試験用電気量が試験
プラグ1A2,2A2(1B2,2B2)に印加された
ものとして示す。同図を見て分かるように同期制御信号
は試験電気量が印加される迄“1”で同期制御を実施し
ている。
FIG. 4 is a block diagram of another embodiment of the present invention. In the figure, 1A1 and 1A2 are current test plugs respectively taken from the current transformer of the A terminal, and the primary side can be short-circuited and disconnected from the secondary side during the test. The former test plug is for synchronous control, and the latter is for fault location. Further, 2A1 and 2A2 are voltage test plugs respectively taken in from the transformer of the A terminal so that the primary side can be opened and the secondary side can be disconnected during the test. The current input via the test plugs 1A1 and 1A2 is input to the analog-digital conversion circuit 5A via the input conversion circuits 3A1 and 3A2, and the voltage input via the test plugs 2A1 and 2A2 is input to the analog-digital conversion circuit 5A via the input conversion circuits 4A1 and 4A2. Is entered. During the test, the test current sources 9A and 10A are switched by the test plugs 1A2 and 2A2 of the second means to input the desired current and voltage. The test quantity of electricity is applied by the second means, and immediately before the failure is generated and detected as shown in FIG. 2, the quantity of electricity (IA1, VA1, IB1, V
B1) is used, and after the detection, the electric quantity is not used, that is, the synchronous control is not performed. FIG. 5 shows the electric quantities (IA1, VA1) of the synchronization control input circuit before and after the application of the test electric quantity, the electric quantities (IA2, VA2) of the orientation input circuit, and the synchronization control signal. In the same figure, it is shown that a test electricity quantity for failure occurrence is applied to the test plugs 1A2, 2A2 (1B2, 2B2) at time t = to. As can be seen from the figure, the synchronization control signal is "1" to perform the synchronization control until the test electric quantity is applied.

【0011】[0011]

【発明の効果】以上説明したように、本発明によれば同
期制御用の入力回路と故障点標定演算用の入力回路を分
けるよう構成したので、下記の点を解決することができ
る。即ち、同期制御用の入力回路用試験プラグは送電線
の変流器,変成器に接続した状態で故障点標定演算用の
電流試験用プラグ1A2、電圧試験用2A2に試験電源
を接続することにより、故障を発生させる直前迄、同期
制御用入力を介して送電線の電気量が故障点標定装置に
入力され、サンプリング同期を行なうことができる。そ
の結果、安定した故障点標定試験が実施可能となる。
As described above, according to the present invention, the input circuit for the synchronous control and the input circuit for the fault point locating operation are configured separately, so that the following points can be solved. That is, by connecting the test plug for the input circuit for synchronous control to the current transformer and transformer of the transmission line, by connecting the test power source to the current test plug 1A2 and the voltage test 2A2 for fault location calculation, Until just before a failure occurs, the electric quantity of the power transmission line is input to the failure point locating device via the synchronization control input, and sampling synchronization can be performed. As a result, a stable fault location test can be carried out.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による故障点標定装置の一実施例の構成
図。
FIG. 1 is a configuration diagram of an embodiment of a fault point locating device according to the present invention.

【図2】図1に示す演算回路の機能を示すブロック図。FIG. 2 is a block diagram showing functions of the arithmetic circuit shown in FIG.

【図3】故障発生前後の電流,電圧波形図。FIG. 3 is a current and voltage waveform diagram before and after a failure occurs.

【図4】故障点標定装置の他の実施例の構成図。FIG. 4 is a configuration diagram of another embodiment of the fault location device.

【図5】本発明の効果を説明する図。FIG. 5 is a diagram for explaining the effect of the present invention.

【符号の説明】[Explanation of symbols]

1A,1A1,1A2 電流量試験プラグ 2A,2A1,2A2 電圧用試験プラグ 3A,3A1,3A2 電流用入力変換回路 4A,4A1,4A2 電圧用入力変換回路 5A アナログ−ディジタル変換回路 6A 演算回路 7A 通信インターフェース 8 送電線 1A, 1A1, 1A2 Current amount test plug 2A, 2A1, 2A2 Voltage test plug 3A, 3A1, 3A2 Current input conversion circuit 4A, 4A1, 4A2 Voltage input conversion circuit 5A Analog-digital conversion circuit 6A Arithmetic circuit 7A Communication interface 8 power lines

───────────────────────────────────────────────────── フロントページの続き (72)発明者 黒沢 保広 東京都府中市東芝町1番地 株式会社東芝 府中工場内 (72)発明者 水口 重則 東京都府中市東芝町1番地 株式会社東芝 府中工場内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhiro Kurosawa No. 1 in Toshiba Fuchu factory, Fuchu, Tokyo (72) Inventor Shigenori Mizuguchi No. 1 in Toshiba Town, Fuchu, Tokyo Toshiba Fuchu factory, Ltd.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 送電線の複数の端子の電圧,電流を収集
し、各端子から分岐点迄の電圧降下分を算出して、求め
た分岐点電圧が当該区間に故障がなければ等しいことを
利用して、前記分岐点電圧が等しくなるように各端子の
電圧,電流の収集タイミングを自動的に合せるよう構成
した故障点標定装置において、故障点を算出するための
電圧,電流を取り込む第1の手段と、前記電圧,電流の
収集タイミングを制御するための電圧,電流を取り込む
第2の手段と、前記第1の手段にて取り込んだ電圧,電
流にて故障を検出したとき前記第2の手段によるタイミ
ング制御を阻止する第3の手段とからなることを特徴と
する故障点標定装置。
1. The voltage and current of a plurality of terminals of a transmission line are collected, the voltage drop from each terminal to a branch point is calculated, and the obtained branch point voltage is equal if there is no failure in the section. A fault point locating device configured to automatically adjust the voltage and current collection timings of the terminals so that the branch point voltages are equalized by using the voltage and current for calculating a fault point. Means, second means for taking in voltage and current for controlling the timing of collecting the voltage and current, and second means for detecting a failure by the voltage and current taken in by the first means. And a third means for preventing the timing control by the means.
JP20050692A 1992-07-03 1992-07-03 Fault location device Expired - Fee Related JP3183957B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20050692A JP3183957B2 (en) 1992-07-03 1992-07-03 Fault location device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20050692A JP3183957B2 (en) 1992-07-03 1992-07-03 Fault location device

Publications (2)

Publication Number Publication Date
JPH0618601A true JPH0618601A (en) 1994-01-28
JP3183957B2 JP3183957B2 (en) 2001-07-09

Family

ID=16425451

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20050692A Expired - Fee Related JP3183957B2 (en) 1992-07-03 1992-07-03 Fault location device

Country Status (1)

Country Link
JP (1) JP3183957B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113482986A (en) * 2021-06-23 2021-10-08 河北津西钢板桩型钢科技有限公司 Fault detection circuit and equipment of hydraulic control valve

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113482986A (en) * 2021-06-23 2021-10-08 河北津西钢板桩型钢科技有限公司 Fault detection circuit and equipment of hydraulic control valve

Also Published As

Publication number Publication date
JP3183957B2 (en) 2001-07-09

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