JPH06181192A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for planarizing an irregular layer formed on a substrate completely. CONSTITUTION:The method for fabricating semiconductor device comprises a step for forming a polysilicon film 5 having polishing rate lower than an SiO2 film 4 entirely on the irregular SiO2 film 4 formed on an Si substrate 1, and a step for polishing the polysilicon film 5 and the SiO2 film 4 thus planarizing the SiO2 film 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a flattening technique for flattening a film to be processed by polishing.

[0002]

2. Description of the Related Art In recent years, a large-scale integrated circuit formed by integrating a large number of transistors, resistors, etc., on one chip in an important part of a computer or communication equipment so as to achieve an electric circuit ( LSI) is frequently used. Therefore, the performance of the entire device is largely linked to the performance of the LSI alone.

The performance improvement of the LSI itself can be realized by increasing the degree of integration, that is, by miniaturizing the elements. For this reason, in recent years, the degree of integration of semiconductor devices has increased, and along with this, miniaturization of wiring width and wiring film thickness and multilayer wiring have been promoted.

A planarization technique is one of the important techniques for realizing multi-layer wiring. The conventional planarization technique will be described with reference to the process sectional view of FIG. 9. First, as shown in FIG. 9A, a SiO ₂ film 42 is formed on a Si substrate 41,
Then, a 1.1 μm thick metal wiring 43 is formed on the SiO ₂ film 42.

Next, as shown in FIG. 9 (b), Si is formed on the entire surface.
The O ₂ film 44 is deposited. At this time, irregularities are formed on the surface of the SiO ₂ film 44 corresponding to the pattern of the metal wiring 43.
Next, the surface of the SiO ₂ film 44 is polished to remove the SiO ₂ film 44.
To remove the irregularities on the surface. The SiO ₂ film 44 is polished by using the polishing apparatus shown in FIG.

That is, the Si substrate 41 is set on the load body 103, and the Si substrate 41 is rotated on the turntable 100. A polishing agent supply pipe 101 is provided on the turntable 100, so that the polishing agent can be continuously supplied during polishing. A polishing cloth 102 is provided between the polishing surface of the Si substrate 41 and the turntable 100, and the polishing cloth 102 and the particles of the polishing agent scrape the surface of the substrate.

In this case, the load body 103 is 40 k
The load of fg is applied and it is rotating at a speed of 100 rpm. The turntable 100 is 100 rp
It is rotating at a speed of m.

However, in this type of method, as shown in FIG.
As shown in (c), the original irregularities on the surface of the SiO ₂ film 44 are alleviated, but the SiO ₂ film 4 between the metal wirings 43 is removed.
4 is slightly depressed, so-called dishing occurs.

FIG. 11 shows the result of detailed examination of this situation. This evaluation is for the case where the width of the metal wiring 43 is 500 μm and the pitch between the metal wiring 43 is 1000 μm. In the figure, the horizontal axis represents the polishing time (seconds) in the step of FIG. 9C. The vertical axis represents the distance from the surface of the SiO ₂ film 42 to the surface of the SiO ₂ film 44.

Before polishing, the surface of the SiO ₂ film 42 where the metal wiring 43 is present (projection) is removed from the surface of the SiO ₂ film 44.
The distance (solid line in the figure) from the surface of the SiO ₂ film 42 to the surface of the SiO ₂ film 44 (the dotted line in the figure) at the portion (concave portion) where the metal wiring 43 is absent. It is 1.1 μm, which is the same as the film thickness of the metal wiring 43.

As the polishing progresses, the polishing rate of the SiO ₂ film 44 on the convex portions is higher than that on the concave portions, so that
The difference between the distance between the _2nd film 42 and the SiO ₂ film 44 and that at the convex portion becomes smaller. Here, the convex portion of the SiO ₂ film 44
The reason why the polishing speed of the
_This is because the load concentrates on the _two films 44.

However, the SiO ₂ film 4 on the convex portion
The speed at which the difference between the distance between the 2 · SiO ₂ films 44 and that in the recesses shrinks very slowly, and when polishing is performed for about 70 seconds and the SiO ₂ film 44 on the protrusions is removed by polishing by about 1.0 μm, The SiO ₂ film 44 in the concave portion is also removed by polishing by about 0.65 μm, and as a result, the SiO ₂ film 42 in the convex portion is removed.
The difference between the distance between the SiO ₂ films 44 and that in the recess is about 0.35 μm.

In order to completely flatten the surface of the SiO ₂ film 44 by this method, the polishing amount may be increased. That is, the SiO ₂ film 44 may be thickly formed and polished.

However, with this method, the polishing time becomes very long, and such a long polishing time causes an increase in production cost. Further, since the variation of the polishing rate within the surface of the substrate to be polished increases in proportion to the polishing amount, it is not desirable to increase the polishing amount as described above.

In order to prevent the dishing of the concave portion caused by the above method, for example, a film of silicon nitride or the like is provided as a polishing stopper for the concave portion to form the SiO ₂ film 4 in the concave portion.
It is sufficient to suppress the polishing of No. 4 and increase the speed at which the difference between the thickness of the SiO ₂ film 44 at the convex portion and that at the concave portion is reduced.

This method will be described with reference to the process sectional view of FIG. 12. First, as shown in FIG. 12A, as in the previous method, the SiO ₂ film 62 and the metal wiring 63 are formed on the Si substrate 61. (Thickness 1.1 μm) is formed. Next, FIG. 12 (b)
, The entire surface is covered with Si so that the metal wiring 63 is hidden.
The O ₂ film 64 is deposited.

Next, as shown in FIG. 12 (c), SiO ₂
After depositing the silicon nitride film 65 on the film 64, the silicon nitride film 65 is patterned so that the silicon nitride film 65 is formed only on the SiO ₂ film 64 in the concave portion where the metal wiring 63 is not formed.
Selectively leave. After this, as in the previous method, FIG.
The surface of the SiO ₂ film 64 is polished by using the polishing apparatus shown in FIG.

According to this method, as shown in FIG. 12D, it is possible to alleviate the original unevenness of the surface of the SiO ₂ film 64 and prevent the dishing of the recess.
However, the SiO ₂ film 64 between the metal wirings 63 is slightly protruded, and the shape of the SiO ₂ film 64 after polishing has a concavo-convex shape reverse to the shape before polishing.

FIG. 13 shows the result of detailed examination of this situation. In this evaluation, the width of the metal wiring 63 is 500 μm and the pitch between the metal wiring 63 is 1000 μm. In the figure, the horizontal axis represents the polishing time (seconds) in the process of FIG. The vertical axis represents the distance from the surface of the SiO ₂ film 62 to the surface of the SiO ₂ film 44.

Before polishing, the surface of the SiO ₂ film 62 where the metal wiring 63 is present (projection) is removed from the surface of the SiO ₂ film 64.
The distance from the surface of the SiO ₂ film 62 to the surface of the SiO ₂ film 64 (dotted line in the figure) is both metal. It is 1.1 μm, which is the same as the film thickness of the wiring 63.

When polishing is started, the convex portion of the SiO ₂ film 64 is formed.
Since the polishing speed of S is higher than that of the concave,
The difference between the distance between the iO ₂ 62 and SiO ₂ films 64 and that in the recesses is getting smaller. Here, the convex portion of the SiO ₂ film 6
The reason that the polishing speed of No. 4 is higher than that of the concave portions is that when polishing those having irregularities, the load is concentrated on the convex portions. Further, in this method, since the silicon nitride film 65 as a stopper film is provided in the concave portion, the polishing rate of the SiO ₂ film 64 in the concave portion is much slower than that of the convex portion, and the SiO ₂ film 64 in the convex portion is Depending on the polishing rate, SiO in the convex part
The difference between the distance between the _2nd film 62 and the SiO ₂ film 64 and that in the recess decreases.

Then, about 70 seconds after the start of polishing, the difference between the distance between the SiO ₂ film 62 and the SiO ₂ film 64 in the recess and that in the recess becomes almost zero, and the surface of the SiO ₂ film 64 becomes flat. However, even if the surface of the SiO ₂ film 64 becomes flat, polishing continues thereafter, so that the portion not covered with the silicon nitride film 65, that is, the S
The iO ₂ film 64 is polished and becomes thinner.

As a result, the SiO ₂ film 62
The distance between the SiO ₂ films 64 is smaller than that in the recesses, and the shape of the SiO ₂ film 64 after polishing has the irregularities reversed from the shape before polishing.

[0024] To prevent the reversal of such a shape of the SiO ₂ film 64, when the surface of the SiO ₂ film 64 becomes flat, so that the silicon nitride film 65 disappears, the thickness of the silicon nitride film 65 However, there is a problem that the optimum film thickness range is narrow and it is not practical. In addition, the step of forming a stopper film such as the silicon nitride film 65 and patterning it, which is an essential step in this method, is complicated and costly.

[0025]

As described above, the conventional method of flattening an insulating film by polishing has a problem that dishing occurs in the concave portion and complete flattening is difficult. Therefore, in order to suppress the occurrence of dishing, a method has been attempted in which a stopper film such as a silicon nitride film is selectively provided in the recess and polishing is performed.

In this method, however, dishing occurs in the insulating film on the convex portion having no stopper film immediately after the flattening of the insulating film is achieved by polishing. There was a problem that it was difficult.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device having a step of completely planarizing a layer to be processed. .

[0028]

In order to achieve the above object, in the method for manufacturing a semiconductor device of the present invention, a polishing rate is applied to the entire surface of a film to be processed having an uneven portion formed on a substrate. The method further comprises a step of forming a polishing auxiliary film slower than that of the processed film, and a step of polishing the surface of the substrate on the side where the polishing auxiliary film is formed to flatten the film to be processed. .

[0029]

According to the research conducted by the present inventors, after forming a polishing auxiliary film having a polishing rate slower than that of the film to be processed on the entire surface of the film to be processed having an uneven portion, the polishing auxiliary film and the film to be processed are formed. It was found that the polishing can remove the uneven portion of the film to be processed and flatten the film to be processed without causing dishing. It is considered that this flattening is realized for the following reasons. Generally, since the load applied to the convex portion is larger than that of the concave portion, the polishing rate of the convex portion is faster than that of the concave portion. Therefore, in the initial stage of polishing, it is considered that the polishing assisting film on the convex portion is mainly polished. At this stage, the unevenness of the film to be processed is not yet relaxed. When the polishing auxiliary film on the convex portion is polished and the polishing auxiliary film on the convex portion disappears, then the film to be processed on the convex portion is mainly polished, and the unevenness of the film to be processed is alleviated.

Then, as the unevenness of the film to be processed is alleviated, the polishing assisting film in the recess gradually becomes thinner, and at some point the polishing assisting film in the recess disappears. At this time, it is considered that the film to be processed becomes flat. Therefore, after that, since the polishing proceeds while keeping the flat shape, the film to be processed can be flattened without causing dishing. Further, according to the research conducted by the present inventors, it has been found that polishing with excellent flatness can be performed without depending much on the film thickness of the polishing auxiliary film, which is highly practical.

[0031]

Embodiments will be described below with reference to the drawings. 1A to 1D are process cross-sectional views showing a method of planarizing an interlayer insulating film according to an embodiment of the present invention. First, as shown in FIG. 1A, an S having a desired semiconductor element (not shown) is formed.
A SiO ₂ film 2 as a base is deposited on the i substrate 1. Next, as shown in FIG. 1B, an Al wiring 3 having a thickness of 1.1 μm is formed on the SiO ₂ film 2. Next, as shown in FIG. 1C, a SiO ₂ film 4 is deposited to a thickness of about 1.2 μm on the entire surface of the substrate on which the Al wiring 3 is formed.

[0032] Next, as shown in FIG. 1 (d), on the SiO ₂ film 4, as a slow film polishing rate than the SiO ₂ film 4, the polysilicon film 5 (polishing auxiliary layer) of about 0.1μm Deposited to a thickness of.

[0033] Thereafter, the polysilicon film is polished 5, SiO ₂ film 4 by using the polishing apparatus shown in FIG. 10, SiO ₂
The irregularities on the surface of the film 4 are removed. As the abrasive, for example, a 1 wt% cerium oxide suspension is used. By such a polishing process, as shown in FIG.
_{2 The} film 4 could be completely flattened.

FIG. 2 shows the result of detailed examination of this situation. In this evaluation, the width of the Al wiring 3 is 500 μm and the pitch between the Al wirings 43 is 1000 μm.
In the figure, the horizontal axis is the polishing time (seconds) in the process of FIG.
Is shown. The vertical axis is from the surface of the SiO ₂ film 2 to SiO ₂
The distance to the surface of the membrane 4 is shown.

Before polishing, the distance (solid line in the figure) from the surface of the SiO ₂ film 2 to the surface of the SiO ₂ film 4 in the portion (convex portion) where the Al wiring 3 is present and the portion where the Al wiring 3 is not present. The distance (dotted line in the drawing) from the surface of the SiO ₂ film 2 to the surface of the SiO ₂ film 4 in the (concave portion) is 1.1 μm, which is the same as the film thickness of the Al wiring 3.

When the polishing is performed, first, the convex polysilicon film 5 is removed. When the polishing time is about 30 seconds, the convex polysilicon film 5 is completely removed and the convex SiO ₂ film is removed. The film 4 is exposed. The convex portion of the polysilicon film 5 is removed preferentially because the load applied to the convex portion is larger than that of the concave portion.

When the convex polysilicon film 5 disappears, the convex SiO ₂ film 4 is then removed by polishing. During this time, the polysilicon film 5 in the recess is gradually removed by polishing. However, since the load applied to the concave portion is smaller than that of the convex portion, the polysilicon film 5 remains in the concave portion even while the SiO ₂ film 4 of the convex portion is removed by polishing.

As the convex SiO ₂ film 4 is removed by polishing, the irregularities on the surface of the SiO ₂ film 4 are alleviated. Then, when the polishing time was about 100 seconds, the polysilicon film 5 in the recess disappeared almost completely, and the surface of the SiO ₂ film 4 became almost completely flat. Therefore, the flattening of the SiO ₂ film 4 can be achieved with the required minimum amount of scraping without causing dishing. After the polishing time of about 100 seconds, the flattened SiO ₂ film 4 is polished, so that the unevenness does not appear again.

As described above, according to the flattening method by polishing of the present embodiment, the polishing is performed by providing the polysilicon film 5 having a polishing rate slower than that on the SiO ₂ film 4, which is necessary. The SiO ₂ film 4 can be flattened with a minimum amount of shaving. Further, even if polishing is continued after the flattening of the SiO ₂ film 4 is achieved, the SiO ₂ film 4 does not have irregularities.

Further, in this embodiment, the thickness of the polysilicon film 5 is set to 0.1 μm, but the polysilicon film 5 in the recess is formed.
Is polished corresponding to the convex polysilicon film 5, so that the margin of the film thickness of the polysilicon film 5 becomes wide. Actually, similar results were obtained by using a polysilicon film having a film thickness of 0.08 μm and 0.15 μm.

As described above, in the flattening method of this embodiment, the film thickness margin of the polysilicon film 5 is large, and a stopper film such as a silicon nitride film is formed and patterned as in the conventional case. That is, it is highly practical because it does not require a complicated and costly process. Further, according to the research conducted by the present inventors, it has been found that the SiO ₂ film as the film to be processed exhibits the same temporal change regardless of the wiring width / pitch interval.

3 to 7, the wiring width / pitch interval is 2, 50, 100, 200, 500, respectively, from the surface of the SiO ₂ film as the base in the convex portion to the processed film. _{2 to} the surface of the SiO ₂ film, and the distance from the surface of the SiO ₂ film as the base in the recess to the surface of the SiO ₂ film as the film to be processed.

From these FIGS. 3 to 7, the SiO ₂ film as the film to be processed in the recesses is not polished at the initial stage of polishing regardless of the wiring width / pitch interval, and the recesses and protrusions are formed after a certain time from the start of polishing. It can be seen that the SiO ₂ film as the film to be processed in some portions is polished at almost the same rate.

Further, according to the study by the present inventors, FIG.
In the case of the structure as shown in (d), the thickness x of the Al wiring 3 (which is not limited to the Al wiring, that is, the base film which causes the uneven portion of the film to be processed) is 0.5 ≦ x ≦ 1. If the range is 5,
The thickness and polishing rate of the polysilicon film 5 (which is not limited to the polysilicon film, that is, a film having a slower polishing rate than the film to be processed) are A and a, respectively, and the SiO ₂ film 4 is used.
It has been found that good results can be obtained under the condition of 100a ≦ b · B ≦ 250a, where b is the polishing rate of (not limited to the SiO ₂ film, that is, the film to be processed).

That is, the thickness of the base film is 0.5 ≦ x ≦
It has been found that in the case of the range of 1.5, if the polishing is performed under the above conditions, the film to be processed can be completely flattened regardless of the film thickness of the film to be processed.

In the case of the present invention, the film having a low polishing rate (polishing auxiliary film) on the film to be processed must have a polishing rate lower than that of the film to be processed. It is necessary to pay attention to.

That is, even if the load of the load body is set to W, as shown in FIG. 8C, so that the polishing rate of the film to be processed is faster than that of the auxiliary film for polishing, the polishing is not performed during polishing. If the load fluctuates toward the smaller side, the polishing rate of the film to be processed a may be slower than that of the auxiliary polishing film b. For this reason,
As shown in FIGS. 8A and 8B, it is important that the polishing speed of the film to be processed a is always higher than that of the auxiliary polishing film b regardless of the value of the load.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the case where the SiO ₂ film is used as the film to be processed and the polysilicon film is used as the film whose polishing rate is slower than that of the film to be processed has been described, but these films may be other films. Furthermore, the abrasive is not limited to cerium oxide.

Table 1 shows an abrasive (1 wt% cerium oxide suspension, colloidal silker having SiO ₂ particles dispersed therein), a film to be processed (undoped SiO ₂ film, SiN film,
(Polysilicon film, carbon film, SiO ₂ film containing B and P)
And the polishing rate relationship with is shown.

[0050]

[Table 1]

From Table 1, as the polishing agent and the film to be processed,
It can be seen that when a cerium oxide suspension and a SiO ₂ film (undoped) are used, a silicon nitride film, a carbon film, or the like can be used as the film having a slow polishing rate, in addition to the polysilicon film.

It is also understood that the silicon nitride film and the carbon film can be used even when colloidal silker and SiO ₂ film (undoped) are used as the polishing agent and the film to be processed, respectively.

Further, although the case where the film to be processed is an insulating film has been described in the above embodiment, the present invention can be applied to a metal film. In this case, for example, SiO ₂ having grooves on the surface
A W film as a film to be processed and a Cu film as a film having a slow polishing rate are sequentially deposited on the entire surface of the film to polish the W film and the Cu film.
In this case, the Cu film is hard to be sufficiently polished as compared with the W film, so that the types of abrasives are in a wide range. The present invention can also be applied to semiconductor substrates other than Si substrates and semi-insulating substrates. In addition, within the scope of the present invention,
Various modifications can be implemented.

[0054]

As described in detail above, according to the present invention, after forming a polishing auxiliary film having a polishing rate slower than that of a film to be processed on the film to be processed having an uneven portion, the film to be processed and the polishing are performed. By polishing the auxiliary film, the film to be processed can be planarized without causing dishing or an increase in the number of steps.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method of planarizing an interlayer insulating film according to an embodiment of the present invention.

FIG. 2 Si as a film to be processed by the planarization method of the present invention
Shows the time course of the O ₂ film.

FIG. 3 is a diagram showing changes with time of a SiO ₂ film as a film to be processed by the planarizing method of the present invention when the wiring width / pitch interval is 2.

FIG. 4 is a diagram showing a change with time of a SiO ₂ film as a film to be processed by a planarizing method of the present invention when a wiring width / pitch interval is 50.

FIG. 5 is a diagram showing a change with time of a SiO ₂ film as a film to be processed by the planarizing method of the present invention when the wiring width / pitch interval is 100.

FIG. 6 is a diagram showing changes with time of a SiO ₂ film as a film to be processed by the planarization method of the present invention when the wiring width / pitch interval is 200.

FIG. 7 is a diagram showing changes with time of a SiO ₂ film as a film to be processed by the planarizing method of the present invention when the wiring width / pitch interval is 500.

FIG. 8 is a view for explaining a preferable relationship between a polishing rate of a film to be processed and that of an auxiliary polishing film when a load is used as a parameter.

FIG. 9 is a process cross-sectional view for explaining a conventional flattening technique.

FIG. 10 is a schematic diagram showing a schematic configuration of a polishing apparatus.

FIG. 11: Si as a film to be processed by a conventional planarization method
Shows the time course of the O ₂ film.

FIG. 12 is a process sectional view for explaining another conventional flattening technique.

FIG. 13 is a view showing a change with time of a SiO ₂ film as a film to be processed by another conventional flattening method.

[Explanation of symbols]

1, 41, 61 ... Si substrate _2, 42, 62 ... SiO ₂ film 3, 43, 63 ... Metal (Al) wiring 4, 44, 64 ... SiO ₂ film (working film) 5 ... Polysilicon film (polishing assistance) Film 6) Silicon nitride film 100 ... Turntable 101 ... Abrasive supply pipe 102 ... Polishing cloth 103 ... Load body

Claims (1)

[Claims] 1. A process of forming a polishing auxiliary film having a polishing rate slower than that of the film to be processed on the entire surface of the film to be processed having an uneven portion formed on a substrate, and the film of the polishing auxiliary is formed. Side substrate surface,
And a step of planarizing the film to be processed.