JPH06177663A - Optic/electric conversion transistor circuit - Google Patents

Abstract

PURPOSE:To provide a grounded base optic/electric conversion transistor (TR) circuit which is less effected by a power supply voltage fluctuation. CONSTITUTION:A collector of a TR Q1 is connected to a power supply VCC 1 via a load resistor R1 and its emitter is connected to a power supply VEE1 at a connecting point N1 via a load resistor R2. Its base is connected to the power supply VCC1 via a load resistor R3 and connected to the N1 via diodes D1, D2. An anode of a photo diode PD is connected to a connecting point between the emitter and the load resistor R2 and a bias voltage VH is given to the cathode. The output signal is obtained from a connecting point OUT1 between the load resistor R1 and the collector. The grounded base optic/electric conversion TR circuit which is less effected by a power supply voltage fluctuation is realized by keeping the difference of voltages between the base of the TRQ1 and the point N1 constant by means of the diodes D1, D2.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a photoelectric conversion transistor circuit.

[0002]

2. Description of the Related Art Generally, it is known that a grounded base type amplifier circuit has better characteristics in a high frequency region than a grounded emitter type amplifier circuit. Therefore, by inputting the output signal of the photodetector to the grounded base type amplifier circuit, it is expected to realize a higher speed photoelectric conversion circuit than the grounded emitter type photoelectric conversion circuit. As a conventional technique, Japanese Patent Laid-Open No. 3-7
There is a preamplifier circuit in the equivalent amplifier circuit of the optical signal receiving device described in No. 0305. FIG. 11 shows an example of the preamplifier circuit. The circuit has a collector and an output terminal OU.
It is connected to the power supply VCC via T and the load resistance RL, and the emitter is connected to the power supply VE via the input terminal IN and the load resistance RE.
Connected to E, the base connected to the power supply VCC through the diodes D1 and D2 to supply the bias current,
It is composed of a transistor Q1 which is connected to a power source VEE via a load resistor RB to set an operating point, and a photodetector 101 which is connected to an input terminal IN.

[0003]

SUMMARY OF THE INVENTION In the above conventional technique,
When the power supply VEE changes, the base potential of the transistor Q1 is fixed with respect to the power supply VCC, so the base potential with respect to the connection point N1 between the load resistor RE and the power supply VEE changes. When the base potential changes, the circuit operates as a grounded-emitter amplifier. As a result, the power supply VEE
The problem arises that the fluctuations in the output are amplified and output. Further, when the power supply VCC fluctuates, the base potential of the transistor Q1 with respect to the power supply VEE fluctuates following the fluctuation, which causes a problem of amplifying and outputting the fluctuation of the power supply VCC.

An object of the present invention is to provide a base-grounded photoelectric conversion transistor circuit which is less affected by power supply voltage fluctuations.

[0005]

The principle of the present invention is shown in FIG. An object of the present invention is to set the bias VB applied to the base of the grounded base transistor Q1 to the load resistance RE and the power supply V
This can be achieved by providing by means for following the fluctuation of the potential of the connection point N1 with the EE.

[0006]

Since the potential difference between the base of the grounded base transistor Q1 and N1 is kept constant by the bias means VB that follows the fluctuation of the potential of N1, the circuit does not operate as a grounded-emitter amplifier circuit, and the power supply does not operate. It does not amplify and output fluctuations of VEE and power supply VCC. Therefore,
According to the present invention, it is possible to provide a base-grounded photoelectric conversion circuit that is less affected by power supply voltage fluctuations.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

A first embodiment is shown in FIG. The collector of the transistor Q1 is connected to the power supply VCC1 via the load resistor R1, and the emitter is connected to the power supply VEE1 via the load resistor R2.
Connect to. Here, the connection point between the load resistor R2 and the power supply VEE1 is N1. The base is connected to the power supply VCC1 via the load resistor R3 and the diode N1 via the diodes D1 and D2 at the connection point N2. The anode of the photodiode PD is connected to the connection point between the emitter of the transistor Q1 and the load resistor R2, and the cathode is supplied with the bias voltage VH. The output is obtained from the connection point OUT1 between the collector and the load resistor R1. When an optical signal is input to the photodiode PD, a photocurrent is generated and flows into the load resistor R2.
Since the potential difference between N2 and N1 is kept constant by the forward voltage of the diodes D1 and D2, the transistor Q1 changes the emitter current so that the sum of the base-emitter voltage and the voltage drop of R2 becomes constant. Let A change in the emitter current results in a change in the collector current, which changes the potential of OUT1 and becomes an output signal. Consider now the potential fluctuations of N1 and N2 when the potential of the power supply VEE1 changes. N
The potential of 1 changes following the fluctuation. On the other hand, the potential of N2 becomes a value obtained by adding the forward voltage of the diodes D1 and D2 to N1, and changes in accordance with the potential change of the power supply VEE1 as in N1. However, since the potential difference between N2 and N1 has a constant value regardless of the fluctuation of the power supply VEE1, the circuit does not operate as a grounded-emitter circuit. Therefore, the present embodiment is not affected by the fluctuation of the power source VEE1,
Moreover, the fluctuation of the power supply VCC1 is not amplified and output. Also,
The base potential can be set to a desired potential by changing the forward voltage per diode, the number of diodes connected in series, or the current passed through the diodes.

A second embodiment of the present invention is shown in FIG. First
In the same manner as in the above embodiment, the transistor Q1 and the load resistors R1 and R
2 constitutes a base ground circuit, and the connection point between the load resistor R2 and the power source VEE1 is N1. Photodiode P
The anode of D is connected to the connection point of the emitter of the transistor Q1 and the load resistor R2, and the bias voltage V is connected to the cathode.
Give H. The output is obtained from the connection point OUT1 between the collector of the transistor Q1 and the load resistor R1. Transistor Q
The bias applied to the base of 1 is transistors Q2, Q
3 and load resistors R4, R5 and R6. The collector of the transistor Q2 is connected to the load resistor R4
Connected to the power supply VCC1 via the load resistor R5
Connected to the power supply VCC1 via the
Connect to N1 via 6. Here, the transistor Q2
The connection point between the base of R and the load resistor R5 is N2. next,
The collector of the transistor Q3 is connected to N2, the base is connected to the connection point between the emitter of the transistor Q2 and the load resistor R6, and the emitter is connected to N1. Then, the base of the transistor Q1 is connected to N2. According to the same principle as in the first embodiment, the potential difference between N2 and N1 is kept constant by the base-emitter voltage of the transistors Q2 and Q3. Therefore, the present embodiment is not affected by the fluctuation of the power supply VEE1 and does not amplify and output the fluctuation of the power supply VCC1. Next, the effect peculiar to this embodiment will be described. now,
Consider a case where the base-emitter voltage of the transistors Q2 and Q3 is increased due to a change in temperature or manufacturing variation. Then, the base potential of the transistor Q1 tries to rise, but at the same time, the current flowing through the load resistor R5 increases, and the voltage drop generated in the load resistor R5 increases, and N2 increases.
The potential of drops. Conversely, when the base-emitter voltage of the transistors Q2 and Q3 decreases, the base potential of the transistor Q1 tries to drop, but at the same time, the current flowing through the load resistor R5 decreases and the voltage drop caused by the load resistor R5 occurs. Decreases and the potential of N2 rises. By the above operation, the potential difference between N2 and N1 is
It is held at a constant value regardless of the increase / decrease in the base-emitter voltage of 3 and the fluctuation of the power supply VEE1.

A third embodiment of the present invention is shown in FIG. Second
In place of the load resistor R6 in the embodiment of FIG.
C1 is provided to form a current mirror circuit with the transistor Q3. Also in this case, the same effect as that of the second embodiment can be expected.

A fourth embodiment of the present invention is shown in FIG. In this embodiment, the means for supplying the bias VB applied to the base of the transistor Q1 is not shown. This embodiment is composed of a grounded base circuit composed of a transistor Q1 and load resistors R1 and R2, and an emitter follower circuit composed of a transistor Q4 and load resistor R7. The anode of the photodiode PD is connected to the connection point between the emitter of the transistor Q1 and the load resistor R2, and the cathode is supplied with the bias voltage VH. The collector of the transistor Q4 is connected to the power supply VCC2, the base is connected to the connection point between the collector of the transistor Q1 and the load resistance R1, and the emitter is connected to the power supply VEE2 via the load resistance R7. The output is the connection point O between the emitter of the transistor Q4 and the load resistor R7.
Obtained from UT2. When there is no emitter follower circuit, the output impedance of the grounded base circuit becomes the value of the load resistance R1, and when the output signal line is long, this R1 and the stray capacitance due to the wiring may form a low-pass filter. Further, the output may be divided by the output impedance and the load connected to the output terminal, and the output signal amplitude may decrease. In this embodiment, the emitter-follower circuit is connected to the base-grounded photoelectric conversion circuit, so that the output impedance of the circuit is lowered and the load driving capability is enhanced, and the effect on the stray capacitance and the load is reduced.

A fifth embodiment of the present invention is shown in FIG. In this embodiment, the means for supplying the bias VB applied to the bases of the transistors Q1 and Q5 is not shown. In this embodiment, a base ground circuit group including at least transistors Q1 and Q5 and load resistors R1, R2, R8, and R9,
An emitter follower circuit group including transistors Q4 and Q6 and load resistors R7 and R10, and a differential amplifier A1. The anode of the photodiode PD is connected to the connection point between the emitter of the transistor Q1 and the load resistor R2,
A bias voltage VH is applied to the cathode. A connection point N1 between the emitter of the transistor Q4 and the load resistance R7, and a connection point N between the emitter of the transistor Q6 and the load resistance R10.
2 are connected to the input terminals of the differential amplifier A1, that is, the bases of the transistors QA1 and QA2.
The differential amplifier A1 includes transistors QA1 and QA2, load resistors RA1 and RA2, and a constant current source IG. The collectors of the transistors QA1 and QA2 are connected to the output terminal T1 and the output terminal T2, respectively, and
It is connected to the power supply VCC3 via the load resistors RA1 and RA2. The emitters of the transistors QA1 and QA2 are directly connected,
It is connected to the power supply VEE3 via the constant current source IG. According to the present embodiment, the fluctuation of the power supply VCC1 is input to the differential amplifier A1 as an in-phase signal via the emitter follower circuit. Since the differential amplifier has a function of suppressing the in-phase signal, according to the present embodiment, it is possible to realize the grounded base photoelectric conversion circuit which is not affected by the fluctuation of the power supply VCC1.

A sixth embodiment of the present invention is shown in FIG. This embodiment is an example of means for supplying the bias VB in the fifth embodiment. A transistor Q7 and a load resistor R11 are added to the fifth embodiment. The collector of the transistor Q7 is connected to the power supply VCC1 via the load resistor R11, and the base is the emitter of the transistor Q5 and the load resistor R1.
9 and the emitter is connected to the connection point between the load resistor R2 and the power supply VEE1. And the load resistance R1
Bias VB is supplied from the connection point of 1 and the collector of the transistor Q7. The circuit including the transistors Q5 and Q7 and the load resistors R8, R9 and R11 in this embodiment is
It has the same configuration as the circuit for applying a bias to the base of the transistor Q1 in the second embodiment. Therefore, this embodiment combines the effects of the second and fifth embodiments, and the number of parts can be reduced as compared with the case where the second and fifth embodiments are separately configured and combined. effective.

A seventh embodiment of the present invention is shown in FIG. This embodiment differs from the fifth embodiment in the method of connecting the photodiode PD. In this embodiment, the cathode of the photodiode PD is connected to the bias VH via the load resistance R12, and the connection point between the cathode and the load resistance R12 is connected to the connection point between the emitter of the transistor Q5 and the load resistance R9 via the capacitor C1. Connect to. By setting the time constant determined by the load resistor R12 and the capacitor C1 to be sufficiently longer than the period of the received optical pulse, the photocurrent increases the emitter current of the transistor Q5, and the photocurrent increases.
It flows so as to reduce the emitter current of 1. Therefore, the base-grounded circuit formed by the transistor Q1 and the base-grounded circuit formed by the transistor Q5 input signals having opposite phases to each other, and thus output signals having opposite phases. As a result, mutually opposite-phase signals are input to the differential amplifier A1, and an output signal amplitude twice as large as that when a single-phase signal is input is obtained. That is, according to this embodiment, it is possible to realize a photoelectric conversion circuit having a double amplification factor as compared with the fifth embodiment.

An eighth embodiment of the present invention is shown in FIG. In this embodiment, four base-grounded photoelectric conversion circuits 201 to 2 are used.
04 is integrated on the substrate 301, and bias circuits 401 to 404 for grounded base transistors are provided for each circuit. By integrating a plurality of opto-electric conversion circuits on the same substrate, a single chip can receive multi-channel optical signals. However, when a plurality of base-grounded photoelectric conversion circuits are integrated in one chip, the operating point may vary from circuit to circuit due to fluctuations in the power supply potential depending on the location in the chip. According to the present embodiment, each circuit is provided with the bias circuit for the grounded base transistor, so that there is an effect that the influence of the fluctuation of the power supply potential depending on the place can be suppressed. Also, by integrating the circuit elements including the photodetector on the same substrate, the influence of the parasitic reactance of the wiring can be minimized, and high-speed operation of the circuit can be expected. Examples of the substrate material on which the photodetector and the transistor element can be integrated include Si, GaAs, and InP.

A ninth embodiment of the present invention is shown in FIG. In this embodiment, the circuit portion 501 of the base-grounded photoelectric conversion circuit excluding the photodetector is integrated on the substrate 301, and the photodetector 1
01 is flip-chip mounted on the substrate 301. The photodetector 101 is connected to the circuit 501 formed on the substrate 301 by solder bumps 601 and 602. Compared to the technique of monolithically integrating the photodetector and other circuit elements as in the eighth embodiment, the photodetector can be easily integrated by the flip-chip mounting technique. Therefore, according to this embodiment, it is possible to easily realize a circuit that can operate at high speed.

A tenth embodiment of the present invention is shown in FIG.
In this embodiment, the circuit portion 501 excluding the photodetector is mounted on the substrate 3
01, the photodetector 101 is embedded in a hole 701 provided in the substrate 301 and fixed by a filling material 702. The photodetector 101 is a circuit 5 formed on the substrate.
01 and the wiring 703. According to the present embodiment, the surface of the substrate 301 becomes a flat surface as compared with the flip chip mounting technology described in the ninth embodiment, and another electronic circuit chip 704 is mounted on the substrate surface by flip chip mounting. Can be accumulated. Therefore, according to this embodiment,
A transistor circuit with high integration density can be realized.

An eleventh embodiment of the present invention is shown in FIG.
In this embodiment, N1 and N2 are connected by a capacitor C2 in the first embodiment, and power supplies VCC1 and N2 are connected by a capacitor C2.
3 are connected. According to this embodiment, the power supply VC
Since the fluctuations of C1 and the power supply VEE1 are absorbed by the capacitors C2 and C3, it is possible to realize a grounded base photoelectric conversion circuit which is less affected by the fluctuations of the power supply voltage as compared with the first embodiment.

A twelfth embodiment of the present invention is shown in FIG.
The cathode of the photodiode PD1 is connected to the bias VH1 and the anode of the photodiode PD1 is connected to the emitter of the transistor Q1.
Connect to the connection point with the load means of. The cathode of the photodiode PD2 is connected to the bias VH2, and the anode is connected to the connection point between the emitter of the transistor Q5 and the load resistor R9. According to this embodiment, a transistor circuit that receives a differential optical signal can be realized by inputting signals of opposite phases to the photodiodes PD1 and PD2.

It can be easily inferred that the transistor used in this embodiment can be realized not only by using a bipolar transistor made of silicon or a compound semiconductor but also by using a field effect transistor.

The photodiode used in this embodiment can be either a PIN photodiode or an MSM photodiode, or a photoconductor can be used as a photodetector instead of the photodiode.

[0022]

As described above, according to the present invention,
It is possible to realize a base-grounded photoelectric conversion circuit that is stable against fluctuations in power supply voltage.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing a third embodiment of the present invention.

FIG. 4 is a diagram showing a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a fifth embodiment of the present invention.

FIG. 6 is a diagram showing a sixth embodiment of the present invention.

FIG. 7 is a diagram showing a seventh embodiment of the present invention.

FIG. 8 is a diagram showing an eighth embodiment of the present invention.

FIG. 9 is a diagram showing a ninth embodiment of the present invention.

FIG. 10 is a diagram showing a tenth embodiment of the present invention.

FIG. 11 is a diagram illustrating a conventional technique.

FIG. 12 is a diagram illustrating the principle of the present invention.

FIG. 13 is a diagram showing an eleventh embodiment of the present invention.

FIG. 14 is a diagram showing a twelfth embodiment of the present invention.

[Explanation of symbols]

Q1-Q7, QA1, QA2, QC1: Transistor, RL, RE, RB, R1-R12, RA1, RA2: Load resistance, C1, C2, C3: Capacitor, D1, D2: Diode, PD, PD1, PD2: Photodiode , VCC, VCC1, VCC2, VCC3, VEE, VEE1, VEE2, VEE3: power supply, VB, VH, VH1, VH2: bias, A1: differential amplifier, IG: constant current source, N1, N2: connection point of elements, IN: input terminal, OUT, OUT1, OUT2, T1, T2: output terminal, 101: photodetector, 201-204: base-grounded photoelectric conversion circuit, 301: substrate, 401-404: bias circuit, 501: light Circuit part of base-grounded photoelectric conversion circuit excluding detector, 601, 602: solder bumps, 701: holes, 702: Filler, 703: Wiring, 704: Electronic circuit chip.

Claims (14)

[Claims] 1. A first collector is connected to a first power supply through a first load means, a first base is connected to a first bias, and a first emitter is connected to a second load means. Second through
A first transistor connected to the power supply of the first light source, a first terminal connected to a connection point between the first emitter and the second load means, and a second light source connected to the second bias. In a transistor circuit having a detector and a first output terminal connected to the connection point between the first load means and the first collector, with respect to the potential at the connection point between the second load means and the second power source, ,
A transistor circuit comprising: a bias unit that follows the potential of the first bias. 2. The transistor circuit according to claim 1, wherein the bias means comprises one diode or a diode circuit in which two or more diodes are connected in series, and the anode of the diode circuit is connected to the third load means. To the first power source, the cathode of the diode circuit is connected to the connection point of the second load means and the second power source, and the first point is connected to the connection point of the anode and the third load means. A transistor circuit characterized by obtaining a bias. 3. The transistor circuit according to claim 1, wherein the bias means connects the second collector to the first power supply through the fourth load means and the second base to the fifth load means. A second transistor connected to the first power supply via the second transistor, and a second emitter connected to the connection point between the second load means and the second power supply via the sixth load means; The collector is connected to the connection point between the second base and the fifth load means, the third base is connected to the connection point between the second emitter and the sixth load means, and the third emitter is connected to the second Transistor circuit comprising a third transistor connected to a connection point between the load means and the second power source, and obtaining a first bias from a connection point between the third collector and the fifth load means. . 4. The fourth collector is connected to a third power supply, the fourth base is connected to the first output terminal, and the fourth emitter is connected to the fourth power supply via the seventh load means. 4. A fourth transistor connected thereto, and a second output terminal connected to a connection point between the fourth emitter and the seventh load means, further comprising: a fourth output terminal connected to the fourth emitter. The transistor circuit according to. 5. A fifth collector is connected to a first power supply via an eighth load means, a fifth base is connected to a first bias, and a fifth emitter is connected to a ninth load means. Second through
A fifth transistor connected to a connection point between the load means and the second power supply, a sixth collector connected to the third power supply, a sixth base connected to the fifth collector and an eighth load means. Connect to the connection point of
A sixth transistor in which the sixth emitter is connected to the fourth power supply through the tenth load means, and a third output terminal connected to a connection point between the tenth load means and the sixth emitter, 5. A differential amplifier further comprising a second output terminal and a third output terminal connected as inputs, the differential amplifier.
The transistor circuit described. 6. The seventh collector is connected to the first power supply through the eleventh load means, and the seventh base is connected to a connection point between the fifth emitter and the ninth load means. A seventh transistor having an emitter connected to a connection point between the second load means and the second power source, and a seventh collector and a first collector;
6. The transistor circuit according to claim 5, wherein the first bias is obtained from a connection point with one load means. 7. The transistor circuit according to claim 5, wherein the second terminal is connected to the second bias via the twelfth load means, and a connection point between the second terminal and the twelfth load means is provided. A transistor circuit, wherein a connection point between the fifth emitter and the ninth load means is connected via the first capacitance means. 8. The method according to claim 1, wherein at least one or more of the transistor circuits or the transistor circuits excluding the photodetector from the circuit are monolithically integrated on the same substrate. The transistor circuit according to claim 1. 9. The transistor circuit according to claim 8, further comprising a bias unit that applies a first bias to each of the transistor circuits. 10. The transistor circuit according to claim 8, wherein the photodetector comprises a photodiode or a photoconductor. 11. The transistor circuit according to claim 8, wherein the photodetector is flip-chip mounted or hybrid mounted on the substrate. 12. The transistor circuit according to claim 8, wherein the substrate is made of silicon or a compound semiconductor, and the first to seventh transistors are bipolar transistors or field effect transistors. 13. The transistor circuit according to claim 2, wherein at least one of a connection point between the second load means and the second power supply or the first power supply has a first base and a first power supply. A transistor circuit characterized in that the connection point with the bias of is connected via a capacitance means. 14. A transistor circuit according to claim 5, wherein the third terminal is connected to a third bias, and the fourth terminal is connected to a connection point between the fifth emitter and the ninth load means. A transistor circuit comprising two photodetectors.