JPH06177389A - Vertical field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce the parasitic gate capacitance of the gate electrode of a vertical field-effect transistor. CONSTITUTION:The parasitic gate capacitance of the gate electrode of the vertical field-effect transistor is reduced by providing an intrinsic polysilicon area 7 at the central part of a polysilicon gate electrode 6 and making the thickness of a silicon oxide film 3 formed on the area 7 thickest on the area 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical field effect transistor, and more particularly to a gate electrode.

[0002]

2. Description of the Related Art In a conventional vertical field effect transistor, a silicon oxide film 3 and a polysilicon film 4 are formed on a surface including a drain region 1 and a source region 2 as shown in FIG. Is used as a gate electrode, and the source electrode 5 is insulated by being covered with the silicon oxide film 3.

Further, since the silicon oxide film 3 has a structure for storing a capacitance, as shown in FIG. 5, the gate electrode has a structure in which a part of the polysilicon film 4 is removed.

[0004]

The conventional vertical field effect transistor described above has a structure in which a polysilicon film is used as a gate electrode. Therefore, the gate capacitance is stored in the silicon oxide film, and the electrostatic capacitance C is determined by the area of the polysilicon film that acts as an electrode.

[0005]

From the equation (1), it is clear that the area of the polysilicon film and the thickness of the silicon oxide film are involved in the reduction of the gate capacitance. Has problems such as threshold voltage. Further, in the technique of partially removing the polysilicon film as shown in FIG. 5, there is a problem that an electric field is likely to be generated in a step generated by the removal.

[0007]

A vertical field effect transistor according to the present invention has a vertical electric field having a gate electrode made of a conductive polysilicon film provided on a surface including a drain region and a source region via a gate insulating film. The effect transistor includes an intrinsic polysilicon region provided in the central portion of the gate electrode, and an insulating film thicker than the insulating films in other portions provided on the intrinsic polysilicon region.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIGS. 1A and 1B are a plan view and a sectional view taken along the line AA 'showing an embodiment of the present invention.

As shown in FIGS. 1A and 1B, a P-type base region 23 provided in the N-type drain region 1, an N-type source region 2 provided in the base region 23, and a drain. The gate oxide film 17 provided on the surface including the region 1 and the source region 2, the N-type polysilicon gate electrode 6 provided on the gate oxide film 17, and the intrinsic polysilicon provided at the center of the N-type polysilicon gate electrode 6. And a silicon region 7.

FIG. 2 is a cross-sectional view showing the dimensions of each part of FIG.

As shown in FIG. 2, in the vertical field effect transistor, by applying a voltage to the N-type polysilicon gate electrode 6, the P-type base region 2 immediately below the polysilicon gate electrode 6 is formed.
3 For the operational reason of controlling the current by reversing the conductivity type of the surface to N type, the lateral spread width 8 of the P type base region 23 immediately below the N type polysilicon gate electrode 6 is N
It is necessary to widen the width 9 of the type polysilicon gate electrode 6.

Here, the total width 10 of the polysilicon film is 12
μm, polysilicon gate electrode 6 in P-type base region 23
Assuming that the width 8 of the lateral extension from the end is 3 μm, the width 9 of the N-type polysilicon gate electrode 6 must be wider than 3 μm and the width 11 of the intrinsic polysilicon region 7 must be narrower than 6 μm.

Further, the thickness 12 of the insulating film on the intrinsic polysilicon region 7 is 1.5 μm, and the thickness 1 of the insulating film in the other portions is 1.
3 is about 1 μm.

3 (a) to 3 (e) are sectional views of a semiconductor chip showing the order of steps for explaining a manufacturing method according to an embodiment of the present invention.

First, as shown in FIG. 3A, with the silicon oxide film 15 selectively formed on the surface of the N-type silicon substrate 14 as a mask, P-type impurities are ion-implanted to push in the P ⁺ -type diffusion layer 16. To form.

Next, as shown in FIG. 3B, after removing the silicon oxide film 15, the surface of the N type silicon substrate 14 including the P ⁺ type diffusion layer 16 is thermally oxidized to form a gate oxide film 17. Then, an intrinsic or non-doped polysilicon film 18 and a silicon oxide film 19 are sequentially deposited on the gate oxide film 17 and selectively sequentially etched, and then the silicon oxide film 1 is formed.
P-type impurities are ion-implanted using 9 as a mask, and the ions are pressed to form a P-type diffusion layer 20 connected to the P ⁺ -type diffusion layer 16.

Next, as shown in FIG. 3C, the silicon oxide film 19 is selectively etched and removed, and N-type impurities are ion-implanted using the remaining silicon oxide film 19 and the polysilicon film 18 as a mask. Then, the N-type polysilicon gate electrode 6, the N ⁺ type source region 2 and the intrinsic polysilicon region 7 are formed.

Next, as shown in FIG. 3D, a silicon oxide film 3 is formed and patterned to form the silicon oxide film 3.
Using as a mask, P-type impurities are ion-implanted and pressed to form a P ⁺ -type diffusion layer 21.

Next, as shown in FIG. 3E, a drain electrode 22 is provided on the back surfaces of the source electrode 5 and the N type silicon substrate 14 which are connected to the N ⁺ type source region 2.

[0021]

As described above, the present invention reduces the effective area of the gate electrode by forming an intrinsic polysilicon region in the central portion of the conductive polysilicon gate electrode of the vertical field effect transistor (polysilicon film). 12 μm in total width and the intrinsic polysilicon region width 6 μm, the area of the polysilicon gate electrode is reduced by about 33%), and the insulating film above the intrinsic or non-doped polysilicon film is thickened (insulating film in other parts). 1.5 times, the capacitance between the polysilicon gate electrode and the source electrode is reduced by about 9%), which has the effect of reducing the capacitance of the gate electrode.

[Brief description of drawings]

FIG. 1 is a plan view and a sectional view taken along the line AA ′ showing an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing dimensions of each part of FIG.

3A to 3D are cross-sectional views showing the manufacturing process of one embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view showing a first example of a conventional vertical field effect transistor.

FIG. 5 is a sectional view showing a second example of a conventional vertical field effect transistor.

[Explanation of symbols]

1 Drain Region 2 Source Region 3, 15, 19 Silicon Oxide Film 4 Po Silicon Film 5 Source Electrode 6 Polysilicon Gate Electrode 7 Intrinsic Polysilicon Region 8 Lateral Spreading Width of Base Region 9 Polysilicon Gate Electrode Width 10 Polysilicon Film Full width 11 Width of intrinsic polysilicon region 12 Thickness of insulating film on intrinsic polysilicon region 13 Thickness of insulating film in other portion 14 N-type silicon substrate 16, 21 P ⁺ type diffusion layer 17 Gate oxide film 18 Intrinsic or Non-doped silicon film 20 P-type diffusion layer 22 Drain electrode 23 Base region

Claims (1)

[Claims] 1. A vertical field effect transistor having a gate electrode made of a conductive polysilicon film provided on a surface including a drain region and a source region via a gate insulating film, wherein the intrinsic field effect transistor provided at the central portion of the gate electrode. A vertical field-effect transistor comprising a polysilicon region and an insulating film thicker than the insulating film of the other portion provided on the intrinsic polysilicon region.