JPH06177350A - Manufacture of semiconductor memory - Google Patents

Abstract

PURPOSE:To increase the margin during the contact hole making step while lessening the contact resistance by decreasing the thickness of insulating layers formed in a peripheral circuit region. CONSTITUTION:Multiple word lines 5a-5d are formed with mutual intervals in a memory cell region. On the other hand, a polycrystalline silicon layer 7 is formed on the word lines 5a-5d through the intermediary of insulating layers 6a-6c. Besides, a silicon oxide film 8 covering this polycrystalline silicon layer 7 and extending over a peripheral circuit region is formed. Next, holes 10 are made to expose the partial surface of the polycrystalline silicon layer 7. Next, a resist layer 11 filling up these holes 10, covering the silicon oxide film 8 in the memory cell region and exposing the film 8 in the peripheral circuit region is formed. Finally, the silicon oxide film 8 formed in the peripheral circuit region is to be etched back using this resist layer 11 as a mask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device having a cylindrical storage node.

[0002]

2. Description of the Related Art Conventionally, there has been known a semiconductor memory device having a cylindrical storage node in which a storage node is formed so as to extend upward in order to increase the capacitance of a capacitor. Hereinafter, an example of a semiconductor memory device having such a cylindrical storage node will be given as a conventional example, and a manufacturing method thereof will be described with reference to FIGS.
20 to 40 are partial cross-sectional views showing respective manufacturing steps of a conventional semiconductor memory device.

First, referring to FIG. 20, in the memory cell region, impurity regions 103a, 103b, 103c and 103d are formed on the main surface of semiconductor substrate 101 at predetermined intervals.
Are formed. Impurity region 103c and impurity region 1
03d, the field oxide film 102 is formed. An impurity region 103b and an impurity region 103c are provided on a region between the impurity region 103a and the impurity region 103b.
On the region between the word line 1 and the word line 1 via the insulating layer 104.
05a and 105b are formed respectively.

Word line 105a and word line 105b
Are covered with an insulating layer 106a. Further, on the field oxide film 102, the word line 105c, the word line 105
d are formed at intervals. The word line 105c and the word line 105d are also covered with the insulating layer 106a. Bit line 13 is formed in impurity region 103b.
5 is electrically connected. This bit line 135 is
It is covered with an insulating layer 106b.

On the other hand, in the peripheral circuit region, field oxide film 102 is spaced apart from the main surface of semiconductor substrate 101.
Are formed. Impurity region 103e is formed on the main surface of semiconductor substrate 101 in the region sandwiched by field oxide film 102.

Next, referring to FIG. 21, an insulating film such as a silicon nitride film having a film thickness of about 0.1 μm is formed on the main surface of semiconductor substrate 101 in the state shown in FIG. 20 by the CVD method. The layer 106c is formed. A resist 136 is applied on the insulating layer 106c, and the resist 136 is patterned into a predetermined shape. Thereby, the impurity region 1
03a, impurity region 103c, and impurity region 10
The surface of the insulating layer 106c located above 3d is exposed.

Then, referring to FIG. 22, the insulating layer 106c is selectively removed by performing reactive ion etching using the resist 136 as a mask. Thereby, the impurity regions 103a, 103c, 10
Part of the surface of 3d is exposed. However, since anisotropic etching is used when performing the above-mentioned reactive ion etching, the insulating layer 106c remains on the side wall of the insulating layer 106a.

Next, referring to FIG. 23, the resist 136 is removed. Then, the polycrystalline silicon layer 107 is formed on the entire main surface of the semiconductor substrate 101 by using the CVD method. Next, referring to FIG. 24, the semiconductor substrate 101
A resist 137 is applied on the entire main surface. Then, by patterning this resist 137 into a predetermined shape, the resist 137 on the peripheral circuit region is removed.

Then, using the patterned resist 137 as a mask, the polycrystalline silicon layer 107 formed in the peripheral circuit region is removed by etching. As a result, the insulating layer 106c is exposed in the peripheral circuit region. This insulating layer 106c has a function as an etching stopper in a later step. By forming this insulating layer 106c, it becomes possible to prevent the impurity region 103e from being etched in a later step.

Referring to FIG. 25, after removing resist 137, silicon oxide film 108 having a thickness of about 1.1 μm is formed on the entire main surface of semiconductor substrate 101 by the CVD method. To form. Then, referring to FIG. 26, a resist 109 is applied on silicon oxide film 108. By patterning the resist 109 into a predetermined shape, the word lines 105a and the word lines 10 are
The resist 109 on the region between 5b and the region between the word line 105c and the word line 105d is removed.

The resist 1 patterned in this way
By performing reactive ion etching using 09 as a mask,
a silicon oxide film 108 located on the region between
The silicon oxide film 108 located on the region between the word line 105c and the word line 105d is selectively removed.
As a result, a hole 110 exposing a part of the surface of the polycrystalline silicon layer 107 is formed in the silicon oxide film 108.

Next, referring to FIG. 27, after removing the resist 109 described above, reactive ion etching is performed using the silicon oxide film 108 as a mask to form a polycrystal located at the bottom of the hole 110. Silicon layer 1
07 is removed. Thereby, the bottom conductive layer portion 107b of the storage node is formed. At this time, the insulating layer 106c acts as an etching stopper.

Next, referring to FIG. 28, the semiconductor substrate 10
1. A polycrystalline silicon layer 112 is formed on the entire main surface by a CVD method. Thereby, the silicon oxide film 10
8, the upper surface portion 108a, the side wall portion 108b, the insulating layer 10
A polycrystalline silicon layer 112 is formed on 6c and on the silicon oxide film 108 in the peripheral circuit region.
At this time, the silicon oxide film 1 of the polycrystalline silicon layer 112
The film thickness A on the upper surface 108a of 08 is smaller than the film thickness B of the polycrystalline silicon layer 112 formed at the bottom of the hole 110 located on the field oxide film 102.

Next, referring to FIG. 29, silicon oxide film 108 is formed by performing reactive ion etching.
The polycrystalline silicon layer 112 formed on the upper surface portion 108a and on the silicon oxide film 108 in the peripheral circuit region is removed. As a result, the polycrystalline silicon layer 1 is formed on the side wall portion 108b of the silicon oxide film 108 defining the hole 110.
12 remains. This portion becomes the sidewall conductive layer portion 107a of the storage node.

Here, referring again to FIG. 28, as described above, the thickness A of the polycrystalline silicon layer 112 on the upper surface portion 108a is equal to that of the hole 110 formed on the field oxide film 102.
Film thickness B of the polycrystalline silicon layer 112 formed at the bottom
It is smaller than. Therefore, the upper surface portion 1
Even if the reactive ion etching is performed until the polycrystalline silicon layer 112 on 08a is removed by etching, as shown in FIG. 29, field oxide film 102 is formed.
At the bottom of the upper hole 110, the polycrystalline silicon layer 11 is formed.
2 remains.

Next, referring to FIG. 30, further reactive ion etching is performed in order to remove the polycrystalline silicon layer 112 remaining at the bottom of the hole 110. As a result, the upper portion of the sidewall conductive layer portion 107a is etched, and the height of the sidewall conductive layer portion 107a becomes low.

To bring the capacitance of the capacitor to a predetermined value,
The height of the sidewall conductive layer portion 107a also needs to be a predetermined height. However, as described above, if the polycrystalline silicon layer 112 remains at the bottom of the hole 110, overetching must be performed to remove it.
As a result, the height of the sidewall conductive layer portion 107a is lowered to some extent as described above. Therefore, the height of the silicon oxide film 108 is increased in advance, that is, the silicon oxide film 1 is
The side wall conductive layer portion 107a having a desired height is obtained by forming a thick film 08. Therefore, the film thickness of the silicon oxide film 108 formed in the memory cell region and the peripheral circuit region is inevitably large.

Then, referring to FIG. 31, a resist 138 is applied on silicon oxide film 108, and resist 13 is applied.
By patterning 8, the resist 138 located on the memory cell region is removed. And FIG.
, The resist 138 is used as a mask to form the silicon oxide film 1 formed in the memory cell region.
08 is removed by etching. At this time, the insulating layer 106c
However, it functions as an etching stopper. The storage node 114 is formed through the above steps. Therefore, this storage node 114
Side wall conductive layer portion 107a and bottom conductive layer portion 107b
It will be composed of and.

Referring to FIG. 33, after removing resist 138, dielectric film 121 is formed on the entire main surface of semiconductor substrate 101 by the CVD method or the like. A polycrystalline silicon layer 115 is formed on this dielectric film 121 by the CVD method. This polycrystalline silicon layer 115 becomes the cell plate 115. By applying a resist 139 on the polycrystalline silicon layer 115 and patterning the resist 139 into a predetermined shape,
The resist 139 formed on the peripheral circuit region is removed. Then, using the patterned resist 139 as a mask, the polycrystalline silicon layer 115 and the dielectric film 121 formed on the peripheral circuit region are removed by etching. As a result, the cell plate 115 is formed as shown in FIG.

Next, after removing the resist 139, as shown in FIG. 35, an insulating layer 116 made of a silicon oxide film or the like having a film thickness of about 0.3 μm is formed on the entire main surface of the semiconductor substrate 101. Are formed by using the CVD method. Next, referring to FIG. 36, a resist 140 is applied on insulating layer 116. By patterning this resist 140 into a predetermined shape, an opening 141 is formed in a portion located on the impurity region 103e in the peripheral circuit region.
To form.

Using the patterned resist 140 as a mask, reactive ion etching is performed to form the insulating layer 11 formed in the peripheral circuit region.
6, the silicon oxide film 108 and the insulating layer 106c are sequentially removed by etching. Thereby, contact hole 118 exposing a part of the surface of impurity region 103e is formed. The side wall of this contact hole 118 is tapered.

Then, referring to FIG. 38, a tungsten (W) layer 122 is formed on insulating layer 116 by a CVD method so as to fill contact hole 118.
Then, as shown in FIG. 39, this tungsten layer 122 is etched back to leave the tungsten layer 122 in the contact hole 118. As a result, the tungsten plug 122 connected to the impurity region 103e is formed. After that, FIG.
As shown by 0, the aluminum wiring layer 120 is selectively formed on the insulating layer 116 located on the memory cell region and on the tungsten plug 122 formed in the peripheral circuit region.

[0023]

Although the conventional semiconductor memory device is formed through the above steps, the semiconductor memory device formed through this conventional step has the following problems. It was First, with reference to FIG. 36, the reason why the side wall of the contact hole 118 formed in the peripheral circuit region is tapered will be described. As described above, the contact layer 118 is filled with the tungsten layer 122 using the CVD method. However, the source gas is more difficult to be supplied to the lower part of the contact hole 118 than to the upper part thereof.

Therefore, tungsten is more likely to be deposited on the upper part of the side wall of the contact hole 118 than on the lower part of the side wall of the contact hole 118. for that reason,
For example, as shown in FIG. 37, the contact hole 1
When the contact hole 118 is formed so that the side wall of 18 does not have a tapered shape, the contact hole 118
A void 123 is formed in the tungsten layer 122 filled inside.
May be formed. In order to prevent such a situation, as shown in FIG. 36, the side wall of the contact hole 118 is tapered.

As described above, due to the tapered side wall of the contact hole 118, the following problems occur. Referring again to FIG. 36, as described above, the thickness of the insulating layer 106c is about 0.1 μm,
The thickness of the silicon oxide film 108 is about 1.1 μm, and the thickness of the insulating layer 116 is about 0.3 μm. Therefore, the depth of the contact hole 118 is about 1.5 μm.

At this time, the opening diameter of the opening 141 is set to about 0.
When the diameter is 4 μm and the inclination angle θ of the side wall of the contact hole 118 is 87 °, the diameter of the lower end of the contact hole 118 is about 0.24 μm. That is, by tapering the side wall of the contact hole 118, the possibility that voids will be generated in the tungsten plug 122 is significantly reduced, but the diameter at the lower end of the contact hole 118 is reduced. The smaller the diameter of the lower end of the contact hole 118, the smaller the impurity region 103e.
Since the contact area between the tungsten plug 122 and the tungsten plug 122 is small, the contact resistance is increased.

As a first means for increasing the diameter of the lower end of the contact hole 118, increasing the diameter of the opening 141 can be considered. However, increasing the diameter of the opening 141 is disadvantageous for miniaturization of the semiconductor memory device. Therefore, there is a limit to increasing the diameter of the opening 141.

As a second means for preventing the diameter of the lower end portion of the contact hole 118 from decreasing, referring to FIGS. 33 and 34, using the resist 139 as a mask, the polycrystalline silicon layer 115 in the peripheral circuit region, It is possible to reduce the film thickness of the silicon oxide film 108 in the peripheral circuit region by etching the silicon oxide film 108 continuously after removing the dielectric film 121 by etching.
However, this method has the following problems.

FIG. 41 shows the boundary between the memory cell region and the peripheral circuit region in the manufacturing process shown in FIG. Referring to FIG. 41, cell plate 115 is formed so as to ride on silicon oxide film 108 in the peripheral circuit region. The connection between the cell plate 115 and the upper wiring layer will be made at the portion on the silicon oxide film 108.

The silicon oxide film 10 is formed using the resist 139 formed on the cell plate 115 as a mask.
FIG. 42 shows a state in which the silicon oxide film 108 is reduced in thickness by etching No. 8 of FIG. Referring to FIG. 42, by etching the silicon oxide film 108, a step portion having a depth C is formed. Resist 139
FIG. 43 shows a state in which the insulating layer 116 is formed on the entire main surface of the semiconductor substrate 101 after removing the.

Since the step portion is formed in the silicon oxide film 108, even when the insulating layer 116 is formed so as to cover the step portion, the surface of the insulating layer 116 reflects the shape of the step portion. And the unevenness becomes severe. When the upper wiring layer is formed on the surface having such a large unevenness, there is a problem that the upper wiring layer is broken.

As a third means for preventing the diameter of the lower end portion of the contact hole 118 from decreasing, it is conceivable to deposit the silicon oxide film 108 thinly in advance. However, from the viewpoint of ensuring a predetermined capacitance of the capacitor, it is preferable that the silicon oxide film 108 is formed thick in advance as described above. Therefore, the silicon oxide film 10
It can be said that reducing the film thickness of 8 in advance is extremely disadvantageous in terms of ensuring the capacitance of the capacitor.

The present invention has been made to solve the above problems, and it is possible to reduce the contact resistance in the peripheral circuit region and increase the margin at the time of forming a contact hole. An object is to provide a method for manufacturing a semiconductor memory device.

[0034]

In a semiconductor memory device according to the present invention, a memory cell region in which a memory cell for storing information is formed and a peripheral circuit region for controlling the operation of the memory cell are provided on a semiconductor substrate. It is assumed to have it on the main surface. Then, in the method of manufacturing a semiconductor memory device according to the present invention, first, a plurality of word lines are formed in the memory cell region at intervals. A first conductive layer is formed on the word line with a first insulating layer interposed. A second insulating layer that covers the first conductive layer and extends into the peripheral circuit region is formed, and a hole that exposes a part of the surface of the first conductive layer is formed in the second insulating layer.

Then, a resist layer is formed to fill the holes and cover the second insulating layer in the memory cell region to expose the second insulating layer in the peripheral circuit region. By etching using this resist layer as a mask, the film thickness of the second insulating layer formed in the peripheral circuit region is reduced. Then, the first insulating film is formed on the side wall portion of the second insulating layer defining the hole.
A storage node is formed by forming a sidewall conductive layer connected to the conductive layer. A cell plate is formed on the storage node with a capacitor dielectric film interposed.

[0036]

According to the present invention, it is possible to reduce the film thickness of the second insulating layer formed in the peripheral circuit region without causing a step in the peripheral circuit region and ensuring a desired capacitor capacitance. Becomes As a result, the diameter of the lower end portion of the contact hole can be made larger than the conventional diameter without increasing the diameter of the upper end portion of the contact hole formed in the peripheral circuit region. This makes it possible to reduce the contact resistance.

[0037]

Embodiments of the method of manufacturing a semiconductor memory device according to the present invention will be described below with reference to FIGS. 1 to 11 are partial cross-sectional views sequentially showing respective steps of the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention. 12 to 19 are partial cross-sectional views sequentially showing each step of the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention.

First, referring to FIG. 1, field oxide film 2 is formed on the main surface of semiconductor substrate 1 through the same steps as in the prior art, and impurity regions 3a, 3b, 3c, 3d and 3e are formed.
Are formed respectively. Then, the impurity regions 3a to 3d
On the region sandwiched by the word line 5 with the insulating layer 4 interposed.
a and 5b are formed, and the word line 5 is formed on the field oxide film 2.
c and 5d are formed respectively. These word lines 5a, 5
An insulating layer 6a is formed so as to cover b, 5c and 5d.

Further, the bit line 35 is formed so as to be electrically connected to the impurity region 3b, and the insulating layer 6b is formed so as to cover the bit line 35. The insulating layer 6a,
An insulating layer 6c made of a silicon nitride film or the like is formed on 6b. The insulating layer 6c has a function as an etching stopper. A polycrystalline silicon layer 7 is formed on the insulating layer 6c by using the CVD method or the like.

On the other hand, in the peripheral circuit region, the impurity region 3e is formed in the region between the field oxide films 2. On this impurity region 3e and field oxide film 2
An insulating layer 6c is formed on top. CVD is performed on the insulating layer 6c and the polycrystalline silicon layer 7 in the peripheral circuit region.
Oxide film 8 having a predetermined film thickness D
Is formed. The thickness D of the silicon oxide film 8 is preferably about 1.1 μm.

Next, referring to FIG. 2, a resist 9 is applied on the silicon oxide film 8 and the resist 9 is patterned into a predetermined shape. As a result, the resist 9 formed on the position where the sidewall conductive layer portion of the storage node will be formed in a later step is removed. Using the patterned resist 9 as a mask,
The silicon oxide film 8 is etched. Thereby, a hole 10 exposing a part of the surface of the polycrystalline silicon layer 7 is formed.

Next, referring to FIG. 3, a resist 11 is applied on the entire main surface of the semiconductor substrate 1. Then, the resist 11 is patterned into a predetermined shape. Thereby,
A resist pattern is formed which fills the holes 10 and covers the memory cell region, exposing the surface of the silicon oxide film 8 formed in the peripheral circuit region. By using the resist 11 thus patterned as a mask, etching is performed to reduce the thickness of the silicon oxide film 8 formed in the peripheral circuit region.

At this time, the reduction amount D1 of the film thickness of the silicon oxide film 8 formed in the peripheral circuit region is preferably about 5000Å in this case. However, the height of the upper surface of the silicon oxide film 8 formed in the peripheral circuit region is adjusted to be substantially the same as the height of the uppermost portion of the sidewall conductive layer portion of the storage node formed in a later step. It is preferable. Therefore, the above value of D1 may be different from the above value depending on the height of the storage node formed in the memory cell region.

Next, referring to FIG. 4, the resist 1 described above is used.
After removing 1, the polycrystalline silicon layer 7 formed at the bottom of the hole 10 is removed by etching by using the silicon oxide film 8 as a mask.
At this time, the insulating layer 6c serves as an etching stopper. As a result, the bottom conductive layer portion 7b of the storage node is formed.

Next, referring to FIG. 5, a polycrystalline silicon layer 12 is formed on the entire main surface of semiconductor substrate 1 by the CVD method or the like. Thereby, the polycrystalline silicon layer 12 is formed on the bottom of the hole 10, the side wall 8b of the silicon oxide film 8 defining the hole 10, the upper surface 8a of the silicon oxide film 8 and the surface of the silicon oxide film 8 in the peripheral circuit region. Will be done. At this time, the film thickness B of the polycrystalline silicon layer 12 formed on the insulating layer 6c formed on the region between the word lines 5c and 5d is the same as the silicon oxide film 8
Of the polycrystalline silicon layer 12 formed on the upper surface portion 8a of the
Is larger than the film thickness A of

Next, referring to FIG. 6, reactive ion etching is performed to etch the polycrystalline silicon layer 12 described above, whereby the upper surface 8a of the silicon oxide film 8 and the silicon oxide film 8 in the peripheral circuit region are etched. The polycrystalline silicon layer 12 on the surface is removed. As a result, the polycrystalline silicon layer 12 remains on the side wall portion 8b of the silicon oxide film 8 defining the hole 10. However, as described above, the polycrystalline silicon layer 12 formed on the bottom portion 13 of the hole 10 formed on the region between the word lines 5c and 5d has a film thickness in the height direction of that portion. Is thicker than the other portions, and therefore remains at the bottom 13 of the hole 10.

Then, referring to FIG. 7, further reactive ion etching is performed to remove polycrystalline silicon layer 12 formed on bottom portion 13 of hole 10 described above. As a result, the upper portion of the polycrystalline silicon layer 12 formed on the side wall portion 8b of the silicon oxide film 8 is also etched and its height is reduced. As a result, sidewall conductive layer portion 7a of the storage node is formed. At this time, the height of the silicon oxide film 8 in the peripheral circuit area is adjusted so that the height of the sidewall conductive layer portion 7a and the height of the upper surface of the silicon oxide film 8 formed in the peripheral circuit area are substantially equal. It is preferable.

Next, referring to FIG. 8, a resist 24 is applied over the entire main surface of semiconductor substrate 1. This resist 2
By patterning 4 into a predetermined shape, a resist pattern that covers the peripheral circuit region and exposes the memory cell region is formed. Then, the patterned resist 24 is used as a mask to perform etching, whereby the silicon oxide film 8 formed in the memory cell region is etched.
To remove. As a result, the storage node 14 is formed. The storage node 14 is composed of a sidewall conductive layer portion 7a and a bottom conductive layer portion 7b. At this time, the insulating layer 6c serves as an etching stopper.

Next, referring to FIG. 9, the resist 2 described above is used.
After removing 4, the dielectric film 21 is formed on the storage node 14 by the CVD method or the like. The cell plate 15 is formed on the dielectric film 21 by the CVD method or the like. Then, an insulating layer 16 having a film thickness D2 is formed on the cell plate 15 and the silicon oxide film 8 in the peripheral circuit region. This insulating layer 16 is preferably a silicon oxide film, and the value of the film thickness D2 is preferably about 0.3 μm.

Next, referring to FIG. 10, resist 17 is applied on silicon oxide film 16. By patterning this resist 17 into a predetermined shape, an opening 17a is formed in the resist 17 on the peripheral circuit region. The insulating layer 16, the silicon oxide film 8, and the insulating layer 6c are sequentially etched by performing reactive ion etching using the resist 17 patterned in this way as a mask. Thereby, the contact hole 18 is formed. At this time, the etching conditions are selected so that the side wall of the contact hole 18 has a tapered shape. The value of the angle θ between the side wall of the contact hole 18 and the semiconductor substrate 1 is preferably about 87 °.

The value of the depth D3 of the contact hole 18 thus formed is about 1.0 μm. At this time, similarly to the conventional example, when the value of the diameter W of the opening of the contact hole 18 is set to about 0.4 μm, the value of the diameter W1 of the lower end of the contact hole 18 becomes about 0.3 μm. Therefore, the diameter can be made larger than the diameter (about 0.24 μm) of the lower end portion of the contact hole 118 formed by the conventional method. Thereby, the contact area between the impurity region 3e and the tungsten plug formed in a later step can be increased, and the contact resistance can be reduced.

Next, referring to FIG. 11, after the resist 17 is removed, a tungsten layer is formed on the insulating layer 16 and in the contact hole 18 by the CVD method or the like. By etching back this tungsten layer, a tungsten plug 19 is formed in the contact hole 18. After that, an aluminum layer is formed on the insulating layer 16 and the tungsten plug 19, and the aluminum layer is patterned into a predetermined shape to form the aluminum wiring layer 20.

A second embodiment of the method of manufacturing a semiconductor memory device according to the present invention will be described with reference to FIGS. First, referring to FIG. 12, a silicon oxide film 8 is formed on the main surface of semiconductor substrate 1 through the same steps as those in the first embodiment. At this time, the silicon film 8
The value of the film thickness D is the same as in the case of the first embodiment. Then, a polycrystalline silicon layer 30 is formed on the silicon oxide film 8 by using the CVD method or the like. The polycrystalline silicon layer 30 has a function as an antireflection film.

Next, referring to FIG. 13, a resist 31 is applied on this polycrystalline silicon layer 30. By patterning this resist 31 into a predetermined shape, the resist 31 on the region where the sidewall conductive layer portion of the storage node formed in a later step is formed is removed. Then, etching is performed using the patterned resist 31 as a mask to sequentially remove the polycrystalline silicon layer 30 and the silicon oxide film 8 by etching.

As a result, a hole 32 exposing a part of the surface of the polycrystalline silicon layer 7 is formed. The above resist 31
It is possible to prevent the patterning accuracy of the resist 31 from being deteriorated by the reflected light from the polycrystalline silicon layer 7 formed under the silicon oxide film 8 due to the presence of the polycrystalline silicon layer 30 when patterning It becomes possible to do.

Then, referring to FIG. 14, after removing resist 31, polycrystalline silicon layer 7 formed at the bottom of hole 32 is removed by etching. Thereby, the bottom conductive layer portion 7b of the storage node is formed. At this time, at the same time, the polycrystalline silicon layer 30 formed on the silicon oxide film 8 is also removed by etching. After that, a resist 33 is applied on the entire main surface of the semiconductor substrate 1, and the resist 33 is etched back. Thereby, the resist 33 is filled in the hole 32.

In FIG. 15, the resist 33 is provided in the hole 32.
FIG. 3 is a partial cross-sectional view showing a memory cell region, a boundary region, and a peripheral circuit region in a state of being filled. Referring to FIG. 15, by filling the resist 33 in the hole 32 as described above, the resist 33 is also filled in the concave portion in the boundary region existing between the memory cell region and the peripheral circuit region. Become. Note that the polycrystalline silicon layer 7c is locally left in the peripheral circuit region by the etching for forming the bottom conductive layer portion 7b of the storage node.

Next, referring to FIG. 16, after forming resist 33, resist 34 is further applied over the entire main surface of semiconductor substrate 1. Then, by patterning the resist 34, the surface of the silicon oxide film 8 formed in the peripheral circuit region is exposed. The states of the memory cell area, the boundary area, and the peripheral circuit area at this time are shown in FIG. Referring to FIG. 17, by filling the concave portion in the boundary region with resist 33 as described above, it becomes possible to provide a margin for patterning resist 34.

In the first embodiment described above, in the state shown in FIG. 17, that is, when the thickness of the silicon oxide film 8 in the peripheral circuit region is reduced, the field oxide film formed in the boundary region is formed. The polycrystalline silicon layer 7 remains on the upper surface 2. As a result, since this polycrystalline silicon layer 7 can be used as an etching stopper, it is possible to obtain a certain margin for resist patterning. However, in the second embodiment, when the polycrystalline silicon layer 7 formed at the bottom of the hole 32 is removed by etching, the polycrystalline silicon layer 7 formed in the recess in this boundary region is also removed by etching. I will end up.

As a result, the insulating layer 6 made of a nitride film or the like is formed.
c is exposed. Therefore, if the same patterning as that of the first embodiment is performed, the insulating layer 6c may be exposed. As a result, when the silicon oxide film 8 is etched back, it is conceivable that the insulating layer 6c will also be etched by the current etching technique. Therefore, this insulating layer 6c
By forming the resist 33 in advance so as to cover the above, it is possible to secure a margin when patterning the resist 34.

Resist 3 formed as described above
By etching using 3, 34 as a mask, the silicon oxide film 8 formed in the peripheral circuit region is etched back as shown in FIG. At this time, the reduction amount D4 of the thickness of the silicon oxide film 8 due to the etch back is preferably about 5000 Å. The height of the silicon oxide film 8 at this time is also adjusted to be substantially equal to the height of the side wall conductive layer portion of the storage node formed in a later step, as in the case of the first embodiment. Is preferred.

FIG. 19 shows the states of the memory cell region, the boundary region, and the peripheral circuit region when the silicon oxide film 8 formed in the peripheral circuit region is etched back using the resist 33 and the resist 34 described above. Has been done. Referring to FIG. 19, by performing the above-described etch back, the value of height D5 of silicon oxide film 8 in the peripheral circuit region from the main surface of semiconductor substrate 1 and the storage formed in the subsequent step. It is preferable that the height of the upper surface of silicon oxide film 8 is adjusted such that the height of the side wall conductive layer portion of the node from the main surface of semiconductor substrate 1 is substantially equal. After the silicon oxide film 8 in the peripheral circuit region is etched back as described above, the resist 33 and the resist 34 are removed, and the state shown in FIG. 11 is obtained through the same steps as those in the first embodiment. The semiconductor memory device will be formed.

[0063]

As described above, according to the present invention, it is possible to reduce the thickness of the second insulating layer formed in the peripheral circuit region. As a result, when the contact hole is formed in the second insulating layer, the contact hole has the same opening width as in the conventional case, so that the opening width at the lower end of the contact hole can be increased. This makes it possible to reduce the contact resistance. Further, it is possible to increase the margin in forming the contact hole in the peripheral circuit region as compared with the related art.

[Brief description of drawings]

FIG. 1 is a partial cross sectional view showing a sixth step of the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 2 is a partial cross sectional view showing a seventh step of the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a partial cross sectional view showing an eighth step of the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a partial cross sectional view showing a ninth step of the method for manufacturing the semiconductor memory device in the first embodiment according to the present invention.

FIG. 5 is a partial cross sectional view showing a tenth step of the method for manufacturing the semiconductor memory device in the first embodiment of the present invention.

FIG. 6 is a partial cross sectional view showing an eleventh step of the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 7 is a partial cross sectional view showing a twelfth step of the method for manufacturing the semiconductor memory device in the first embodiment of the present invention.

FIG. 8 is a partial cross sectional view showing a thirteenth step of the method for manufacturing the semiconductor memory device in the first embodiment of the present invention.

FIG. 9 is a partial cross sectional view showing a fourteenth step of the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 10 is a partial cross sectional view showing a fifteenth step of the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 11 is a partial cross sectional view showing a sixteenth step of the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 12 is a partial cross sectional view showing a sixth step of the method for manufacturing the semiconductor memory device in the second embodiment according to the present invention.

FIG. 13 is a partial cross sectional view showing a seventh step of the method for manufacturing the semiconductor memory device in the second embodiment according to the present invention.

FIG. 14 is a partial cross sectional view showing an eighth step of the method for manufacturing the semiconductor memory device according to the second embodiment of the present invention.

FIG. 15 is a partial cross sectional view showing a memory cell region, a boundary region, and a peripheral circuit region in an eighth step of the method for manufacturing a semiconductor memory device according to the second embodiment of the present invention.

FIG. 16 is a partial cross sectional view showing a ninth step of the method for manufacturing the semiconductor memory device in the second embodiment according to the present invention.

FIG. 17 is a partial cross sectional view showing a memory cell region, a boundary region, and a peripheral circuit region in a ninth step of the method for manufacturing a semiconductor memory device according to the second embodiment of the present invention.

FIG. 18 is a partial cross sectional view showing a tenth step of the method for manufacturing the semiconductor memory device in the second embodiment according to the present invention.

FIG. 19 is a partial cross sectional view showing a memory cell region, a boundary region, and a peripheral circuit region in a tenth step of the method for manufacturing a semiconductor memory device according to the second embodiment of the present invention.

FIG. 20 is a partial cross-sectional view showing a first step of a method for manufacturing a conventional semiconductor memory device.

FIG. 21 is a partial cross-sectional view showing a second step of the conventional method for manufacturing a semiconductor memory device.

FIG. 22 is a partial cross-sectional view showing a third step of the conventional method for manufacturing a semiconductor memory device.

FIG. 23 is a partial cross-sectional view showing a fourth step of the conventional method for manufacturing a semiconductor memory device.

FIG. 24 is a partial cross-sectional view showing a fifth step of the conventional method for manufacturing a semiconductor memory device.

FIG. 25 is a partial cross-sectional view showing a sixth step of the conventional method for manufacturing a semiconductor memory device.

FIG. 26 is a partial cross-sectional view showing a seventh step of the conventional method for manufacturing a semiconductor memory device.

FIG. 27 is a partial cross-sectional view showing an eighth step of the conventional method for manufacturing a semiconductor memory device.

FIG. 28 is a partial cross-sectional view showing a ninth step of the conventional method for manufacturing a semiconductor memory device.

FIG. 29 is a partial cross sectional view showing a tenth step of the method for manufacturing the conventional semiconductor memory device.

FIG. 30 is a partial cross sectional view showing an eleventh step of the conventional method for manufacturing a semiconductor memory device.

FIG. 31 is a partial cross sectional view showing a twelfth step of the method for manufacturing the conventional semiconductor memory device.

FIG. 32 is a partial cross sectional view showing a thirteenth step of the conventional method for manufacturing a semiconductor memory device.

FIG. 33 is a partial cross sectional view showing a fourteenth step of the method for manufacturing the conventional semiconductor memory device.

FIG. 34 is a partial cross sectional view showing a fifteenth step of the method for manufacturing the conventional semiconductor memory device.

FIG. 35 is a partial cross sectional view showing a sixteenth step of the conventional method for manufacturing a semiconductor memory device.

FIG. 36 is a partial cross sectional view showing a seventeenth step of the conventional method for manufacturing a semiconductor memory device.

FIG. 37 is a schematic diagram showing a state where voids are generated in the conductive layer filled in the contact hole when the side wall of the contact hole in the peripheral circuit region is not tapered.

FIG. 38 is a partial cross sectional view showing the eighteenth step of the method for manufacturing the conventional semiconductor memory device.

FIG. 39 is a partial cross sectional view showing a nineteenth step of the method for manufacturing the conventional semiconductor memory device.

FIG. 40 is a partial cross sectional view showing a twentieth step of the method for manufacturing the conventional semiconductor memory device.

41 is a cross-sectional view showing a first step when etching silicon oxide film to reduce the thickness of silicon oxide film. FIG.

FIG. 42 is a cross-sectional view showing a second step in the case of etching silicon oxide film to reduce the thickness of silicon oxide film.

FIG. 43 is a cross-sectional view showing a third step when etching silicon oxide film to reduce the thickness of silicon oxide film.

[Explanation of symbols]

1, 101 semiconductor substrate 5a, 5b, 5c, 5d, 105a, 105b, 105
c, 105d Word line 6a, 6b, 6c, 106a, 106b, 106c Insulation layer 7,107 Polycrystalline silicon layer 8,108 Silicon oxide film 7a, 107a Side wall conductive layer portion 7b, 107b Bottom conductive layer portion 14,114 Storage node 15,115 Cell plate 18,118 Contact hole 30,34 Polycrystalline silicon layer

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor memory device having a memory cell region in which a memory cell for storing information is formed, and a peripheral circuit region for controlling the operation of the memory cell on a main surface of a semiconductor substrate. Forming a plurality of word lines spaced apart from each other in the memory cell region; forming a first conductive layer on the word lines with a first insulating layer interposed therebetween; Forming a second insulating layer that covers the conductive layer and extends into the peripheral circuit region; and forming a hole in the second insulating layer to expose a part of the surface of the first conductive layer. Forming a resist layer filling the holes, covering the second insulating layer in the memory cell region and exposing the second insulating layer in the peripheral circuit region, and using the resist layer as a mask To etching Therefore, the step of reducing the film thickness of the second insulating layer formed in the peripheral circuit region, and the first side wall portion of the second insulating layer defining the hole,
A semiconductor memory device comprising: a step of forming a storage node by forming a sidewall conductive layer connected to a conductive layer; and a step of forming a cell plate with a capacitor dielectric film interposed on the storage node. Production method.