JPH06177150A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE:To make uniform the side wall between a gate electrode and source- drain regions on the opposite sides thereof by making a contact hole on a conductor layer. CONSTITUTION:A conductor layer 17a is provided contacting with source-drain regions 15a, 15b and the side wall 16a of a gate electrode 13 contiguous thereto. Consequently, when a contact hole 18a is made through the side wall 16a of an interlayer insulation film 18 covering them, the contact hole 18a is made above the conductor layer 17a even if the gate electrode 13 is approached due to misalignment. In this regard, thickness of the side wall 16a between the gate electrode 13 and the conductor layer 17a is kept intact. This method ensures uniform thickness of a side wall 16a formed between the gate electrode 13 and the source-drain electrode 19 formed in the contact hole 18a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a gate electrode of an insulated gate field effect transistor and an interlayer insulating film on S / D region layers on both sides of the gate electrode. And a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices have been required to have high density, and it is necessary to miniaturize patterns. As one means for achieving this, miniaturization of insulated gate field effect transistors has been attempted.

6 (a) to 6 (d), 7 (a) and 7 (b)
Is the gate electrode of the insulated gate field effect transistor,
FIG. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor device having a contact hole formed in an interlayer insulating film on the S / D region layer on both sides of the gate electrode. As an example of the insulated gate field effect transistor, one having a floating gate as an EPROM cell is used.

First, FIG. 6A shows a state after a gate electrode having a floating gate and a control gate and a source / drain region layer are formed on a semiconductor substrate on both sides of the gate electrode. Is a semiconductor substrate, 2
Is a gate insulating film on the semiconductor substrate 1, 3 is a gate insulating film 2
A gate electrode having a floating gate 3a / insulating film 3b / control gate 3c thereon, 4 is a gate electrode 3
The insulating films 5a and 5b on a are the source / drain region layers (S / D) formed on the semiconductor substrate 1 on both sides of the gate electrode 3.
Area layer).

In this state, first, as shown in FIG. 6B, the insulating film 6 is formed by covering the gate electrode 3 to form the side wall. Next, the insulating film 6 is anisotropically etched to form a sidewall 6a made of the insulating film 6 on the side wall of the gate electrode 3 (FIG. 6C).

Next, an interlayer insulating film 7 is formed on the entire surface (FIG. 6 (d)). Then, the interlayer insulating film 7 on the S / D region layer 5b is selectively etched and removed to form a contact hole 7a in the interlayer insulating film 7 on the S / D region layer 5b (FIG. 7A).

Next, after forming a conductor film, patterning is performed, and the S / D region layer 5b is formed through the contact hole 7a.
The S / D electrode or the wiring layer 8 connected to is formed (FIG. 7).
(B)). Then, an insulated gate field effect transistor is completed through a predetermined process.

[0008]

However, according to the method of manufacturing a semiconductor device of the above-mentioned conventional example, in order to miniaturize the element, the S / D region layers 5a and 5b are made small, and the contact hole 7a is made as small as possible. It is necessary to bring it close to the gate electrode 3. Therefore, if misalignment occurs during patterning for forming the contact holes, the pattern shown in FIG.
As shown in FIG. 3, the side wall 6a may be etched to form the contact hole 7b.

Therefore, the S / D is formed in the contact hole 7b.
When the electrode or the wiring layer is formed, the insulating film thickness between the gate electrode and the S / D electrode or the wiring layer varies, the parasitic capacitance varies, or the accumulated charge leaks and the accumulated charge varies. There is.

The present invention was created in view of the problems of the conventional example, and the film thickness of the sidewall between the gate electrode and the S / D electrode or the wiring layer is achieved while the device is miniaturized. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of ensuring the uniformity of the above.

[0011]

The above-mentioned problems are as follows. First, a semiconductor substrate, a gate insulating film on the semiconductor substrate, a gate electrode on the gate insulating film, and semiconductor substrates on both sides of the gate electrode. Of the formed source / drain region layer, the side wall made of the first insulating film formed on the side wall of the gate electrode, and the gate electrode adjacent to the source / drain region layer in the region where the contact hole is to be formed. A conductor film in contact with the sidewall and in contact with the source / drain region layer, a second insulating film covering the gate electrode, the sidewall and the conductor film, and the conductor film. A semiconductor device having a contact hole formed in a second insulating film on the source / drain region layer adjacent to the gate electrode, and secondly, The first electrode is formed by forming a floating gate on the gate insulating film, a third insulating film on the floating gate, and a control gate on the third insulating film. Thirdly, the first or second aspect is achieved by the semiconductor device according to the third aspect, wherein the conductor film is a polysilicon film.
Which is achieved by the semiconductor device according to the invention, and fourthly,
A gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film; source / drain region layers formed on the semiconductor substrate on both sides of the gate electrode; and a fourth sidewall formed on the sidewall of the gate electrode. And a fifth insulating film formed on the gate electrode, and a step of forming a conductive film on the entire surface and anisotropically etching the conductive film. Then, patterning is performed on the source / region of the region where the contact hole is to be formed.
Covering the gate electrode, the sidewalls, and the conductor film with the step of leaving the conductor film in contact with the sidewall of the gate electrode adjacent to the drain region layer and in contact with the source / drain region layer Forming a sixth insulating film, and patterning the sixth insulating film to form the contact hole on the source / drain region layer adjacent to the gate electrode on which the conductor film is formed. And a method for manufacturing a semiconductor device having a process.

[0012]

According to the semiconductor device and the method of manufacturing the same of the present invention, the conductor which is in contact with the sidewall of the gate electrode adjacent to the source / drain region layer in the region where the contact hole is to be formed and which is in contact with the source / drain region layer. Since it has a film, the second insulating film or the sixth
When the contact hole is formed in the insulating film, even if the position shifts to approach the gate electrode, the contact hole is formed on the conductor film. in this case,
Since the film thickness of the sidewall between the gate electrode and the conductor film remains unchanged at the initial stage, the uniformity of the film thickness of the insulating film between the source / drain electrode formed in the contact hole and the gate electrode is ensured. be able to.

[0013]

Embodiments of the present invention will now be described with reference to the drawings. 1 (a)-(d) and 2 (a)-
FIG. 3D is a sectional view illustrating a method for manufacturing a semiconductor device having a gate electrode of an insulated gate field effect transistor and a contact hole formed in an interlayer insulating film on the S / D region layer on both sides of the gate electrode; FIG. 3 is a plan view for explaining the method for manufacturing the semiconductor device, and the sectional view taken along the line AA of FIG. 3 corresponds to the sectional views of FIGS. . In addition, FIG. 4 shows FIGS. 1 (a) to 1 (d) and FIG.
It is a circuit block diagram containing the transistor shown to sectional drawing of (a)-(d). As an example of the insulated gate field effect transistor, one having a floating gate as an EPROM cell is used.

First, FIG. 1A shows a state after a source / drain region layer is formed on a gate electrode having a floating gate and a control gate, and a semiconductor substrate on both sides of the gate electrode. Is a semiconductor substrate made of silicon, 12 is a gate insulating film made of a silicon oxide film on the semiconductor substrate 11, 13 is a gate electrode on the gate insulating film 12, and a floating gate 13a made of a polysilicon film / an insulating film made of a silicon oxide film. A control gate 13c composed of the film 13b / polysilicon film is formed. 14 is an insulating film on the gate electrode 13, 15a, 15
Reference numeral b is a source / drain region layer (S / D region layer) formed on the semiconductor substrate 11 on both sides of the gate electrode 13. The control gate 13c is connected to the word line.

In such a state, first, as shown in FIG. 1B, an insulating film 16 made of a silicon oxide film having a film thickness of about 3000 Å is formed so as to cover the gate electrode 13 to form a sidewall. To do.

Next, reactive ion etching using a fluorine-based gas such as HF (hereinafter referred to as RIE).
Thus, the insulating film 16 is anisotropically etched to form a side wall 16a made of the insulating film 16 on the side wall of the gate electrode 13 (FIG. 1C).

Next, a polysilicon film (conductor film) is formed on the entire surface.
After forming 17 (FIG. 1D), the polysilicon film 17 is anisotropically etched by RIE using a chlorine-based gas to adjoin the S / D region layer 15b in the region where the contact hole 18a is to be formed. Side wall 16 of gate electrode 13
The polysilicon film 17a remains so as to be in contact with a and to be in contact with the S / D region layers 15a and 15b (FIG. 2A). In addition,
Polysilicon film 17 on all sidewalls by anisotropic etching
Since a remains, in order to prevent electrical short-circuit with other regions, the polysilicon film 17a is further patterned after this step if necessary, and S / of the region where the contact hole 18a is to be formed. The polysilicon film 17b must be left only in the region adjacent to the D region layer 15b (FIG. 3).

Next, an interlayer insulating film 18 is formed on the entire surface (FIG. 2B). Then, the interlayer insulating film 18 on the S / D region layer 15b is selectively etched and removed to remove the S / D region layer.
A contact hole 18a is formed in the interlayer insulating film 18 on 15b (FIG. 2C).

Next, after forming an aluminum film, patterning is performed to form an S / D electrode or wiring layer 19 connected to the S / D region layer 15b through the contact hole 18a (FIG. 2 (d)). After that, a semiconductor device including an insulated gate field effect transistor is completed through predetermined steps (FIG. 4). In FIG. 4, reference numeral 21 denotes a source line, which connects sources of desired transistors. Two
Reference numeral 2 is a word line, which is connected to the control gate electrode 13c. A bit line 23 is connected to the drain of each transistor. A row decoder 24 sends an address signal to the control gate 13c of a desired transistor via each word line 22, and a column decoder 25 sends an address signal to the drain of a desired transistor via each bit line 23.

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, the sidewall 16a of the gate electrode 13 adjacent to the S / D region layer 15b in the region where the contact hole 18a is to be formed is formed. Contact and S / D area layer
Since the polysilicon film 17a which is in contact with 15b is formed,
A contact hole 18 is formed in the interlayer insulating film 18 covering them.
When forming a, as shown in FIG. 5, even if the alignment is shifted to approach the gate electrode, the polysilicon film 17a
The contact hole 18b will be formed thereover. In this case, since the film thickness of the sidewall 16a between the gate electrode 13 and the polysilicon film 17a remains unchanged at the initial state, the S / D electrode or wiring layer 19 formed by filling the contact hole 18b and the gate electrode 13 are formed. It is possible to secure the uniformity of the film thickness of the insulating film between and.

This makes it possible to prevent the parasitic capacitance from varying and the accumulated charges from leaking to cause the accumulated charges to vary. Although the polysilicon film 17a is used as the conductor film in the embodiment, another conductor film such as a refractory metal film may be used.

The floating gate 13a / insulating film
The present invention is applied to an insulated gate field effect transistor having a gate electrode 13 formed with 13b / control gate 13c, but an insulated gate type having an ordinary gate electrode formed with only one layer of gate. The present invention can be applied to a field effect transistor.

[0023]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, the source / drain region adjacent to the source / drain region layer in the region where the contact hole is to be formed is in contact with the source / drain region and the source / drain region is formed. Since it has a conductor film in contact with the drain region layer, even when the contact hole is formed on the conductor film when the contact hole is formed in the interlayer insulating film that covers the drain region layer even if the contact hole is misaligned and approaches the gate electrode. Will be formed. in this case,
Since the film thickness of the sidewall between the gate electrode and the conductor film remains unchanged from the initial state, the film thickness of the insulating film between the source / drain electrode or the wiring layer and the gate electrode formed by filling the contact hole is uniform. It is possible to secure the property, and it is possible to prevent the parasitic capacitance from varying and the accumulated charges from leaking to cause the accumulated charges to vary.

[Brief description of drawings]

FIG. 1 is a cross-sectional view (1) for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view (No. 2) explaining the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 3 is a plan view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 4 is a circuit configuration diagram of a semiconductor device according to an exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating the operation and effect of the method for manufacturing a semiconductor device according to the embodiment of the invention.

FIG. 6 is a sectional view (No. 1) for explaining a method for manufacturing a semiconductor device according to a conventional example.

FIG. 7 is a cross-sectional view (2) explaining the method for manufacturing a semiconductor device according to the conventional example.

FIG. 8 is a cross-sectional view illustrating a problem with a conventional example.

[Explanation of symbols]

 11 semiconductor substrate, 12 gate insulating film, 13 gate electrode, 13a floating gate, 13b, 14, 16 insulating film, 13c control gate, 15a, 15b S / D region layer, 16a sidewall, 17, 17a, 17b polysilicon film (Conductor film), 18 interlayer insulating film, 18a, 18b contact hole, 19 S / D electrode or wiring layer, 20 resist mask, 21 source line, 22 word line, 23 bit line, 24 row decoder, 25 column decoder.

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display location H01L 27/115 29/788 29/792 H01L 29/78 371

Claims (4)

[Claims] 1. A semiconductor substrate, a gate insulating film on the semiconductor substrate, a gate electrode on the gate insulating film, source / drain region layers formed on the semiconductor substrate on both sides of the gate electrode, and the gate. A side wall made of a first insulating film formed on a side wall of the electrode and in contact with a side wall of a gate electrode adjacent to the source / drain region layer in a region where a contact hole is to be formed, and the source / drain region layer On the source / drain region layer adjacent to the gate electrode on which the conductor film is formed, the second insulating film covering the gate electrode, the sidewall and the conductor film, and the gate electrode on which the conductor film is formed. A semiconductor device having the contact hole formed in the second insulating film of. 2. The gate electrode comprises a floating gate on the gate insulating film, a third insulating film on the floating gate, and a control gate on the third insulating film. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein the conductor film is a polysilicon film. 4. A gate insulating film on a semiconductor substrate, a gate electrode on the gate insulating film, source / drain region layers formed on the semiconductor substrate on both sides of the gate electrode, and a sidewall of the gate electrode. The formed side wall of the fourth insulating film and the fifth side wall formed on the gate electrode.
A conductive film is formed on the entire surface of the source / drain region layer in a region where a contact hole is to be formed by anisotropically etching the conductive film and then patterning the conductive film. A step of leaving the conductor film in contact with the sidewall of the gate electrode adjacent to the gate electrode and in contact with the source / drain region layer; and a step of covering the gate electrode, the sidewall and the conductor film. And a step of patterning the sixth insulating film to form the contact hole on the source / drain region layer adjacent to the gate electrode on which the conductor film is formed. Method for manufacturing semiconductor device having the same.