JPH06176570A - Dynamic random access memory - Google Patents

Abstract

PURPOSE:To unnecessitate a boosting circuit, to decrease an occupancy area and to reduce power consumption by directly supplying a high reference voltage from a power source in a DRAM driven by a reference voltage lower than a power source voltage and making the high reference voltage a writing voltage. CONSTITUTION:A DRAM formed of a DRAM circuit 1 and a logical integrated circuit 2 is driven by a decreased reference voltage Vdd=1.5V by means of the voltage Vcc=3.3V of a power source 4 through a power source voltage converter circuit 3 and its logical amplitude becomes 0-1.5V. Since the threshold voltage of a transistor is 0.5V, a difference between Vcc and Vdd is about 1.8V and writing to the DRAM cell is executed with Vcc as a high reference voltage without boosting, the voltage Vcc is directly supplied as the writing voltage. Consequently, the boosting circuit is not required, the occupancy area and power consumption are reduced and the adverse effect of noise caused by the boosting circuit does not affect the memory.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to memory integrated circuits,
In particular, the present invention relates to a dynamic random access memory suitable for mounting on an ASIC.

[0002]

2. Description of the Related Art Conventionally, a dynamic random access memory (hereinafter referred to as a DRAM in this embodiment) can be driven by a reference voltage Vdd lower than the power supply voltage Vcc as it is. Things are known. According to this DRAM, power consumption can be reduced, but when the memory cell is an NMOS type at this time, a voltage higher than Vdd by a threshold voltage Vth is written to the gate electrode of this NMOS access transistor. It is necessary to apply to the gate as a voltage for.
Therefore, conventionally, a booster circuit for boosting the reference voltage Vdd has been incorporated in the DRAM.

However, the booster circuit for generating a voltage higher than the reference voltage Vdd has a tendency to increase the chip area and power consumption by this circuit. Further, the booster circuit as described above needs to be stable in order to secure high reliability both in terms of circuit and process in view of its application, and its management is complicated. Even when a PMOS type memory cell is used, the same problem as described above occurs when low-level writing is performed.

On the other hand, with the progress of miniaturization of integrated circuit processes, a small signal amplitude interface for driving a large-capacity load at high speed has been considered promising in recent years. The booster circuit described above may be a source of noise for the small signal amplitude interface, which is a problem in a small signal amplitude system that requires strict specifications for noise margin.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the problems of the prior art as described above, and its main purpose is to reduce the chip area and power consumption, and to further reduce the small signal. An object is to provide a dynamic random access memory capable of reducing noise in a system using an amplitude interface.

[0006]

According to the present invention, the above objects are driven by a reference voltage lower than the power supply voltage generated in the power supply voltage conversion circuit, and writing is performed by a voltage higher than the reference voltage. It is achieved by providing a dynamic random access memory characterized in that a voltage higher than the reference voltage is directly supplied from a power supply.

[0007]

As described above, the booster circuit can be omitted by directly using the external power supply voltage for writing.
The area required for the circuit configuration and the power consumption used for the circuit can be eliminated. Furthermore, even when this memory is used in a system to which an interface of small signal amplitude is connected, there is no concern that noise will occur due to the booster circuit.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a memory / logic embedded type integrated circuit using a DRAM to which the present invention is applied. In the circuit of this embodiment, the DRAM circuit 1
The logic integrated circuit 2 and the logic integrated circuit 2 are mounted together to form an ASIC circuit. In both of these circuits 1 and 2, a reference voltage Vdd is supplied from a power supply 4 through a power supply voltage conversion circuit (step-down circuit) 3.
(1.5V) is supplied. The substrate bias Vbb is supplied from the substrate bias generating circuit 5 to both the circuits 1 and 2. Further, the power supply 4 also supplies power to the level conversion circuit 6 and the small signal amplitude interface 7.

The DRAM circuit 1 and the logic integrated circuit 2 are designed to exchange signals with an external circuit via the level conversion circuit 6 and the small signal amplitude interface 7. Here, the power supply 4 directly supplies the power supply voltage Vcc (3.3 V) to the DRAM circuit 1 and the logic integrated circuit 2. Reference numeral 8 is a ground terminal, and each circuit 1 to
3, 5-7.

The memory cell 11 of the DRAM circuit 1 is shown in FIG.
Enlarged to show. This memory cell 11 is composed of an NMOS transistor 12 and a capacitor 13,
The reference voltage Vdd is selectively supplied to the bit line (BL) connected to the drain of the transistor 12, and the power supply voltage Vdd is supplied to the word line (WL) connected to the gate.
cc is selectively supplied.

The DRAM circuit 1 and the logic integrated circuit 2 are driven by the reference voltage Vdd.
Its logical amplitude is 0 to 1.5V. Further, since the threshold voltage of the NMOS transistor is around 0.5V and the difference between the power supply voltage Vcc and the reference voltage Vdd is about 1.8V, the power supply voltage Vcc is sufficient even if it is not the voltage obtained by boosting the reference voltage Vdd. Information can be written in the memory cell 12.

The data is transferred between the DRAM circuit 1 and the logic integrated circuit 2 at the reference voltage Vdd, and the level between the both circuits 1 and 2 and the small signal amplitude interface 7 is changed. Vdd and Vcc by the conversion circuit 6
Data is exchanged by performing level conversion between and.

Needless to say, the present invention is not limited to the above-mentioned embodiment and various applications are possible. For example, in this embodiment, a DRAM circuit and a logic integrated circuit are mixedly mounted. Although the ASIC circuit has been described, it goes without saying that a similar structure is possible even if the ASIC circuit is composed only of a DRAM circuit and its peripheral circuits and a logic integrated circuit is arranged outside.

[0015]

As is apparent from the above description, the memory integrated circuit according to the present invention requires a reference voltage lower than the power supply voltage for driving and a voltage higher than this reference voltage for writing. In the DRAM
By directly supplying a voltage higher than the reference voltage from the power supply, a separate booster circuit is not required, the chip area and the power consumption required for the booster circuit can be eliminated, and a small signal amplitude Even when a DRAM is used in the system, there is no concern that noise generated from the booster circuit will act on the small signal amplitude interface.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an ASIC circuit to which the present invention is applied.

FIG. 2 is a circuit diagram showing a main part of FIG.

[Explanation of symbols]

 1 DRAM circuit 2 Logic integrated circuit 3 Power supply voltage conversion circuit 4 Power supply 5 Substrate bias generation circuit 6 Level conversion circuit 7 Small signal amplitude interface 8 Ground terminal 11 Memory cell 12 NMOS transistor 13 Capacitor

Claims (2)

[Claims] 1. A dynamic random access memory which is driven by a reference voltage lower than a power supply voltage generated by a power supply voltage conversion circuit and which is written with a voltage higher than the reference voltage, wherein the dynamic random access memory is higher than the reference voltage. A dynamic random access memory characterized in that a high voltage is directly supplied from a power supply. 2. A level conversion circuit and a small signal amplitude interface provided to match the logic level of the output signal with the logic level of the external logic circuit and shift the signal voltage to the power supply voltage. The dynamic random access memory according to claim 1.