KR960009959B1 - Connecting method of dram cell - Google Patents

Connecting method of dram cell Download PDF

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Publication number
KR960009959B1
KR960009959B1 KR1019940004734A KR19940004734A KR960009959B1 KR 960009959 B1 KR960009959 B1 KR 960009959B1 KR 1019940004734 A KR1019940004734 A KR 1019940004734A KR 19940004734 A KR19940004734 A KR 19940004734A KR 960009959 B1 KR960009959 B1 KR 960009959B1
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South Korea
Prior art keywords
bit
cell
bit line
node
transfer transistor
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KR1019940004734A
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Korean (ko)
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최재명
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현대전자산업 주식회사
김주용
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Priority to KR1019940004734A priority Critical patent/KR960009959B1/en
Priority to GB9504936A priority patent/GB2287560A/en
Priority to DE1995108736 priority patent/DE19508736A1/en
Priority to JP7052407A priority patent/JPH0855474A/en
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Publication of KR960009959B1 publication Critical patent/KR960009959B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits

Abstract

one node of a first cell capacitor, where the source of a transfer transistor is connected to the first bit line, to the drain of the transfer transistor of the first cell, and the other node to a second bit line(/BIT); one node of the second cell capacitor, where the source of the transfer transistor is connected to the second bit line(/BIT), to the drain of the transfer transistor of the second cell, and the other node to the first bit line(BIT).

Description

디램 셀 접속방법How to connect DRAM cell

제1도는 종래의 셀과 증폭기의 연결 상태를 도시한 회로도.1 is a circuit diagram showing a connection state of a conventional cell and an amplifier.

제2도는 본 발명의 셀과 감지 증폭기의 연결 상태를 도시한 회로도.2 is a circuit diagram showing a connection state of a cell and a sense amplifier of the present invention.

제3도는 제2도에 관련된 신호의 출력 파형도.3 is an output waveform diagram of a signal related to FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 제1셀12 : 제2셀11: first cell 12: second cell

본 발명은 디램(DRAM : Dyanmic Random Access Memory)소자의 셀(cell)접속방법에 관한 것으로 특히, 셀의 캐패시터(capacitor) 양단을 한쪽은 셀의 전달 트랜지스터에 연결시키고 다른쪽은 셀의 전달 트랜지스터가 연결되어 있지 않은 인접한 다른 데이타선에 연결하여 데이타 센싱 마진(sensing margin)과 센싱 속도를 향사시킨 셀 접속 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell connection method of DRAM (DRAM) devices. The present invention relates to a cell access method in which data sensing margins and sensing speeds are improved by connecting to adjacent non-connected data lines.

일반적인 셀은 제1도에 도시된 바와 같이 하나의 전달 트랜지스터와 하나의 캐패시터로 이루어지는데, 비트선(BIT)와 비트선(/BIT)에 연결된 셀을 보면 전달 트랜지스터를 통해 캐패시터와 연결되고 캐패시터의 한쪽 노드는 일정전위를 갖는 기판전위(Vcp)에 연결된다.A typical cell consists of one transfer transistor and one capacitor, as shown in FIG. 1. In a cell connected to a bit line (BIT) and a bit line (/ BIT), a cell is connected to a capacitor through a transfer transistor and is connected to a capacitor. One node is connected to the substrate potential Vcp having a constant potential.

그러나, 상기 기판전위(Vcp)는 모든셀의 캐패시터에 공통으로 연결되어 있으므로, 기판전위(Vcp)를 일정한 전위로 유지시키기 위해서는 큰 구동회로가 필요하고, 캐패시터에 저장되어 있던 데이타가 비트선에 전달될 때에는 기판전위(Vcp)의 레벨이 흔들려서 비트선의 전위에 영향을 미치므로 데이타 센싱 마진이 감소하는 문제가 발생한다.However, since the substrate potential Vcp is commonly connected to the capacitors of all the cells, a large driving circuit is required to maintain the substrate potential Vcp at a constant potential, and data stored in the capacitor is transferred to the bit line. In this case, the level of the substrate potential Vcp is shaken, which affects the potential of the bit line, thereby reducing the data sensing margin.

따라서, 본 발명에서는 기판전위(Vcp)에 접속되는 셀 캐패시터의 한쪽 노드를 인접하는 다른 비트선에 접속시킴으로써, 종래에 비해 개선된 데이타 센싱 마진과 센싱 속도를 얻도록 하는데에 그 목적이 있다.Accordingly, an object of the present invention is to obtain an improved data sensing margin and sensing speed compared with the related art by connecting one node of a cell capacitor connected to the substrate potential Vcp to another adjacent bit line.

즉, 하나의 셀을 살펴보면 전달 트랜지스터의 소오스는 비트선(BIT)에 연결되고 트레인은 셀 캐패시터에 연결되며, 캐패시터의 다른쪽 노드는 종래의 경우 기판전위(Vcp)에 연결되지만 본 발명에서는 인접한 다른 비트선(/BIT)에 연결된다. 이렇게 하면 프리차지 모드(precharge)의 경우에 비트선(BIT)과 비트선(/BIT)이 같이 연결되어 있으므로 캐패시터와 전달 트랜지스터가 접속된 노드의 전위가 비트선에 의해 부스트랩(boostrap)되는 효과가 생기어 비트선(BIT)으로 셀 데이타를 전달할 때에 비트선(BIT, /BIT) 사이의 전위차가 크게 되고 센싱 노이즈(sensing noise) 또한 줄어들게 된다. 이에 따라, 칩의 데이타 억세스 타임이 빨라지고 셀 캐패시터가 비트선(BIT, /BIT)에 연결됨으로써 셀 면적이 감소하고 레이아웃이 용이해진다.That is, when one cell is looked at, the source of the transfer transistor is connected to the bit line BIT, the train is connected to the cell capacitor, and the other node of the capacitor is conventionally connected to the substrate potential Vcp, It is connected to the bit line (/ BIT). In this case, since the bit line (BIT) and the bit line (/ BIT) are connected together in the precharge mode, the potential of the node to which the capacitor and the transfer transistor are connected is boosted by the bit line. When the cell data is transferred to the bit line BIT, the potential difference between the bit lines BIT and / BIT becomes large, and the sensing noise is also reduced. As a result, the data access time of the chip is faster and the cell capacitor is connected to the bit lines BIT and / BIT, thereby reducing the cell area and facilitating the layout.

제2도는 본 발명에 의한 셀과 비트선의 연결 상태를 도시한 것으로서, 제1셀(11)의 전달 트랜지스터(T1)는 비트선(BIT)과 캐패시터(C1)를 연결시키고 캐패시터(C1)는 전달 트랜지스터와 인접한 비트선(/BIT)에 연결된다. 또한, 제2셀(12)의 전달 트랜지스터(T2)는 비트선(/BIT)에 연결되고 캐패시터(C2)는 전달 트랜지스터(T2)와 인접한 비트선(/BIT)에 연결된다.2 is a diagram illustrating a connection state between a cell and a bit line according to an exemplary embodiment of the present invention, wherein the transfer transistor T1 of the first cell 11 connects the bit line BIT and the capacitor C1 and the capacitor C1 is transferred. It is connected to the bit line (/ BIT) adjacent to the transistor. In addition, the transfer transistor T2 of the second cell 12 is connected to the bit line / BIT and the capacitor C2 is connected to the bit line / BIT adjacent to the transfer transistor T2.

제3도는 제2도에 도시된 회로의 동작 상태를 도시한 신호 파형도이다.3 is a signal waveform diagram showing an operating state of the circuit shown in FIG.

제3도에서 제1셀(11)의 저장노드(S1)는 프리차지 모드로 갈때 비트선(/BIT)에 의해 부스트램되어 다음 사이클에서 데이타 출력시 더 큰 센싱 마진을 제공한다.In FIG. 3, the storage node S1 of the first cell 11 is boosted by the bit line / BIT when going to the precharge mode to provide a larger sensing margin when outputting data in the next cycle.

제1셀(11)에 저장되어 있는 하이 상태의 셀 데이타를 리드하는 경우에 프리차지 신호(øBLP)가 로우 상태로가면 비트선(BIT)과 비트선(/BIT)의 접속이 끊어지고 워드선(WL)이 하이 상태로 되어 셀 데이타가 비트선(BIT)에 실리게 된다. 이때, 저장노드(S1) 역시 하이 상태인 Vcc+1/2Vcc로 있다가 비트선(BIT)과 동일한 전위로 떨어진다. 일정시간 후에 비트선 감지증폭기 제어신호(øRTO, /øS)가 인에이블되어 센싱 동작이 이루어지면 비트선(BIT)은 전원전위(Vcc)로 비트선(/BIT)은 접지전위(Vss)로 천이하면, 캐패시터(C1)의 저장노드(S1)는 전원전위(Vcc)가 되고 다른쪽 노드는 비트선(/BIT)에 연결되어 접지전위(Vss)가 된다. 이후 다시 프리차지 모드로 가면 워드선(WL)이 로우 상태가 되어 셀을 턴-오프시키고, 이에 따라 저장노드(S1)는 플로팅(floating)된다. 프리차지 모드에서 프리차지 신호(øBLP)가 하이 상태로 되어 비트선(BIT)과 비트선(/BIT)을 기판전위(Vcp=1/2Vcc)로 프리차지 시키면 비트선(/BIT)이 접지전위(Vss)에서 기판전위(1/2Vcc)로 천이함에 따라 캐패시터(C1)의 저장노드(S1)는 전원전위(Vcc)에서 Vcc+1/2Vcc로 되고 비트선(/BIT)은 기판전위(1/2Vcc)로 된다. 따라서 다음 사이클에서 데이타 리드 동작을 할 때 비트선(BIT)은 셀에 전원전위(Vcc)를 라이트(write) 했지만 리드(read)시는 Vcc+1/2Vcc를 리드하게 되어 더 큰 전위의 데이타 디벨롭(develop)을 하게 된다.When the precharge signal øBLP goes low when the cell data of the high state stored in the first cell 11 is read, the connection between the bit line BIT and the bit line / BIT is lost and the word line is disconnected. (WL) becomes high so that the cell data is loaded on the bit line BIT. At this time, the storage node S1 is also at the high state Vcc + 1 / 2Vcc and then drops to the same potential as the bit line BIT. After a certain time, when the bit line sense amplifier control signal (øRTO, / øS) is enabled and sensing operation is performed, the bit line (BIT) transitions to the power potential (Vcc) and the bit line (/ BIT) to the ground potential (Vss). In this case, the storage node S1 of the capacitor C1 becomes the power supply potential Vcc and the other node is connected to the bit line / BIT to become the ground potential Vss. Afterwards, the word line WL is turned low to turn off the cell, and thus the storage node S1 is floated. In the precharge mode, when the precharge signal (øBLP) becomes high and precharges the bit line (BIT) and bit line (/ BIT) to the substrate potential (Vcp = 1 / 2Vcc), the bit line (/ BIT) is grounded. As the transition from Vss to the substrate potential (1 / 2Vcc), the storage node S1 of the capacitor C1 becomes Vcc + 1 / 2Vcc at the power supply potential Vcc, and the bit line (/ BIT) becomes the substrate potential (1). / 2Vcc). Therefore, during the data read operation in the next cycle, the bit line (BIT) writes the power supply potential (Vcc) to the cell, but at the time of read, it reads Vcc + 1 / 2Vcc so that the data level of the larger potential Develop it.

셀 데이타가 로우 산태인 경우에도 상기와 같은 원리로 설명될 수 있으며, 저장노드에 접지전위(Vss)를 라이트하면 리드시키는 Vss-1/2Vss 전위로 리드하게 되어 데이타 디벨롭을 향상시킬 수 있다.Even when the cell data is in a low birth state, the above-described principle can be explained. When the ground potential Vss is written to the storage node, the cell data can be read at the potential of Vss-1 / 2Vss, thereby improving data development.

이상, 제2도 및 제3도에서 설명한 본 발명의 셀 접속방법을 사용하게 되면 종래에 비해 더 큰 데이타 디벨롭 전위를 갖게 되고, 이에 따라 데이타 센싱 마진을 크게 하여 안정된 칩 동작을 갖게 하고 또한, 바른 센싱 동작이 이루어져 고속 반도체 소자를 실현할 수 있는 효과가 있다.As described above, when the cell connection method of the present invention described with reference to FIGS. 2 and 3 has a larger data development potential than in the related art, the data sensing margin is increased, resulting in stable chip operation. Proper sensing operation is achieved to realize a high-speed semiconductor device.

Claims (2)

디램소자의 셀 어레이 블럭에서 이웃하는 두 비트선(BIT, /BIT)에 접속된 셀들에 있어서, 제1비트선(BIT)에 전달 트랜지스터의 소오스가 접속된 제1셀의 캐패시터의 한쪽 노드는 상기 제1셀의 전달 트랜지스터의 드레인에 연결하고 다른쪽 노드는 제2비트선(/BIT)에 연결하며, 제2비트선(/BIT)에 전달 트랜지스터의 소오스가 접속된 제2셀의 캐패시터의 한쪽 노드는 상기 제2셀의 전달 트랜지스터의 드레인에 연결하고 다른쪽 노드는 제1비트선(BIT)에 연결하는 것을 특징으로 하는 셀 접속방법.In cells connected to two neighboring bit lines BIT and / BIT in a cell array block of a DRAM device, one node of a capacitor of a first cell in which a source of a transfer transistor is connected to the first bit line BIT One of the capacitors of the second cell connected to the drain of the transfer transistor of the first cell, the other node is connected to the second bit line (/ BIT), and the source of the transfer transistor is connected to the second bit line (/ BIT). And a node is connected to the drain of the transfer transistor of the second cell and the other node is connected to the first bit line (BIT). 제1항에 있어서, 상기 이웃하는 두 비트선(BIT, /BIT) 사이에는 프리차지 모드시 두 비트선의 전위를 동일하게 유지시켜 주는 프리차지 회로가 포함되어 있는 것을 특징으로 하는 셀 접속방법.The cell connection method of claim 1, wherein a precharge circuit is provided between the two neighboring bit lines (BIT, / BIT) to maintain the same potential of the two bit lines in the precharge mode.
KR1019940004734A 1994-03-11 1994-03-11 Connecting method of dram cell KR960009959B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019940004734A KR960009959B1 (en) 1994-03-11 1994-03-11 Connecting method of dram cell
GB9504936A GB2287560A (en) 1994-03-11 1995-03-10 Memory cell for dynamic random access memory
DE1995108736 DE19508736A1 (en) 1994-03-11 1995-03-10 Memory cell for dynamic random access memory
JP7052407A JPH0855474A (en) 1994-03-11 1995-03-13 Memory cell of dynamic random access memory

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KR1019940004734A KR960009959B1 (en) 1994-03-11 1994-03-11 Connecting method of dram cell

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KR960009959B1 true KR960009959B1 (en) 1996-07-25

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DE (1) DE19508736A1 (en)
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Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4420822A (en) * 1982-03-19 1983-12-13 Signetics Corporation Field plate sensing in single transistor, single capacitor MOS random access memory
US4506351A (en) * 1982-06-23 1985-03-19 International Business Machines Corporation One-device random access memory having enhanced sense signal
US4493056A (en) * 1982-06-30 1985-01-08 International Business Machines Corporation RAM Utilizing offset contact regions for increased storage capacitance
JPS60239993A (en) * 1984-05-12 1985-11-28 Sharp Corp Dynamic semiconductor memory device
US4715015A (en) * 1984-06-01 1987-12-22 Sharp Kabushiki Kaisha Dynamic semiconductor memory with improved sense signal
US5293563A (en) * 1988-12-29 1994-03-08 Sharp Kabushiki Kaisha Multi-level memory cell with increased read-out margin

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GB9504936D0 (en) 1995-04-26
DE19508736A1 (en) 1995-10-12
JPH0855474A (en) 1996-02-27
GB2287560A (en) 1995-09-20

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