JPH06175848A - High-speed branch processing system for central processing unit - Google Patents

Abstract

PURPOSE:To fetch a branch destination address or a branch destination address with the high probability of branching next to a branching instruction for accelerating the branching instruction at a central processing unit (CPU) such as a microcomputer. CONSTITUTION:This system is constituted of a CPU 1 provided with a pipeline processing part 2 from fetch 3 to execution 4 and a program counter 5, a program counter stack means 7, a high-probability branch destination registering means 9, a program counter queue storage means 8 for the step of queuing a counter value and an instruction judging means 6 for analyzing an instruction 10 fetched 3, reloading the counter 5 with the branching destination address in an unconitional case, writing the branch destination in the counter when the instruction is registered, and loading the address value in the lowest step of the program counter queue storage means to the program counter 5 when the conditions are not satisfied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control operation unit such as a sequencer or a microcomputer, which fetches an instruction for branching to an address registered in an address comparison table in a chip or an unconditional branch instruction. The present invention relates to a high-speed branch processing method of a central processing unit that fetches a jump destination instruction before executing it and speeds up branch processing.

[0002]

2. Description of the Related Art An example of a conventional processing method for branching processing of a central processing unit will be described. FIG. 12 is a configuration example of a general central processing unit.

The central processing unit 1200 comprises a fetch unit 1210 for fetching a program, a decode unit 1220 for decoding, a source fetch unit 1230 for fetching source operands, and an execution unit 1240 for executing instructions. . The execution unit 1240 uses the register file 1241,
It consists of a program counter PC1242 and an ALU1243.

Since the fetch unit 1210, the decode unit 1220, the source fetch unit 1230, and the execution unit 1240 operate independently of each other, four-stage pipeline processing (fetch, decode, source operand fetch, execution) can be performed. it can.

FIG. 13 shows an example of a program including an unconditional branch instruction, and FIG. 14 shows a time chart when this program is processed by the configuration of the general central processing unit shown in FIG.

When the program shown in FIG. 13 is executed by the apparatus shown in FIG. 12, as shown in the time chart of FIG.
Processing progresses one cycle at a time. First, 1000 addresses are set on the address bus (A bus) in one cycle.
IN which is the contents of address 1000 on the data bus (D bus)
C A is set. And the program counter (P
C) is number 1000.

In the second cycle, INC A is fetched and the next JMP LOOP instruction is set on the data bus. Similarly, in the third cycle, INC A is decoded, JMP LOOP is fetched, MOV A,
B is set to the data bus. IN the next 4th cycle
CA is source fetched and executed in the fifth cycle.

Focusing on the branch instruction (JUMP LOOP), the program fetch unit 1210 fetches from the instruction memory 1100 in the third cycle,
In a cycle, the program decode unit 1220 decodes an instruction into a branch instruction and a branch destination address. Then, in the fifth cycle, the source fetch unit 1230 fetches the source operand, and finally in the sixth cycle, JUMP LO.
Execute the OP instruction.

In the execution unit 1240, the program counter (P
The value of C) is rewritten to the branch destination address to invalidate the contents of each pipeline. Then, in the cycles from the cycle 7 onward, the processing of fetching-decoding-source fetching-execution from the address 2000 onward is executed.

[0010]

However, in the conventional method, it is necessary to clear all the contents of the pipeline as the branch instruction is executed and then start the instruction after the branch instruction from the fetch processing. There is a problem of causing cycle overhead.

That is, in the time chart of FIG. 14, the program counter reaches the address 2000 when the JUMP instruction is executed in the sixth cycle, and after invalidating all the contents of the pipeline, the instructions after the address 2000 are fetched. Processing, 7th cycle to 10th cycle
The execution unit 1240 is not operating in the cycle. This means that there is an overhead of 4 cycles.

An object of the present invention is to eliminate such overhead in branch processing and speed up branch instruction processing.

[0013]

FIG. 1 is a functional block diagram of the present invention. The present invention relates to a central processing unit 1 for pipeline processing of fetch 3 to execution 4 of an instruction 10.
Is assumed. Further, the central processing unit 1 has a program counter 5.

The instruction judging means 6 receives the fetched instruction 10 as an input and judges whether the instruction 10 is a branch instruction. If it is not a branch instruction, the pipeline processing unit 2 of the central processing unit 1 performs normal fetch 3 to execution 4. In the case of a branch instruction, the processing according to either the unconditional branch instruction or the conditional branch instruction is executed.

When the instruction judging means 6 judges that the instruction 10 is an unconditional branch instruction, the instruction judging means 6 rewrites the contents of the program counter 5 to the branch destination address of the unconditional branch instruction.

Program counter stack means 7
In the case of a subroutine call instruction among unconditional branch instructions, pushes the contents of the program counter 5 onto the stack and then rewrites the contents of the program counter 5 with the branch address of the unconditional branch instruction. In the case of a return subroutine instruction, the stack is hopped and the return address of the subroutine is loaded into the program counter 5.

The branch address registration means 9 registers the branch destination address when the probability of jumping to the branch destination address is high. The program counter queue storing means 8 queues the program counter value at the timing when the program counter 5 is rewritten. The save queue is one stage smaller than the number of pipeline stages and has the same bit width as the program counter 5.

The instruction judging means 6 uses the fetched instruction 10
Is a conditional branch instruction, it is judged whether or not the branch destination address is registered in the branch address registration means 9, and if it is registered, the contents of the program counter 5 are rewritten to the branch destination address.

When the conditional branch instruction is executed 4 in the pipeline processing unit 2, if the condition is satisfied, if the processing is continued as it is, the instruction in the branch destination address is executed next. On the other hand, when the condition is not satisfied, the program counter queue storing means 8 loads the address of the lowest stage of the queue into the program counter 5. At this time, the next address of the conditional branch instruction is entered at the bottom of the queue. As a result, when this address is fetched 3 to 4 by the pipeline processing unit 2, the instruction is correctly executed.

[0020]

First, if there is a branch destination address with a high probability of branching in the conditional branch instruction, the branch destination address is registered in the branch address registration means 9 through the execution 4 of the pipeline processing unit 2.

Further, the program counter queue storing means 8 queues the program counter value every time the program counter 5 is rewritten. For example, in the case of the 4-stage pipeline processing unit 2 of fetch 3-decode-source fetch-execute 4, a 3-stage save queue is prepared. As a result, the next address of the instruction address processed in execution 4 is always in the bottom row of the queue.

When the instruction 10 is fetched 3 by the pipeline processing section 2, the instruction judging means 6 fetches the fetched instruction 1
Analyze 0 opcodes. If the instruction 10 is other than a branch instruction, the pipeline processing unit 2 performs normal fetch to execution.

On the other hand, when the instruction 10 is a branch instruction, the corresponding processing is executed depending on the type of the branch instruction. First,
When the instruction 10 is an unconditional branch instruction, the instruction judging means 6
Rewrites the contents of the program counter 5 to the branch destination address. As a result, the branch destination address is fetched 3 to 4 after the unconditional branch instruction.

Among unconditional branch instructions, a subroutine
In the case of a call instruction, the instruction judging means 6
The contents of the program counter 5 are first pushed to the counter stack means 7, and then the address of the subroutine which is the branch destination address is written in the program counter 5. As a result, the return address after the execution of the subroutine is stored in the program counter stack means 7.

When the instruction 10 is a return subroutine instruction, the program counter stack means 7 is hopped and the return address of the subroutine is written in the program counter 5. As a result, after the return subroutine instruction, the instruction at the return address is fetched 3 to
It will be executed 4.

When the instruction 10 is a conditional branch instruction, the instruction judging means 6 judges whether or not the branch address registering means 9 has a branch destination address of the conditional branch instruction. If the branch destination address is not registered, normal pipeline processing is continued.

On the other hand, when the branch destination address is registered, the instruction judging means 6 writes the branch destination address in the program counter 5. Then, after the conditional branch instruction, the instructions after the branch destination address are processed by the pipeline processing unit 2
To process.

When the conditional branch instruction is actually executed 4 in the pipeline processing unit 2, the condition is satisfied or not satisfied. If the condition is satisfied, the branch destination instruction that is pipelined next may be executed 4. On the other hand, if the condition is not satisfied, the instruction at the address next to the conditional branch instruction must be processed. Since this address is in the lowest stage of the program counter queue storing means 8, the address of the lowest stage of the queue is loaded into the program counter 5, and the pipeline processing unit 2 fetches 3 to 4 for fetching. As a result, the instruction at the address next to the conditional branch instruction is correctly processed.

[0029]

EXAMPLES Examples of the present invention will be described below. Figure 2
FIG. 1 is a system configuration diagram of an embodiment.

This embodiment comprises a central processing unit 210, an instruction memory 200 and a data memory 290 as in the conventional system, but the central processing unit 210 is strengthened.

The central processing unit 210 includes an instruction fetch unit 220 for fetching a program, an instruction decode unit 230 for decoding the fetched instruction, a source fetch unit 240 for fetching a source operand, and an execution unit 250 for executing an instruction. In addition to the above, the instruction determining unit 260 for determining the content of the instruction is included. Also, the instruction fetch unit 220 is strengthened.

The instruction fetch unit 220 uses the fetch queue.
221, a program counter PC222, a PC stack 223 for stacking program counts, and a PC queue 224 for queuing PCs. PC queue
The number 224 is three, which is the number of pipeline stages after fetching minus one.

On the other hand, the instruction judging section 260 is a branch destination table which is a table having a cache structure for storing an instruction judging logic 261 for analyzing an instruction and a branch destination address.
It is composed of 262 etc.

An instruction address bus 270 and an instruction data bus 275 are provided as the input / output buses of the instruction memory 200. The instruction address bus 270 is connected to the program counter 222 of the instruction fetch section 220 and is connected to the instruction data bus 275. Is connected to the fetch queue 221 of the instruction fetch unit 220. And the instruction memory 200 is the instruction address bus.
The contents of the program counter value input to 270 are output to the fetch queue 221 via the instruction data bus 275.

The output of the fetch queue 221 is the instruction judgment unit 261 of the instruction decoding unit 230 and the instruction judgment unit 260.
It is connected to the. The instruction stored in the fetch queue 221 is analyzed by the instruction judgment logic 261 to judge whether or not the instruction is a branch instruction.

FIG. 3 is a block diagram of the instruction determination unit 260 of one embodiment. The instruction determination unit 260 includes an instruction determination logic 261, a branch destination table 262, an OR gate 300, and an AND gate 35.
It consists of 0.

The instruction determination logic 261 is an instruction fetch unit.
It is connected to the fetch queue 221 of 220, and only the opcode (a part excluding the operand) of the instructions in the fetch queue 221 is used as its input. Instruction decision logic 261
Determines whether the operation code is a branch instruction, or if it is a branch instruction, it is an unconditional branch instruction or a conditional branch instruction.
For this determination, the operation codes of the unconditional branch instruction and the conditional branch instruction are held in the instruction judgment logic 261, and the operation code to be input may be matched. If the operation code is judged to be an unconditional branch instruction, one input of the OR gate 300 is set to "1", and if it is not an unconditional branch instruction, the input is set to "0". On the other hand, if the operation code is judged to be a conditional branch instruction, one input of the AND gate 350 is set to "1", and if it is not a conditional branch instruction, the input is set to "0".

The branch destination table 262 is a cache structure table, and each time a branch instruction is executed by the instruction executing section 250, the branch destination address of the branch instruction is registered in this table. Then, when an instruction enters the fetch queue 221, only the operand of the instruction is branched to the branch destination table 262.
And input. When the operand is input, the operand is compared with the branch destination address stored in the branch destination table 262, and if there is a match (HIT),
The other input of the AND gate 350 is set to "1", and when there is no matching address, the input is set to "0". The output of the AND gate 350 becomes the other input of the OR gate 300. The output of the OR gate 300 is the load timing signal (LD) of the program counter 222.
Becomes

With the above configuration, the fetch queue 221
When an instruction is input to the OR gate 300, if the instruction is an unconditional branch instruction, one input of the OR gate 300 is “1”,
The output of 300 becomes "1". At the time when “1” is input to LD, the program counter 222 fetches the fetch queue.
Load the branch destination address that is the operand from 221.

On the other hand, if the instruction is a conditional branch instruction, one input of the AND gate 350 becomes "1". At this time, if the branch destination table 262 has a branch destination address to be hit, the other one of the AND gate 350. Also becomes "1", the output of the AND gate 350 becomes "1", and the output (LD) of the OR gate 300 becomes "1". This causes the program counter 222 to fetch queue 221.
Load the branch destination address from. Even if the instruction is a conditional branch instruction, if there is no branch destination address to be hit in the branch destination table 262, the other input of the AND gate 350 becomes "0", so that the output of the AND gate 350 becomes "0". ", The output of the OR gate 300 becomes" 0 ". Therefore, the program counter 222 becomes the fetch queue 221.
The branch destination address is not loaded from.

If the instruction is not a branch instruction, one input of the AND gate 350 indicating a conditional branch becomes "0" and one input of the OR gate 300 indicating an unconditional branch becomes "0", and the OR gate 300 Is 0, the program counter 222 fetches the fetch queue 221.
The branch destination address is not loaded from.

FIG. 4 is an example of a program including an unconditional branch instruction. When this program is processed by the system configuration of the embodiment shown in FIG. 2, the operation shown in the time chart of FIG. 5 is performed.

An unconditional branch instruction called JMP LABEL at address 1001 in the program shown in FIG. 4 is set in the instruction data bus 275 in the second cycle and enters the fetch queue 221 in the third cycle. The instruction judgment logic 261 of the instruction judgment unit 260 is the fetch queue 221.
The entered instruction is analyzed to determine that it is an unconditional branch instruction, the branch destination address 2000 is stored in the program counter 222 in the next cycle (fourth cycle), and the next address that should enter the fetch queue 221 is stored. Invalidates the instruction ADD A, C. From the fifth cycle, fetch-decode-source fetch-execution processing of the branch destination instruction is performed.
That is, in the fifth cycle, the instruction at the branch destination address 2000, AND A, D, is fetched, in the sixth cycle, the decoding section 230 decodes, in the seventh cycle, the source fetch section 240 fetches the operand, and in the eighth cycle. Execution takes place. As a result, the END instruction at the address 2001 is executed in the ninth cycle, and the processing ends.

When the similar program of FIG. 4 is executed in the conventional system configuration (FIG. 12), the unconditional branch instruction is executed to change the program counter to the branch destination and invalidate the contents of the pipeline. Was there. as a result,
In the seventh cycle, which is the cycle after the execution of the unconditional branch instruction, the content of the program counter becomes address 2000, and from the eighth cycle, the fetch-execution processing of the branch destination instruction is performed. Therefore, it is the twelfth cycle that the END instruction at the address 2001 is executed and the processing is ended.

That is, according to this embodiment, in the case of this program, the branch processing can be sped up for 3 cycles. FIG. 6 is a program example including a subroutine call instruction, and FIG. 7 is a time chart when the program of FIG. 6 is processed by the system configuration (FIG. 2) of this embodiment.

In this program example, the instruction at address 1001 is a subroutine call instruction, and after executing the program at addresses 2000 to 2002 by this instruction, the program returns to address 1002.

When processing is performed with the system configuration (FIG. 2) of this embodiment, as shown in FIG. 7, CAL is performed in the second cycle.
L LABEL instruction is an instruction data bus
275 and stored in the fetch queue 221 in the third cycle. At this point, the instruction determination logic 261 of the instruction determination unit 260 determines that the instruction is a subroutine call instruction, and invalidates the content of the instruction at address 1002 that should be stored in the fetch queue 221 in the fourth cycle, The contents (address 1002) of the program counter 222 at that time are pushed to the PC stack 223, and the branch destination address (address 2000) is stored in the program counter 222. Then, from the fifth cycle, the processing moves to the subroutine.

That is, the fetch of address 2000 (AND A, C) is performed in the fifth cycle, and the fetch of address 2001 (MUL A, D) and 20 are performed in the sixth cycle.
No. 00 (AND A, C) is decoded and the 7th
In the cycle, fetching at address 2002 (RTS) and 20
Decoding of address 01 (MUL A, D) and source fetch of address 2000 (AND A, C) are performed.

When the return subroutine instruction (RTS) is stored in the fetch queue 221, the instruction decision logic 261 of the instruction decision unit 260 decides that it is a return instruction, and the PC stack 223 reads it from the next cycle (eighth cycle). Pop the program counter 222 and invalidate the contents of the fetch queue 221. As a result, the program counter 222 becomes the address 1002. further,
In the eighth cycle, decoding of address 2002 (RTS), source fetch of address 2001 (MUL A, D), and execution of address 2000 (AND A, C) are performed.

From the ninth cycle, the program fetch-execution processing is performed from address 1002. With the above processing, the program of FIG. 6 is completed in the 14th cycle (the END instruction at address 1003 is executed in the 14th cycle).

On the other hand, when the program of FIG. 6 is executed with the conventional system configuration (FIG. 12), C at address 1001
Next cycle after executing ALL LABEL instruction (7th cycle)
In the cycle, the program counter 222 is set to the address 2000, and the next cycle (from the 8th cycle to 2000)
Fetching to execution after the address is performed. Therefore 2000
The AND A, C instruction at the address is executed in the 11th cycle, and the RTS instruction at the address 2002 is in the 13th cycle. When the RTS instruction is executed, the program counter 222 is set to the address 1002 in the next 14th cycle, and the fetch-execution from the 15th cycle to the address 1002 and thereafter is performed. Therefore, in the conventional configuration, the program of FIG. 6 is completed in the 19th cycle (the END instruction at address 1003 is executed in the 19th cycle).

As a result, the configuration of this embodiment (FIG. 2) is faster than the conventional configuration (FIG. 12) by 5 cycles. FIG. 8 is an example of a program including a conditional branch instruction. FIG. 9 shows a time chart when this program is executed by the system configuration (FIG. 2) of this embodiment.

The program shown in FIG. 8 is composed of an initial routine that is executed in advance and a main routine that is executed after the initial routine is executed. MOV at address 0000 when the initial routine is executed
The branch destination address LOOP is stored in the branch destination table 262 when a branch instruction of BAT, LOOP is executed. Then, an unconditional branch instruction called JMP MAIN at address 0001 jumps to the main routine.

The main routine substitutes 2 for C by the instruction at address 1000, and loops addresses 1001 to 1002 when the value of C is not 0. Here, since the initial routine has been executed in advance, it is assumed that the branch destination table 262 stores the address of LOOP, and the main routine is executed under this premise.

Explaining with the time chart of FIG. 9, when the conditional branch instruction (JNE 1001) is stored in the fetch queue 221 in the fourth cycle, the instruction judgment logic 261 searches the branch destination table 262 and the branch destination address is Make sure it is stored there. The fact that it is stored means that there is a high probability of branching, and the instruction judgment logic 261 has the program counter 22 in the fifth cycle.
The branch destination address 1001 is stored in 2, and the contents of the fetch queue that should be fetched next are invalidated. In the sixth and subsequent cycles, the fetch-execution of the branch destination is performed.

On the other hand, the PC queue 224 performs queuing at the timing when the program counter 222 is rewritten. For example, when the program counter value "1000" is rewritten to "1001", it is queued and P
'1000' is pushed to the top of C. After that, since the PC queue 224 is pushed when the counter value is rewritten, '1000' is the PC queue in the fourth cycle.
It will be queued at the bottom of 224. In the fifth cycle, the program counter 222 in the fourth cycle
The matching '1003' enters the top stage of the PC queue 224, and enters the bottom stage in the seventh cycle.

In the seventh cycle, the conditional branch instruction (JNE
LOOP) is executed. The value of C is set to '2' in the fifth cycle, decremented by 1 in DEC C in the sixth cycle, and becomes '1' in the seventh cycle. Therefore, the seventh
The conditional branch instruction of the cycle matches the condition (C ≠ 0), 1
It will loop to address 001. This address 1001 refers to the branch address table 262 at the time of the conditional branch instruction fetch in the fourth cycle, and the program counter 22
It is set to 2, fetched in the 6th cycle, decoded in the 7th cycle, and source fetched in the 8th cycle. Therefore, it is possible to execute the address 1001 in the ninth cycle. As a result of execution, the value of C becomes "0". In the 10th cycle, the conditional branch instruction (J
NE LOOP) is executed.

On the other hand, in the seventh cycle, the fetch queue
A JNE LOOP instruction has been fetched by 221. Similar to the case of the fourth cycle, LOOP (1001
Address) is stored in the branch address table 262. Since it is stored, the program counter 222 is set to the address 1001 in the eighth cycle.
Invalidates the contents of fetch queue 221. Also, PC
Queue 224 has a program counter in the 7th cycle
Push the address 1003 which is the content of 222.

In the 10th cycle, the conditional branch instruction (JN
When E LOOP) is executed, the condition is not satisfied at this time (C = 0). In this case, unlike the case of the condition match (seventh cycle), the next address 1003 is executed without looping. Therefore, the first
In one cycle, the return address 1003 from the bottom of the PC queue 224 is loaded into the program counter 222, and the contents of the fetch queue 221 and the instruction decoding unit 230 are loaded.
And the contents of the source fetch unit 240 are invalidated. Then, from the next twelfth cycle, the fetch-execution processing from the address 1003 onward is started. By this, 1003
The address can be executed by the instruction execution unit 250 in the 15th cycle.

As described above, in the case of a conditional branch instruction,
By storing the branch destination address having a high probability of branching in advance in the branch address table 262, the branch destination address can be fetched next after the conditional branch instruction is fetched. Therefore, when the condition is satisfied, the instruction at the branch destination address can be executed two cycles after the conditional branch instruction execution cycle. On the other hand, if the condition is not satisfied, the lowermost stage of the PC queue 224 is loaded into the program counter 222 in the next cycle, and then fetch-execute processing is performed. Therefore, when the condition is not satisfied, the next address can be executed 5 cycles after the conditional branch instruction execution cycle.

When this program (FIG. 8) is executed with the conventional system configuration (FIG. 12), after execution of the conditional branch instruction, if the condition is not satisfied, the next address can be executed in the next cycle, but the condition is satisfied. If so, the branch destination address can be executed after 5 cycles. When the probability of branching to the branch destination address is high, 5 cycles are wasted each time the condition is satisfied, and this embodiment speeds up by 3 cycles each time.

FIG. 10 is an example of a program in which conditional branch instructions are continuous, and FIG. 11 is a time chart when the program of FIG. 10 is executed by the system configuration of this embodiment (FIG. 2).

In this case, address 1001 (JNE L1)
Is fetched (third cycle), the instruction decision unit 260 processes the program in the next cycle (fourth cycle).
The counter 222 is set to the branch destination address L1 (address 2000), and the contents of the fetch queue 221 are invalidated. In the fourth cycle, the PC queue 224
Address 1002 is stored in the uppermost row of.

In the fifth cycle, address 2000 (JZE
L2) is fetched. Then, in the next cycle (sixth cycle), the instruction counter 260 sets the program counter to the branch destination address L2 (address 3000) and invalidates the contents of the fetch queue 221.

On the other hand, in the sixth cycle, address 1001 (J
NE L1) is executed. In this case, since A = 0, the conditions do not match. Therefore, L1 (address 1002 is executed next without jumping to address 2000).
If the conditions do not match, the next cycle (7th cycle)
Then, the contents of the bottom of the PC queue 224 are loaded into the program counter 222, and the contents of the pipeline (fetch, decode, source fetch) are invalidated. As a result, the content of the program counter becomes the address 1002, and the fetch to execution of the address 1002 and subsequent addresses are performed from the eighth cycle.

If the PC queue 224 is simply a temporary save register, the contents of the register are updated in cycle 6 after fetching the second conditional branch instruction, and the first conditional branch instruction is If there is a mismatch,
It becomes impossible to return to the original processing address (address 1002). Therefore, it is significant to set the PC queue 224 to three stages, which is one stage less than the pipeline stage number of four stages.

[0067]

As described above, according to the present invention, when an instruction is stored in the fetch queue, the instruction judging section analyzes the instruction, thereby making it possible to accelerate the branch processing of the unconditional branch instruction as compared with the conventional method. Further, regarding the conditional branch instruction as well, by registering the branch destination address in the branch destination table for the branch instruction having a high probability of branching, it is possible to speed up the entire program execution. In addition, the number of stages is one less than the number of pipeline stages
By providing a queue, it is possible to quickly return to the original processing address even if the conditional branch instructions do not match.

[Brief description of drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a system configuration diagram of an embodiment.

FIG. 3 is a configuration diagram of an instruction determination unit according to an embodiment.

FIG. 4 is a program example including an unconditional branch instruction according to an embodiment.

FIG. 5 is a time chart of unconditional branch instruction processing according to an embodiment.

FIG. 6 is a program example including an unconditional subroutine call instruction according to an embodiment.

FIG. 7 is a time chart of unconditional subroutine call instruction processing according to an embodiment.

FIG. 8 is a program example including a conditional branch instruction according to an embodiment.

FIG. 9 is a time chart of conditional branch instruction processing according to an embodiment.

FIG. 10 is an example of a program in which conditional branch instructions of one embodiment are consecutive.

FIG. 11 is a time chart when conditional branch instructions of one embodiment are consecutive.

FIG. 12 is a block diagram of a conventional central processing unit.

FIG. 13 is a program example for explaining the operation of the conventional system.

FIG. 14 is a time chart explaining the operation of the conventional system.

[Explanation of symbols]

 1 Central Processing Unit 2 Pipeline Processing Unit 3 Fetch 4 Execution 5 Program Counter 6 Instruction Judging Means 7 Program Counter Stacking Means 8 Program Counter Queue Storing Means 9 Branch Address Registering Means 10 Instructions

Claims (2)

[Claims] 1. A central processing unit (1) comprising a pipeline processing section (2) for pipeline processing fetch (3) to execution (4) of an instruction (10) and a program counter (5), comprising: The contents of the executed instruction (10) are analyzed, and if the instruction (10) is an unconditional branch instruction, the program
Instruction judging means (6) for rewriting the counter (5) to the branch destination address of the unconditional branch instruction, and if the unconditional branch instruction is judged to be a subroutine call instruction, the instruction Before the program counter (5) is rewritten by the judging means (6), the contents of the program counter (5) are pushed onto the stack to store the return address, and the instruction judging means (6) stores If the conditional branch instruction is determined to be a return / subroutine instruction, the stack is hopped,
A high-speed branch processing system of a central processing unit, comprising: a program counter stack means (7) for setting a return address of a subroutine in a program counter (5). 2. A high-speed branch high-speed processing method for a central processing unit according to claim 1, wherein a branch address registering means (9) for registering a branch address with a high probability of branching, and the number of stages of queues are provided. It has the same bit width as the program counter (5) at (the number of pipeline stages of the central processing unit-1), and the program counter (5) is queued at the rewriting timing of the program counter (5) to The instruction determining means (6) further comprises a program counter queue storing means (8) for saving the contents of the counter (5), and the fetched instruction (1
0) is a conditional branch instruction, and if the branch destination address is registered in the branch address registering means (9), the program counter (5) is rewritten to the branch destination address and the condition of the conditional branch instruction is rewritten. The branch destination address is executed immediately after the condition is satisfied, and if the condition of the conditional branch instruction is not satisfied, the address to be processed next, which is the lowermost content of the program counter queue storing means (8), is programmed. A high-speed branch processing method of the central processing unit, which is characterized in that it is loaded into the counter (5).