JPH06175158A - Liquid crystal display - Google Patents
Liquid crystal displayInfo
- Publication number
- JPH06175158A JPH06175158A JP33071192A JP33071192A JPH06175158A JP H06175158 A JPH06175158 A JP H06175158A JP 33071192 A JP33071192 A JP 33071192A JP 33071192 A JP33071192 A JP 33071192A JP H06175158 A JPH06175158 A JP H06175158A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- liquid crystal
- crystal display
- pixel electrode
- display device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133509—Filters, e.g. light shielding masks
- G02F1/133512—Light shielding layers, e.g. black matrix
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は表示装置、特にアクティ
ブマトリクス型の液晶ディスプレイに関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to an active matrix type liquid crystal display.
【０００２】[0002]
【従来の技術】従来、２枚の基板間に液晶を挟持し、少
なくとも一方の基板上にスイッチング素子を形成したア
クティブマトリクス液晶表示装置の一画素部分は、たと
えば図１、及び図１のＸ−Ｘ’間に於ける断面図である
図２に示す様な構成となっている。ガラス、石英、サフ
ァイア等の基板１１上に不純物を添加した多結晶シリコ
ン等のＮ+ シリコン薄膜からなるソース領域１２・ドレ
イン領域１３が形成されている。これらのソース領域１
２・ドレイン領域１３の上側に接して、この両者を結ぶ
様に多結晶シリコン等のシリコン薄膜からなるチャネル
領域１４が設けられている。これら全体をシリコン酸化
膜等の絶縁膜から成るゲート絶縁膜１５が被覆してお
り、この上に金属、透明導電膜等から成るゲート電極兼
走査線１６が形成されている。この上に、シリコン酸化
膜等の絶縁膜から成る層間絶縁膜１７が被膜しており、
コンタクト・ホール１８を介して、金属、透明導電膜等
から成る信号線１９、同じく画素電極２０がソース領域
１２・ドレイン領域１３に各々接続されている。この様
に画素電極２０と信号線１９は同一平面上に形成するの
が一般的であるが、この場合、画素電極２０と信号線１
９の間は、ショートしない様に間隔を開ける必要があ
る。同様に画素電極２０と走査線１６の間もクロストー
クを防ぐ為に間隔を開けるのが普通である。この為、画
素電極面積の減少、即ち開口率の低下が問題となる。加
えて、コントラストの低下を防止する為に、画素電極以
外の領域にブラック・ストライプ（ＢＳ）２１と呼ばれ
る遮光膜を形成する場合には、画素電極とＢＳのアライ
メント余裕も必要となって、開口率は更に低下してしま
う。2. Description of the Related Art Conventionally, one pixel portion of an active matrix liquid crystal display device in which a liquid crystal is sandwiched between two substrates and a switching element is formed on at least one substrate is, for example, shown in FIGS. The structure is as shown in FIG. 2, which is a sectional view taken along the line X ′. On a substrate 11 made of glass, quartz, sapphire, or the like, a source region 12 and a drain region 13 made of N + silicon thin film made of doped polycrystalline silicon are formed. These source regions 1
2. A channel region 14 made of a silicon thin film such as polycrystalline silicon is provided so as to be in contact with the upper side of the drain region 13 and connect the two. A gate insulating film 15 made of an insulating film such as a silicon oxide film is entirely covered, and a gate electrode / scanning line 16 made of metal, a transparent conductive film, or the like is formed on the gate insulating film 15. An interlayer insulating film 17 made of an insulating film such as a silicon oxide film is coated on this,
A signal line 19 made of metal, a transparent conductive film or the like, and a pixel electrode 20 are connected to the source region 12 and the drain region 13 via the contact holes 18, respectively. In this way, the pixel electrode 20 and the signal line 19 are generally formed on the same plane, but in this case, the pixel electrode 20 and the signal line 1 are formed.
It is necessary to open a space between 9's to prevent short circuit. Similarly, a space is usually provided between the pixel electrode 20 and the scanning line 16 to prevent crosstalk. Therefore, the reduction of the pixel electrode area, that is, the reduction of the aperture ratio becomes a problem. In addition, when a light-shielding film called a black stripe (BS) 21 is formed in a region other than the pixel electrode in order to prevent a decrease in contrast, an alignment margin between the pixel electrode and BS is required, and the opening The rate will drop further.
【０００３】その対策として、信号線を先に形成し、そ
の上に絶縁膜を堆積した後、画素電極を形成する方法が
提案されている。この方法を用いると、画素電極を信号
線上にまで延ばす事が出来るので、大幅な開口率の向上
が期待出来る。その一例を図３、及び図３のＸ−Ｘ’間
に於ける断面図である図４に示す。ガラス、石英、サフ
ァイア等の基板３１上に不純物を添加した多結晶シリコ
ン等のＮ+ シリコン薄膜からなるソース領域３２・ドレ
イン領域３３が形成されている。これらのソース領域３
２・ドレイン領域３３の上側に接して、この両者を結ぶ
様に多結晶シリコン等のシリコン薄膜からなるチャネル
領域３４が設けられている。これら全体をシリコン酸化
膜等の絶縁膜から成るゲート絶縁膜３５が被覆してお
り、この上に金属、透明導電膜等から成るゲート電極、
兼走査線３６が形成されている。この上に、シリコン酸
化膜等の絶縁膜から成る層間絶縁膜３７が被膜してお
り、コンタクト・ホール３８を介して、金属、透明導電
膜等から成る信号線３９がソース領域３２と接続されて
いる。この上に、第二の層間絶縁膜４０が堆積され、第
二のコンタクト・ホール４１を介して、画素電極４２が
ドレイン領域３３と接続されている。As a countermeasure, there has been proposed a method of forming a signal line first, depositing an insulating film on the signal line, and then forming a pixel electrode. By using this method, the pixel electrode can be extended to above the signal line, so that a significant improvement in the aperture ratio can be expected. An example thereof is shown in FIG. 3 and FIG. 4 which is a cross-sectional view taken along line XX ′ in FIG. A source region 32 and a drain region 33 are formed on a substrate 31 made of glass, quartz, sapphire, or the like, which is made of an N + silicon thin film made of impurity-doped polycrystalline silicon or the like. These source regions 3
2. A channel region 34 made of a silicon thin film of polycrystalline silicon or the like is provided so as to be in contact with the upper side of the drain region 33 and connect the two. A gate insulating film 35 made of an insulating film such as a silicon oxide film covers the whole of these, and a gate electrode made of metal, a transparent conductive film, or the like is formed on the gate insulating film 35.
Dual scanning lines 36 are formed. An interlayer insulating film 37 made of an insulating film such as a silicon oxide film is coated on this, and a signal line 39 made of a metal, a transparent conductive film, or the like is connected to the source region 32 via a contact hole 38. There is. A second interlayer insulating film 40 is deposited on this, and the pixel electrode 42 is connected to the drain region 33 via the second contact hole 41.
【０００４】また、画素電極は信号線、走査線上に延び
ており開口率を向上させている。更に、信号線、走査線
を遮光性材料で形成する事で、ＢＳパターンも省略でき
る。この方法を用いた場合、前述の様にクロストークの
発生が危惧されるが、信号線上に堆積する絶縁膜を充分
厚くする事で対応しようとしている。その意味から、こ
の絶縁膜には、膜厚を厚くでき、また比較的誘電率の小
さいポリイミドが用いられる。Further, the pixel electrode extends on the signal line and the scanning line to improve the aperture ratio. Further, the BS pattern can be omitted by forming the signal line and the scanning line with a light-shielding material. When this method is used, there is a concern that crosstalk will occur as described above, but we are trying to deal with this by making the insulating film deposited on the signal line sufficiently thick. From this point of view, a polyimide having a relatively small dielectric constant can be used for this insulating film.
【０００５】[0005]
【発明が解決しようとする課題】しかし、従来技術には
以下に述べるような課題があった。即ち、画素電極を信
号線や走査線と重なり合わせる事でクロストークの発生
が危惧されるのは、前述の通りであるが、特に自段の走
査線の影響は顕著である。この為、信号線上に堆積する
絶縁膜を充分厚くして、クロストークの発生を抑え様と
する試みは概ね有効であるが、自段の走査線の影響だけ
は完全には除去出来ない。However, the prior art has the following problems. That is, as described above, the occurrence of crosstalk is feared by overlapping the pixel electrode with the signal line or the scanning line, but the influence of the scanning line of its own stage is particularly remarkable. Therefore, it is generally effective to attempt to suppress the occurrence of crosstalk by making the insulating film deposited on the signal line sufficiently thick, but it is not possible to completely remove the influence of the scanning line in its own stage.
【０００６】[0006]
【課題を解決するための手段】本発明は以上の様な問題
点を解決するものであり、信号線上に絶縁膜を堆積した
後画素電極を形成し、これを信号線や走査線と重ね合わ
せて、開口率の向上を図り、またこれら信号線や走査線
を遮光性材料で形成する事で、ＢＳパターンを省略しよ
うとする場合に於て、画素電極を自段の走査線だけとは
重ね合わせない様にし、これによってクロストークの発
生を防止しようとするものである。SUMMARY OF THE INVENTION The present invention solves the problems as described above, in which a pixel electrode is formed after depositing an insulating film on a signal line, and the pixel electrode is superposed on the signal line or the scanning line. In the case where the BS pattern is to be omitted by improving the aperture ratio and forming these signal lines and scanning lines with a light-shielding material, the pixel electrode is not overlapped with the scanning line of its own stage. It is intended to prevent the occurrence of crosstalk by not matching them.
【０００７】加えて、ＢＳパターンを自段の走査線と画
素電極のすき間を塞ぐ様に形成して、コントラストの劣
化を抑え様とするものである。In addition, the BS pattern is formed so as to close the gap between the scanning line and the pixel electrode of its own stage so as to suppress the deterioration of contrast.
【０００８】[0008]
【作用】本発明によって、開口率の向上、コントラスト
の低下防止、クロストークの防止が同時に実現でき、優
れた画質の液晶表示装置の提供が可能となった。According to the present invention, it is possible to improve the aperture ratio, prevent the deterioration of contrast, and prevent crosstalk at the same time, and it is possible to provide a liquid crystal display device having excellent image quality.
【０００９】[0009]
（実施例１）本発明の実施例を図５、及び図５のＸ−
Ｘ’間に於ける断面図である図６を用いて説明する。ガ
ラス、石英、サファイア等の基板５０１上に不純物を添
加した多結晶シリコン等のＮ+ シリコン薄膜からなるソ
ース領域５０２・ドレイン領域５０３が形成されてい
る。これらのソース領域５０２・ドレイン領域５０３の
上側に接して、この両者を結ぶ様に多結晶シリコン等の
シリコン薄膜からなるチャネル領域５０４が設けられて
いる。これら全体をシリコン酸化膜等の絶縁膜から成る
ゲート絶縁膜５０５が被覆しており、この上に金属、透
明導電膜等から成るゲート電極、兼走査線５０６、５０
７が形成されている。この上に、シリコン酸化膜等の絶
縁膜から成る層間絶縁膜５０８が被膜しており、コンタ
クト・ホール５０９を介して、金属、透明導電膜等から
成る信号線５１０、５１１がソース領域５０２と接続さ
れている。この上に、第二の層間絶縁膜５１２が堆積さ
れ、第二のコンタクト・ホール５１３を介して、画素電
極５１４がドレイン領域５０３と接続されている。ま
た、画素電極は信号線５１０、５１１、走査線５０７上
に延びており開口率を向上させているが、自段の走査線
５０６上には、延びておらずこれによってクロストーク
を防いでいる。(Embodiment 1) An embodiment of the present invention is shown in FIGS.
This will be described with reference to FIG. 6, which is a sectional view taken along the line X ′. A source region 502 and a drain region 503 are formed on a substrate 501 made of glass, quartz, sapphire, etc., which is made of an N + silicon thin film made of impurity-doped polycrystalline silicon or the like. A channel region 504 made of a silicon thin film such as polycrystalline silicon is provided so as to be in contact with the upper side of the source region 502 and the drain region 503 so as to connect them. The whole is covered with a gate insulating film 505 made of an insulating film such as a silicon oxide film, and a gate electrode made of a metal, a transparent conductive film, etc., and the scanning lines 506, 50 are also formed thereon.
7 are formed. An interlayer insulating film 508 made of an insulating film such as a silicon oxide film is coated on this, and signal lines 510 and 511 made of metal, a transparent conductive film, or the like are connected to the source region 502 through a contact hole 509. Has been done. A second interlayer insulating film 512 is deposited on this, and the pixel electrode 514 is connected to the drain region 503 through the second contact hole 513. Further, the pixel electrode extends over the signal lines 510 and 511 and the scanning line 507 to improve the aperture ratio, but does not extend over the scanning line 506 of its own stage, thereby preventing crosstalk. .
【００１０】（実施例２）本発明の実施例を図７、及び
図７のＸ−Ｘ’間に於ける断面図である図８を用いて説
明する。ガラス、石英、サファイア等の基板７０１上に
不純物を添加した多結晶シリコン等のＮ+ シリコン薄膜
からなるソース領域７０２・ドレイン領域７０３が形成
されている。これらのソース領域７０２・ドレイン領域
７０３に接して、この両者を結ぶ様に多結晶シリコン等
のシリコン薄膜からなるチャネル領域７０４が設けられ
ている。これら全体をシリコン酸化膜等の絶縁膜から成
るゲート絶縁膜７０５が被覆しており、この上に金属、
透明導電膜等から成るゲート電極、兼走査線７０６、７
０７が形成されている。この上に、シリコン酸化膜等の
絶縁膜から成る層間絶縁膜７０８が被膜しており、コン
タクト・ホール７０９を介して、金属、透明導電膜等か
ら成る信号線７１０、７１１がソース領域７０２と、ド
レイン電極７１２がドレイン領域７０３と接続されてい
る。この上に、ポリイミド膜７１３が堆積され、第二の
コンタクト・ホール７１４を介して、画素電極７１５が
ドレイン電極７１２と接続されている。また、画素電極
は信号線７１０、７１１、走査線７０７上に延びており
開口率を向上させているが、自段の走査線７０６上に
は、延びておらずこれによってクロストークを防いでい
る。この様にして、アクティブ・マトリクス側が完成す
る。一方、対向基板７１６上にはＢＳパターン７１７、
絶縁膜７１８、対向電極７１９が設けられ、アクティブ
・マトリクス側基板と対向し、その間に液晶７２０が封
入されている。この時、ＢＳパターン７１７は画素電極
７１５と自段の走査電極７０６とのすき間部分を塞ぐ如
く形成されている。(Embodiment 2) An embodiment of the present invention will be described with reference to FIG. 7 and FIG. 8 which is a sectional view taken along line XX 'in FIG. A source region 702 and a drain region 703 are formed on a substrate 701 such as glass, quartz, or sapphire, which is made of an N + silicon thin film such as polycrystalline silicon to which impurities are added. A channel region 704 made of a silicon thin film such as polycrystalline silicon is provided so as to be in contact with the source region 702 and the drain region 703 so as to connect them. The whole is covered with a gate insulating film 705 made of an insulating film such as a silicon oxide film, on which a metal,
A gate electrode made of a transparent conductive film and scanning lines 706 and 7
07 are formed. An interlayer insulating film 708 made of an insulating film such as a silicon oxide film is coated on this, and signal lines 710 and 711 made of a metal, a transparent conductive film, or the like are provided to the source region 702 via a contact hole 709. The drain electrode 712 is connected to the drain region 703. A polyimide film 713 is deposited thereon, and the pixel electrode 715 is connected to the drain electrode 712 via the second contact hole 714. The pixel electrode extends on the signal lines 710 and 711 and the scanning line 707 to improve the aperture ratio, but does not extend on the scanning line 706 of its own stage, thereby preventing crosstalk. . In this way, the active matrix side is completed. On the other hand, the BS pattern 717,
An insulating film 718 and a counter electrode 719 are provided, face the active matrix side substrate, and a liquid crystal 720 is sealed between them. At this time, the BS pattern 717 is formed so as to close the gap between the pixel electrode 715 and the scanning electrode 706 of its own stage.
【００１１】[0011]
【発明の効果】本発明を用いる事により、開口率が大き
く出来ると共に、コントラストの低下防止、クロストー
クの防止も同時に実現でき、優れた画質の液晶表示装置
の提供が可能となった。EFFECTS OF THE INVENTION By using the present invention, it is possible to provide a liquid crystal display device having an excellent image quality, since it is possible to increase the aperture ratio and simultaneously prevent deterioration of contrast and crosstalk.
【図１】 従来型のアクティブマトリクス液晶表示装置
に於ける一画素部分の例を表す図である。FIG. 1 is a diagram illustrating an example of a pixel portion in a conventional active matrix liquid crystal display device.
【図２】 図１のＸ−Ｘ’間に於ける断面図である。FIG. 2 is a cross-sectional view taken along line X-X ′ in FIG.
【図３】 従来型のアクティブマトリクス液晶表示装置
に於ける一画素部分の他の例を表す図である。FIG. 3 is a diagram showing another example of a pixel portion in a conventional active matrix liquid crystal display device.
【図４】 図３のＸ−Ｘ’間に於ける断面図である。FIG. 4 is a cross-sectional view taken along line X-X ′ in FIG.
【図５】 本発明の実施例を示す、アクティブマトリク
ス液晶表示装置に於ける一画素部分の例を表す図であ
る。FIG. 5 is a diagram showing an example of a pixel portion in an active matrix liquid crystal display device showing an embodiment of the present invention.
【図６】 図５のＸ−Ｘ’間に於ける断面図である。6 is a cross-sectional view taken along line X-X ′ of FIG.
【図７】 本発明の他の実施例を示す、アクティブマト
リクス液晶表示装置に於ける一画素部分の例を表す図で
ある。FIG. 7 is a diagram showing an example of one pixel portion in an active matrix liquid crystal display device showing another embodiment of the present invention.
【図８】 図７のＸ−Ｘ’間に於ける断面図である。8 is a cross-sectional view taken along line X-X 'in FIG.
１１，３１，５０１，７０１・・・基板 １２，３２，５０２，７０２・・・ソース領域 １３，３３，５０３，７０３・・・ドレイン領域 １４，３４，５０４，７０４・・・チャネル領域 １５，３５，５０５，７０５・・・ゲート絶縁膜 １６，３６，５０６，５０７，７０６，７０７・・・ゲ
ート電極及び走査線 １７，３７，５０８，７０８・・・層間絶縁膜 １８，３８，５０９，７０９・・・コンタクト・ホール １９，３９，５１０，５１１，７１０，７１１・・・信
号線 ７１３・・・ポリイミド膜 ２０，４２，５１４，７１５・・・画素電極 ４０，５１２・・・第二の層間絶縁膜 ４１，５１３，７１４・・・第二のコンタクト・ホール ７１２・・・ドレイン電極む ２１，７１７・・・ＢＳパターン ２４，７１６・・・対向基板 ２３，７１８・・・絶縁膜 ２２，７１９・・・対向電極 ２５，７２０・・・液晶11, 31, 501, 701 ... Substrate 12, 32, 502, 702 ... Source region 13, 33, 503, 703 ... Drain region 14, 34, 504, 704 ... Channel region 15, 35 , 505, 705 ... Gate insulating film 16, 36, 506, 507, 706, 707 ... Gate electrode and scanning line 17, 37, 508, 708 ... Interlayer insulating film 18, 38, 509, 709. ..Contact holes 19, 39, 510, 511, 710, 711 ... Signal line 713 ... Polyimide film 20, 42, 514, 715 ... Pixel electrode 40, 512 ... Second interlayer insulation Films 41, 513, 714 ... Second contact hole 712 ... Drain electrode 21,717 ... BS pattern 24, 716 ... Counter substrate 2 3,718 ... Insulating film 22,719 ... Counter electrode 25,720 ... Liquid crystal
Claims (7)
と、第一の絶縁膜を介して前記走査線上に形成され、且
つ前記走査線と直交して平行に配置された複数の信号線
と、前記走査線と前記信号線の各交点に、前記信号線と
接続されたソース領域、前記走査線と接続されたゲート
電極、そしてドレイン領域とそれに接続された画素電極
を具備した薄膜トランジスタが配置されているアクティ
ブ・マトリックス型液晶表示装置に於て、前記画素電極
は前記信号線上に形成された第二の絶縁膜上に形成され
ており、且つ前記画素電極は前記信号線、及び前段の前
記信号線上と重なり合っている事を特徴とする液晶表示
装置。1. A plurality of scanning lines arranged in parallel on a substrate and a plurality of signals formed on the scanning line via a first insulating film and arranged in parallel to each other at right angles to the scanning line. A thin film transistor having a line, a source region connected to the signal line, a gate electrode connected to the scanning line, and a drain region and a pixel electrode connected to the source region at each intersection of the scanning line and the signal line; In the arranged active matrix type liquid crystal display device, the pixel electrode is formed on a second insulating film formed on the signal line, and the pixel electrode is formed on the signal line and the previous stage. A liquid crystal display device, characterized in that it overlaps with the signal line.
異なる材料からなる事を特徴とする請求項１記載の液晶
表示装置。2. The liquid crystal display device according to claim 1, wherein the first insulating film and the second insulating film are made of different materials.
を特徴とする請求項１記載の液晶表示装置。3. The liquid crystal display device according to claim 1, wherein the second insulating film is an organic insulating film.
事を特徴とする請求項１記載の液晶表示装置。4. The liquid crystal display device according to claim 1, wherein the second insulating film is a polyimide film.
形成された画素電極との接続は、前記第一の絶縁膜上に
形成されたドレイン電極を介して行なわれている事を特
徴とする請求項１記載の液晶表示装置。5. The connection between the drain region and the pixel electrode formed on the second insulating film is performed through the drain electrode formed on the first insulating film. The liquid crystal display device according to claim 1.
からなる事を特徴とする請求項１記載の液晶表示装置。6. The liquid crystal display device according to claim 1, wherein the signal line and the scanning line are made of a light-shielding material.
を塞ぐ如く、遮光性材料からなるパターンを形成する事
を特徴とする請求項１記載の液晶表示装置。7. The liquid crystal display device according to claim 1, wherein a pattern made of a light-shielding material is formed so as to close a gap between the pixel electrode and the scanning line of its own stage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33071192A JPH06175158A (en) | 1992-12-10 | 1992-12-10 | Liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33071192A JPH06175158A (en) | 1992-12-10 | 1992-12-10 | Liquid crystal display |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06175158A true JPH06175158A (en) | 1994-06-24 |
Family
ID=18235712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33071192A Pending JPH06175158A (en) | 1992-12-10 | 1992-12-10 | Liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06175158A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0745885A2 (en) * | 1995-05-31 | 1996-12-04 | Xerox Corporation | An integrated dark matrix for an active matrix liquid crystal display and manufacturing method |
| JPH10502462A (en) * | 1994-06-30 | 1998-03-03 | ハネウエル・インコーポレーテッド | Large aperture AMLCD architecture |
| JP2002014628A (en) * | 2000-04-27 | 2002-01-18 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacturing method |
| US6930741B2 (en) * | 2000-09-28 | 2005-08-16 | Nec Lcd Technologies, Ltd. | LCD device having scanning lines and common lines |
| JP2011197681A (en) * | 2000-04-27 | 2011-10-06 | Semiconductor Energy Lab Co Ltd | El display |
-
1992
- 1992-12-10 JP JP33071192A patent/JPH06175158A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10502462A (en) * | 1994-06-30 | 1998-03-03 | ハネウエル・インコーポレーテッド | Large aperture AMLCD architecture |
| EP0745885A2 (en) * | 1995-05-31 | 1996-12-04 | Xerox Corporation | An integrated dark matrix for an active matrix liquid crystal display and manufacturing method |
| EP0745885A3 (en) * | 1995-05-31 | 1998-05-06 | Xerox Corporation | An integrated dark matrix for an active matrix liquid crystal display and manufacturing method |
| JP2011197681A (en) * | 2000-04-27 | 2011-10-06 | Semiconductor Energy Lab Co Ltd | El display |
| JP2002014628A (en) * | 2000-04-27 | 2002-01-18 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacturing method |
| US8178880B2 (en) | 2000-04-27 | 2012-05-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
| JP2012133376A (en) * | 2000-04-27 | 2012-07-12 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| US9099361B2 (en) | 2000-04-27 | 2015-08-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
| JP2016106243A (en) * | 2000-04-27 | 2016-06-16 | 株式会社半導体エネルギー研究所 | Display device |
| US9419026B2 (en) | 2000-04-27 | 2016-08-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
| JP2017049592A (en) * | 2000-04-27 | 2017-03-09 | 株式会社半導体エネルギー研究所 | Display |
| JP2017161911A (en) * | 2000-04-27 | 2017-09-14 | 株式会社半導体エネルギー研究所 | Display device |
| US9780124B2 (en) | 2000-04-27 | 2017-10-03 | Semiconductor Energy Laboratory Co., Ltd. | Display device including pixel comprising first transistor second transistor and light-emitting element |
| US6930741B2 (en) * | 2000-09-28 | 2005-08-16 | Nec Lcd Technologies, Ltd. | LCD device having scanning lines and common lines |
| US7626671B2 (en) | 2000-09-28 | 2009-12-01 | Nec Lcd Technologies, Ltd. | LCD device having scanning lines and common lines |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100262953B1 (en) | Lcd and manufacturing method of the same | |
| US6373546B1 (en) | Structure of a liquid crystal display and the method of manufacturing the same | |
| US6088072A (en) | Liquid crystal display having a bus line formed of two metal layers and method of manufacturing the same | |
| US5966190A (en) | Array substrate for displaying device with capacitor lines having particular connections | |
| JP2760462B2 (en) | Active matrix substrate | |
| JPH07128685A (en) | Liquid crystal display device | |
| JPH10319431A (en) | Thin film transistor array substrate | |
| US6300987B1 (en) | Thin film transistor array panels for liquid crystal displays | |
| US6545730B1 (en) | Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same | |
| US6084653A (en) | Liquid crystal display having an active matrix substrate with thermosetting inter-layer insulating film with a thickness of greater than 2 μM | |
| JP3326832B2 (en) | Liquid crystal display | |
| JPH08160454A (en) | Liquid crystal display device | |
| JPH06175158A (en) | Liquid crystal display | |
| JP2870075B2 (en) | Thin film transistor panel and liquid crystal display | |
| JPH03196020A (en) | Liquid crystal display device | |
| JPH0887034A (en) | Liquid crystal display and its production | |
| JP3591674B2 (en) | Liquid crystal display | |
| JPH0534679A (en) | Liquid crystal display device | |
| JP3312720B2 (en) | Liquid crystal display | |
| JPH06130415A (en) | Manufacture of tft matrix | |
| JP2950737B2 (en) | Active matrix substrate and manufacturing method thereof | |
| JPH06160900A (en) | Liquid crystal display device | |
| JPH09274202A (en) | Thin-film transistor array substrate | |
| KR100237680B1 (en) | Lcd device and its manufacturing method | |
| JP2000066237A (en) | Liquid crystal display device |