JPH06169112A - Superconducting element and manufacture thereof - Google Patents

Superconducting element and manufacture thereof

Info

Publication number
JPH06169112A
JPH06169112A JP4321583A JP32158392A JPH06169112A JP H06169112 A JPH06169112 A JP H06169112A JP 4321583 A JP4321583 A JP 4321583A JP 32158392 A JP32158392 A JP 32158392A JP H06169112 A JPH06169112 A JP H06169112A
Authority
JP
Japan
Prior art keywords
channel layer
insulating film
gate insulating
superconducting
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4321583A
Other languages
Japanese (ja)
Inventor
Koichi Mizuno
紘一 水野
Hideaki Adachi
秀明 足立
Hiroshi Ichikawa
洋 市川
Kentaro Setsune
謙太郎 瀬恒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP4321583A priority Critical patent/JPH06169112A/en
Priority to US08/080,726 priority patent/US5828079A/en
Priority to EP93110358A priority patent/EP0577074B1/en
Priority to DE69328567T priority patent/DE69328567T2/en
Priority to DE69306316T priority patent/DE69306316T2/en
Priority to EP95118306A priority patent/EP0701292B1/en
Publication of JPH06169112A publication Critical patent/JPH06169112A/en
Pending legal-status Critical Current

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  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

PURPOSE:To obtain a three-terminal superconducting element, on which the normal conductive resistance or a zero resistance temperature of a channel layer changes when voltage is applied to a gate electrode, and this change is controlled even after removal of the applied voltage by using the ferroelectric material for the gate electrode and a superconducting element and an oxide superconducting body for a channel layer. CONSTITUTION:An oxide superconducting thin film is used as a channel layer 1, a ferroelectric gate insulating film 2, which is brought into contact with the channel layer 1, a source electrode 4 and a drain electrode 5 are provided, and a gate electrode 3, which comes in contact with the gate insulating film 2, is provided. A Bi oxide superconducting material Bi2-Sr2-Sr1-Cu2-Ox (x indicates an optional natural number) single crystal of 2212 phase cleaved in the thickness of 0.5mm, for example, is used as the channel layer, and a Pb0.9 La0.1TiO3 thin film of 400nm in thickness, which is formed by rf sputtering method, is used as the gate insulating film 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は超伝導応用技術に関し、
特にゲート電極に印加する電圧によって素子特性を制御
する電界効果型の超伝導素子に関するものである。
BACKGROUND OF THE INVENTION The present invention relates to a superconducting application technique,
In particular, the present invention relates to a field effect type superconducting device in which device characteristics are controlled by a voltage applied to a gate electrode.

【0002】[0002]

【従来の技術】従来、金属系の超伝導体を用いた超伝導
素子といえば、弱結合型ジョセフソン素子、トンネル接
合型ジョセフソン素子、超伝導体の超伝導遷移を利用す
るボロメータ等があった。また、超伝導三端子素子とし
て、半導体−超伝導体接合を利用したジョセフソン電界
効果素子(JOFET)、超伝導薄膜をトランジスタの
ベース電極に使用するSUBSIT、非平衡超伝導状態
を制御するQUITERON等が提案され、原理的研究
及び素子試作がなされた。これらの素子は超高速スイッ
チ、超高周波信号処理用の素子として期待されている
が、現在のところまだ期待通りの特性は得られていな
い。
2. Description of the Related Art Conventionally, a superconducting element using a metal-based superconductor includes a weak coupling Josephson element, a tunnel junction Josephson element, a bolometer utilizing superconducting transition of a superconductor, and the like. It was Also, as a superconducting three-terminal element, a Josephson field effect element (JOFET) using a semiconductor-superconductor junction, SUBSIT using a superconducting thin film as a base electrode of a transistor, QUITERON controlling a non-equilibrium superconducting state, etc. Was proposed, and fundamental research and device prototype were made. These elements are expected as elements for ultra-high-speed switches and ultra-high-frequency signal processing, but at present, expected characteristics have not been obtained.

【0003】一方、近年発見された酸化物超伝導体の中
には、その超伝導遷移温度が液体窒素温度(77.3ケ
ルビン)を越えるものがあり、超伝導体の応用分野を大
きく広げることとなった。この酸化物超伝導体の素子応
用については、酸化物超伝導体を二つに割り、再びわず
かに接触させたジョセフソン素子、酸化物超伝導体を薄
膜にし、小さなくびれをつけたブリッジ型ジョセフソン
素子、酸化物超伝導体間をAu、Ag等の貴金属で接続
したジョセフソン素子等、弱結合型のジョセフソン素子
の試作例が大半を占めている。また、金属超伝導体を用
いた超伝導三端子素子と同じ原理による素子も提案され
てはいるが、その特性確認はいまだされていない。
On the other hand, some oxide superconductors recently discovered have a superconducting transition temperature exceeding the liquid nitrogen temperature (77.3 Kelvin), which greatly expands the field of application of superconductors. Became. As for the device application of this oxide superconductor, the Josephson device, which was made by splitting the oxide superconductor into two and making a slight contact again, made a thin film of the oxide superconductor and made a bridge-type Joseph with a small constriction. Most of the prototypes of weak-coupling Josephson devices, such as the Sonson device and the Josephson device in which oxide superconductors are connected by a noble metal such as Au or Ag. Further, although an element based on the same principle as a superconducting three-terminal element using a metal superconductor has been proposed, its characteristics have not been confirmed yet.

【0004】[0004]

【発明が解決しようとしている課題】超伝導体は、基本
的には完全導体であり、電界を印加できない(電位差を
与えることはできない)。しかし、超伝導転移点付近の
状態は超伝導状態と、常伝導状態の混合状態と考えら
れ、電界の印加が可能である。この様な状態の時に印加
電界の大きさを変化させると、前記した混合状態のうち
の常伝導状態にある準粒子(常伝導電子)が電気的影響
を受ける可能性がある。金属超伝導体(金属)の場合、
キャリア密度が大きく、通常の半導体のように電界効果
が得られにくいためこの様な現象を利用した素子は実現
が難しいと考えられる。一方、酸化物超伝導体はキャリ
ア密度が金属超伝導体に比べ小さく(半導体に近く)電
界効果が有効に生じると考えられる。しかしながら、実
際に効果的に電圧制御によって超伝導素子の特性を制御
した例は少ない。
A superconductor is basically a perfect conductor and cannot apply an electric field (cannot give a potential difference). However, the state near the superconducting transition point is considered to be a mixed state of a superconducting state and a normal conducting state, and an electric field can be applied. When the magnitude of the applied electric field is changed in such a state, the quasi-particles (normal conduction electrons) in the normal conduction state among the mixed states described above may be electrically affected. In the case of metal superconductor (metal),
Since the carrier density is high and it is difficult to obtain the electric field effect unlike ordinary semiconductors, it is considered difficult to realize an element utilizing such a phenomenon. On the other hand, it is considered that the oxide superconductor has a smaller carrier density than a metal superconductor (close to a semiconductor) and an electric field effect is effectively generated. However, there are few examples in which the characteristics of the superconducting device are actually and effectively controlled by voltage control.

【0005】一方、超伝導体を用いた論理回路では、ス
イッチング機能を有する超伝導素子とともに、メモリー
機能を有する素子が必要となる。従来はこの機能を複数
のジョセフソン素子を用いた複合超伝導回路で磁束保持
機能を利用したものが提案されていた。しかしながらこ
の回路では、素子面積が大きく高集積化が困難であり、
単体の素子によって、さらには異なる原理によってメモ
リー機能を実現する超伝導素子が望まれていた。さら
に、変調効率を高め、かつ作製が容易な超伝導三端子素
子が望まれていた。
On the other hand, in a logic circuit using a superconductor, an element having a memory function is required in addition to a superconducting element having a switching function. Conventionally, a composite superconducting circuit using a plurality of Josephson elements, which uses this function as a magnetic flux holding function, has been proposed. However, in this circuit, the device area is large and high integration is difficult,
There has been a demand for a superconducting device that realizes a memory function by a single device and further by a different principle. Furthermore, a superconducting three-terminal element that has high modulation efficiency and is easy to manufacture has been desired.

【0006】本発明は、前記従来の問題を解決するた
め、外部電界で超伝導特性または常伝導特性等の電気的
特性を変化できるチャネル層を用い、さらにゲート絶縁
膜に強誘電性を有する材料を用いることによって、電界
効果によって特性制御可能な、メモリー機能をも実現で
きる新規な超伝導三端子素子を提供することを目的とす
る。また、高い再現性と信頼性で、しかも変調効率の高
い超伝導三端子素子を作製する製造方法を提供すること
を目的とする。
In order to solve the above-mentioned conventional problems, the present invention uses a channel layer whose electric characteristics such as superconducting characteristics or normal conducting characteristics can be changed by an external electric field, and a material having ferroelectricity for a gate insulating film. It is an object of the present invention to provide a novel superconducting three-terminal element which can realize a memory function and whose characteristics can be controlled by the electric field effect. Another object of the present invention is to provide a manufacturing method for manufacturing a superconducting three-terminal element having high reproducibility and reliability and high modulation efficiency.

【0007】[0007]

【課題を解決するための手段】前記目的を達成するた
め、本発明の第1の超伝導素子は、チャネル層と、前記
チャネル層に接するソース電極とドレイン電極とゲート
絶縁膜、および前記ゲート絶縁膜に接するゲート電極を
少なくとも備えた超伝導素子であって、前記チャネル層
が少なくとも酸化物超伝導体を含み、かつ前記ゲート絶
縁膜が強誘電性を有する膜であることを特徴とする。
In order to achieve the above object, a first superconducting element of the present invention comprises a channel layer, a source electrode and a drain electrode in contact with the channel layer, a gate insulating film, and the gate insulating layer. A superconducting device having at least a gate electrode in contact with the film, wherein the channel layer contains at least an oxide superconductor, and the gate insulating film is a film having ferroelectricity.

【0008】前記構成においては、チャネル層、ゲート
絶縁膜、およびゲート電極が薄膜で形成され、基体上に
積層構造で形成されていることが好ましい。。次に本発
明の第2の超伝導素子は、電気伝導層と、前記電気伝導
層に接する強誘電性を有するゲート絶縁膜と、前記ゲー
ト絶縁膜に接するチャネル層と、前記チャネル層に接す
るソース電極とドレイン電極とゲート電極を少なくとも
備えた超伝導素子であって、前記チャネル層が少なくと
も酸化物超伝導体を含み、かつ前記ゲート絶縁膜が強誘
電性を有する膜であることを特徴とする。
In the above structure, it is preferable that the channel layer, the gate insulating film, and the gate electrode are formed of a thin film and are formed in a laminated structure on the substrate. . Next, a second superconducting element of the present invention comprises an electrically conductive layer, a gate insulating film having ferroelectricity in contact with the electrically conductive layer, a channel layer in contact with the gate insulating film, and a source in contact with the channel layer. A superconducting device including at least an electrode, a drain electrode, and a gate electrode, wherein the channel layer includes at least an oxide superconductor, and the gate insulating film is a film having ferroelectricity. .

【0009】前記構成においては、電気伝導層、ゲート
絶縁膜、チャネル層、及びゲート電極が薄膜で形成さ
れ、基体上に積層構造で形成されていることが好まし
い。前記構成においては、ゲート電極が少なくとも2つ
であることが好ましい。
In the above structure, it is preferable that the electric conductive layer, the gate insulating film, the channel layer, and the gate electrode are formed of thin films and are formed in a laminated structure on the base. In the above structure, it is preferable that the number of gate electrodes is at least two.

【0010】また前記構成においては、チャネル層が、
少なくともBiを含む酸化物超伝導体を含み、かつゲー
ト絶縁膜が、少なくともPbを含む強誘電体またはBi
を含む強誘電体を含むことが好ましい。
In the above structure, the channel layer is
A ferroelectric or Bi containing an oxide superconductor containing at least Bi and having a gate insulating film containing at least Pb.
It is preferable to include a ferroelectric substance containing.

【0011】また前記構成においては、チャネル層が、
少なくとも前記式(化1)で表される酸化物超伝導体ま
たは酸化物常伝導体を含み、かつゲート絶縁膜が、少な
くとも(Pb1-x Lax )(Zr1-y Tiy 1-x/4
3 (0≦x≦0.2、0≦y≦1.0)で表される強誘
電体、またはBi3 Ti4 12で表される強誘電体を含
むことが好ましい。
In the above structure, the channel layer is
The gate insulating film contains at least (Pb 1-x La x ) (Zr 1-y Ti y ) 1 - containing at least an oxide superconductor or an oxide normal conductor represented by the above formula (Formula 1). x / 4 O
It is preferable to include a ferroelectric represented by 3 (0 ≦ x ≦ 0.2, 0 ≦ y ≦ 1.0) or a ferroelectric represented by Bi 3 Ti 4 O 12 .

【0012】また前記構成においては、チャネル層が、
少なくともCuとBiを含む酸化物超伝導体とCuとB
iを含む酸化物とからなる積層膜から形成されているこ
とが好ましい。
In the above structure, the channel layer is
An oxide superconductor containing at least Cu and Bi, and Cu and B
It is preferably formed of a laminated film made of an oxide containing i.

【0013】次に本発明の超伝導素子の第1の製造方法
は、基体上にチャネル層を成膜し、前記チャネル層上に
ゲート絶縁膜と、さらに前記ゲート絶縁膜上にゲート電
極を成膜し、その積層膜を用いて超伝導素子を作製する
という構成を備えたものである。
Next, in the first method for manufacturing a superconducting device of the present invention, a channel layer is formed on a substrate, a gate insulating film is formed on the channel layer, and a gate electrode is further formed on the gate insulating film. A film is formed and a superconducting element is manufactured using the laminated film.

【0014】前記構成においては、チャネル層の成膜温
度が少なくとも600℃以上であり、かつ、ゲート絶縁
膜の成膜温度が600℃以下であることが好ましい。ま
た前記構成においては、少なくともチャネル層、ゲート
絶縁膜、ゲート電極を同一真空中で成膜することが好ま
しい。
In the above structure, it is preferable that the film forming temperature of the channel layer is at least 600 ° C. or higher and the film forming temperature of the gate insulating film is 600 ° C. or lower. Further, in the above structure, at least the channel layer, the gate insulating film, and the gate electrode are preferably formed in the same vacuum.

【0015】次に本発明の超伝導素子の第2の製造方法
は、基体上に電気伝導層を成膜し、前記電気伝導層上に
ゲート絶縁膜を成膜し、前記ゲート絶縁膜上にチャネル
層を成膜し、前記チャネル層上にゲート電極を成膜し、
その積層膜を用いて超伝導素子を作製するという構成を
備えたものである。
Next, in the second method for manufacturing a superconducting element of the present invention, an electric conductive layer is formed on a substrate, a gate insulating film is formed on the electric conductive layer, and the gate insulating film is formed on the gate insulating film. Forming a channel layer, forming a gate electrode on the channel layer,
It has a structure in which a superconducting element is manufactured using the laminated film.

【0016】前記構成においては、ゲート絶縁膜の成膜
温度が600℃以下であり、しかも前記ゲート絶縁膜を
成膜後、基板温度を600℃以上に加熱し、チャネル層
を成膜することが好ましい。
In the above structure, the film forming temperature of the gate insulating film is 600 ° C. or lower, and after forming the gate insulating film, the substrate temperature is heated to 600 ° C. or higher to form the channel layer. preferable.

【0017】また前記構成においては、電気伝導層、ゲ
ート絶縁膜、チャネル層、ゲート電極を同一真空中で成
膜することが好ましい。
Further, in the above structure, it is preferable that the electric conductive layer, the gate insulating film, the channel layer and the gate electrode are formed in the same vacuum.

【0018】[0018]

【作用】前記した本発明の構成によれば、チャネル層
と、前記チャネル層に接するソース電極とドレイン電極
とゲート絶縁膜、および前記ゲート絶縁膜に接するゲー
ト電極を少なくとも備えた超伝導素子であって、前記チ
ャネル層が少なくとも酸化物超伝導体を含み、かつ前記
ゲート絶縁膜が強誘電性を有する膜であることにより、
電界効果によって特性制御可能な、メモリー機能も有す
る超伝導三端子素子を実現できる。すなわち、電界が印
加されるゲート電極に強誘電性を有する材料を用い、さ
らにチャネル層に酸化物超伝導体を用いた超伝導素子に
おいて、ゲート電極に電圧を印加した場合、チャネル層
の常伝導抵抗、もしくはゼロ抵抗温度が変化する。ま
た、印加電圧を取り除いた後もこの変化が持続する。
According to the above-described structure of the present invention, a superconducting element including at least a channel layer, a source electrode and a drain electrode in contact with the channel layer, a gate insulating film, and a gate electrode in contact with the gate insulating film is provided. Then, the channel layer contains at least an oxide superconductor, and the gate insulating film is a film having ferroelectricity,
It is possible to realize a superconducting three-terminal device which has a memory function and whose characteristics can be controlled by the field effect. That is, in a superconducting device in which a ferroelectric material is used for the gate electrode to which an electric field is applied and an oxide superconductor is used for the channel layer, when a voltage is applied to the gate electrode, the normal conduction of the channel layer Resistance or zero resistance temperature changes. Moreover, this change continues even after the applied voltage is removed.

【0019】酸化物超伝導体は、キャリア密度が小さ
く、さらにそのキャリア密の大きさによって、超伝導遷
移特性等、種々の超伝導特性、超伝導遷移温度より高温
での常伝導抵抗等常伝導特性が変化する。本発明のチャ
ネル層は、主として酸化物超伝導体からなり、ゲート絶
縁膜を介して印加された電圧によってキャリア密度等が
変化し、電気的特性が変化していると考えられる。ま
た、印加電圧を取り除いた後にも強誘電体の残留分極の
作用で、この変化が持続していると考えられる。
Oxide superconductors have a low carrier density, and depending on the size of the carrier density, various superconducting properties such as superconducting transition properties, normal conducting properties such as normal conducting resistance at temperatures higher than the superconducting transition temperature. The characteristics change. The channel layer of the present invention is mainly made of an oxide superconductor, and it is considered that the carrier density and the like are changed by the voltage applied through the gate insulating film, and the electric characteristics are changed. Moreover, it is considered that this change is maintained by the action of the remanent polarization of the ferroelectric even after the applied voltage is removed.

【0020】一方、ゲート絶縁膜に接して電気伝導層を
設けると(ゲート絶縁膜に対して電気伝導層をグランド
プレーンとすると)、より簡便な作製方法で超伝導素子
が作製できる。これは電気伝導層がグランドプレーンと
して働き、ゲート絶縁膜上のチャネル層上に2つ以上の
ゲート電極を形成できること、またその際に、一度の作
製行程で作製できるためである。また、この構成では、
集積化を図るため絶縁性の基体上に素子を薄膜化し、し
かも、いくつかのチャネル層を並列化する際、とくに作
製プロセスを複雑にしなくてすむ。また、ゲート電極上
にチャネル層を形成するため、チャネル層の電気的特
性、結晶性等の劣化が防げる。
On the other hand, when the electric conductive layer is provided in contact with the gate insulating film (when the electric conductive layer is the ground plane for the gate insulating film), the superconducting element can be manufactured by a simpler manufacturing method. This is because the electrically conductive layer functions as a ground plane, two or more gate electrodes can be formed on the channel layer on the gate insulating film, and in that case, the gate electrode can be manufactured in one manufacturing step. Also, with this configuration,
When thinning the device on an insulating substrate for the purpose of integration, and when several channel layers are arranged in parallel, the manufacturing process is not particularly complicated. Further, since the channel layer is formed on the gate electrode, deterioration of the electrical characteristics, crystallinity and the like of the channel layer can be prevented.

【0021】また一方で、前記の超伝導素子を薄膜化
し、基体上に作製すると、ゲート電極を薄膜化でき、ゲ
ート電極に対する同一の印加電圧に対して、実際にゲー
ト絶縁膜間にかかる電界強度を大きくでき、素子特性の
変調効率が向上する。
On the other hand, when the above-mentioned superconducting element is thinned and formed on the substrate, the gate electrode can be thinned, and the electric field strength actually applied between the gate insulating films can be applied to the same applied voltage to the gate electrode. Can be increased, and the modulation efficiency of element characteristics can be improved.

【0022】一方、これらの超伝導素子において、2つ
以上のゲート電極を形成した際、二つのゲート電極に接
する各々のチャネル層の電気的特性は相補的に変化させ
ることができ、実用上有効である。
On the other hand, in these superconducting devices, when two or more gate electrodes are formed, the electrical characteristics of each channel layer in contact with the two gate electrodes can be changed complementarily, which is practically effective. Is.

【0023】またゲート絶縁膜に接する全ての電極また
は薄膜層(電気伝導層、チャネル層、またはゲート電
極)を同一真空中で作製すると、大気に曝したことによ
る比誘電率の小さい表面劣化層をゲート絶縁膜上に形成
することがなく、素子特性の再現性、変調効率の向上に
有効である。また、各薄膜材料の作製温度を適宜最適な
条件とすることで、超伝導素子の再現性、信頼性、さら
には変調効率が向上できる。上記のような電界効果型超
伝導素子を構成する場合、チャネル層を構成する酸化物
超伝導体に、キャリア密度の小さい酸化物系の材料を用
い、各種の元素置換、または超伝導体と同系の酸化物薄
膜との積層構造(各種積層材料、積層順、積層周期等の
組合せ)によって超伝導性を制御できるので、特定の動
作温度において最も効率よく動作させ得る超伝導素子を
設計できる。
When all electrodes or thin film layers (electrically conductive layer, channel layer, or gate electrode) in contact with the gate insulating film are formed in the same vacuum, a surface-deteriorated layer having a small relative dielectric constant due to exposure to the atmosphere is formed. Since it is not formed on the gate insulating film, it is effective in improving the reproducibility of element characteristics and the modulation efficiency. Further, by appropriately setting the manufacturing temperature of each thin film material, the reproducibility, reliability and modulation efficiency of the superconducting element can be improved. When constructing a field effect superconducting device as described above, an oxide-based material with a low carrier density is used for the oxide superconductor that constitutes the channel layer, and various element substitutions or the same system as the superconductor are used. Since the superconductivity can be controlled by the laminated structure (combination of various laminating materials, laminating order, laminating period, etc.) with the oxide thin film, the superconducting element that can be operated most efficiently at a specific operating temperature can be designed.

【0024】また、積層膜をチャネル層に用いた場合、
構成される各薄膜、およびゲート絶縁膜まで含めて、同
種の結晶構造、格子定数をもつ材料を選択すると、各電
極、薄膜層が各々結晶性よく作製できるため、超伝導素
子の特性向上が可能となる。特にゲート絶縁膜は、薄く
しかも結晶性よく成膜できるため、チャネル層の電気的
特性の高性能化(高誘電率、ゲート絶縁膜の絶縁耐圧の
向上、リーク電流の減少等)の作用がある。
When the laminated film is used for the channel layer,
By selecting materials that have the same type of crystal structure and lattice constants, including each thin film and gate insulating film that are configured, each electrode and thin film layer can be made with good crystallinity, so the characteristics of superconducting devices can be improved. Becomes In particular, since the gate insulating film can be formed thin and with good crystallinity, it has the effect of improving the electrical characteristics of the channel layer (high dielectric constant, improving dielectric strength of the gate insulating film, reducing leak current, etc.). .

【0025】酸化物超伝導体は、その基本構造がペロブ
スカイト構造であり、それらをチャネル層に用いた場
合、強誘電性のゲート絶縁膜は、同じくペロブスカイト
構造をもつPbTiO3 系[(Pb1-x Lax )(Zr
1-y Tiy 1-x/4 3 などで表される]や、Bi層状
構造化合物であるBi3Ti412系などが、薄膜成長条
件、薄膜の特性などの観点から有効な取り合わせであ
る。とくに強誘電性のゲート絶縁膜に、PbTiO3
[(Pb1-x Lax )(Zr1-y Tiy 1-x/4 3
どで表される]や、Bi層状構造化合物であるBi3
412系などを用いる場合、基板温度を600℃以下
とすると組成ずれ(Pb、またはBi比率の低下)を抑
えることができ、良好な強誘電性が得られる。ここで、
電気伝導層上にゲート絶縁層、さらにその上にチャネル
層を積層する構造に於て、ゲート絶縁膜を600℃以下
の温度で成膜し、さらに基板温度を600℃以上に上げ
チャネル層を成膜しても、良好な強誘電性のゲート絶縁
膜が得られるとともに、チャネル層の超伝導性も良好な
ものが得られる。また、チャネル層としてBi系酸化物
を600℃以上で成膜し、その上にPbTiO3 系、ま
たはBi系強誘電体を、ゲート絶縁膜として作製する
際、基板温度を600℃以下にすると、チャネル層の結
晶性、さらには超伝導特性、電気特性を損なうことな
く、また、強誘電体においてはその結晶性、強誘電特
性、比誘電率などの電気的特性が良好なものが得られ
る。これら薄膜成長条件、薄膜の特性などの観点からB
i系酸化物と、Pb系強誘電体、Bi系強誘電体とは本
発明の目的に有効な取り合わせである。
The basic structure of an oxide superconductor is perovsk.
It has a skite structure, and if these are used for the channel layer,
In this case, the ferroelectric gate insulating film is the same perovskite.
PbTiO with structure3System [(Pb1-xLax) (Zr
1-yTiy)1-x / 4O3, Etc.] or Bi layered
Bi, a structural compound3TiFourO12Thin film growth
It is an effective combination from the viewpoints of properties, thin film characteristics, etc.
It Especially for the ferroelectric gate insulating film, PbTiO 33system
[(Pb1-xLax) (Zr1-yTiy)1-x / 4O 3Na
And the Bi layered structure compound Bi.3T
iFourO12When using a system, the substrate temperature is 600 ° C or less
In that case, compositional deviation (decrease in Pb or Bi ratio) is suppressed.
It is possible to obtain good ferroelectricity. here,
A gate insulating layer on the electrically conductive layer and a channel on it
In a structure in which layers are stacked, the gate insulating film is 600 ° C or less
Film formation at the temperature of, and raise the substrate temperature to 600 ℃ or more
Good ferroelectric gate insulation even when forming a channel layer
A film is obtained and the channel layer has good superconductivity.
Things are obtained. Further, as the channel layer, a Bi-based oxide is used.
Is deposited at 600 ° C or higher, and PbTiO3System
Or Bi-based ferroelectric as a gate insulating film
At this time, if the substrate temperature is set to 600 ° C. or lower, the channel layer is bonded.
Do not impair crystallinity, superconducting properties, and electrical properties.
In addition, the crystallinity and ferroelectric characteristics of ferroelectrics
With good electrical characteristics such as electrical conductivity and relative permittivity
It From the viewpoints of these thin film growth conditions and thin film characteristics, B
What are i-based oxides, Pb-based ferroelectrics, and Bi-based ferroelectrics?
It is an effective arrangement for the purpose of the invention.

【0026】さらに、ゲート絶縁膜上に2つのゲート電
極を狭い間隔で対向させて形成すると電極間ギャップを
小さくでき等化的に電界が大きくなり、電界効果を顕著
に大きくなる作用がある。
Further, when two gate electrodes are formed on the gate insulating film so as to face each other at a narrow interval, the gap between the electrodes can be reduced, and the electric field is increased by equalization, and the electric field effect is significantly increased.

【0027】また薄膜積層型の素子構造とすると、集積
化が可能で有るばかりでなく、上記のような積層型チャ
ネル層の設計において、また変調効率の高い薄いゲート
絶縁膜を作製する際において有効である。
The thin film laminated type device structure is not only capable of integration but also effective in designing the laminated type channel layer as described above and in producing a thin gate insulating film having high modulation efficiency. Is.

【0028】[0028]

【実施例】以下実施例を用いて本発明をさらに具体的に
説明する。本実施例の超伝導素子において、強誘電性を
有するゲート絶縁膜は、電界効果を保持する働きがあ
り、メモリー機能を有する超伝導素子を実現できる。こ
の素子は単独でメモリー素子として働くため、高集積化
に非常に有利である。さらに、ゲート電極を2つ以上有
する素子は相補的に働く素子を構成でき、論理演算回路
に有効である。
EXAMPLES The present invention will be described in more detail with reference to the following examples. In the superconducting element of this example, the gate insulating film having ferroelectricity has a function of retaining the electric field effect, and a superconducting element having a memory function can be realized. Since this element independently functions as a memory element, it is very advantageous for high integration. Furthermore, an element having two or more gate electrodes can form an element that works complementarily, which is effective for a logical operation circuit.

【0029】上記のような電界効果型超伝導素子を構成
する場合、チャネル層を構成する酸化物超伝導体は、キ
ャリア密度の小さい酸化物系の材料であれば、その超伝
導遷移温度は低くても使用できる。また各種の元素置換
により、転移温度を設定できる酸化物系の材料は、特定
の動作温度において最も効率よく動作させ得る超伝導素
子を設計するのに望ましいものである。また超伝導体と
同系の酸化物薄膜との積層膜は、その積層構造(積層材
料および組合せ、積層順、積層周期等)によって超伝導
性を制御できるので、先の理由により、単独の相による
チャネル層同様に、チャネル層を構成するのに有効であ
る。この場合、積層膜の積層構造は用途にあわせて任意
であるが、材料の組合せとしては、同種の結晶構造を持
つもの同士が望ましい。例えば、Y−Ba−Cu−Oと
Pr−Ba−Cu−Oの組合せ、Bi−Sr−Ca−C
u−OとBi−Sr−Cu−O(2201相)、または
Bi−Sr−Ca−Cu−OとBi−Sr−Ln−Cu
−O(2212相、LnはY、またはランタノイド元
素)の組合せ等が望ましい。また、チャネル層に用いた
積層膜を構成する各薄膜、およびゲート絶縁膜まで含め
て、同種の結晶構造、格子定数をもつ材料の選択が望ま
しい。例えば、非常に近い結晶構造並びに結晶定数を有
するBi系酸化物超伝導体をチャネル層に用い、ペロブ
スカイト構造のPb系強誘電体をゲート絶縁膜に用いる
か、またはチャネル層、ゲート絶縁膜、さらにはバッフ
ァー層、基体、電気伝導層など、すべてBi系層状構造
化合物を用いると、各電極、薄膜層が各々結晶性よく作
製できるため、超伝導素子の特性向上に有利である。特
にゲート絶縁膜は、薄くしかも結晶性よく成膜できるた
め、チャネル層の電気的特性の高性能化(高誘電率、ゲ
ート絶縁膜の絶縁耐圧の向上、リーク電流の減少等)に
効果がある。
When the field effect type superconducting device as described above is constructed, the oxide superconductor constituting the channel layer has a low superconducting transition temperature if it is an oxide material having a low carrier density. Can also be used. Further, an oxide material whose transition temperature can be set by various element substitutions is desirable for designing a superconducting device that can be operated most efficiently at a specific operating temperature. In addition, since the superconductivity of a laminated film of a superconductor and an oxide thin film of the same system can be controlled by the laminated structure (lamination material and combination, lamination order, lamination period, etc.), it is possible to use a single phase for the above reason. Like the channel layer, it is effective for forming the channel layer. In this case, the laminated structure of the laminated film is arbitrary depending on the application, but the combination of materials is preferably those having the same kind of crystal structure. For example, a combination of Y-Ba-Cu-O and Pr-Ba-Cu-O, Bi-Sr-Ca-C
u-O and Bi-Sr-Cu-O (2201 phase), or Bi-Sr-Ca-Cu-O and Bi-Sr-Ln-Cu.
A combination of —O (2212 phase, Ln is Y, or a lanthanoid element) is desirable. Further, it is desirable to select materials having the same type of crystal structure and lattice constant, including each thin film forming the laminated film used for the channel layer and the gate insulating film. For example, a Bi-based oxide superconductor having a crystal structure and a crystal constant very close to each other is used for a channel layer, and a Pb-based ferroelectric material having a perovskite structure is used for a gate insulating film, or a channel layer, a gate insulating film, and When a Bi-based layered structure compound such as a buffer layer, a substrate, and an electroconductive layer is used, each electrode and thin film layer can be formed with good crystallinity, which is advantageous for improving the characteristics of the superconducting device. In particular, since the gate insulating film can be formed thin and with good crystallinity, it is effective in improving the electrical characteristics of the channel layer (high dielectric constant, improvement of dielectric strength of gate insulating film, reduction of leak current, etc.). .

【0030】特に、酸化物超伝導薄膜の材料として、主
成分が2212相のBi系酸化物超伝導体、例えば(B
1-y Pby 2 −Sr2 −Ca1 −Cu2 −Ox (た
だし0 ≦y <0.5 、xは任意の自然数)、または主成分
が2223相の酸化物超伝導体、例えば(Bi1-y Pb
y 2 −Sr2 −Ca2 −Cu3 −Ox (ただし0 ≦y
<0.5 、xは任意の自然数)を用い、酸化物薄膜の材料
として、主成分が2212相の酸化物、例えば(Bi
1-y Pby 2 −Sr2 −Ln1 −Cu2 −Ox(ただ
し0 ≦y <0.5 、xは任意の自然数、LnはY、および
ランタノイド元素のうち少なくとも一つを示す)、また
は主成分が2201相のBi系酸化物、例えば(Bi
1-y Pby 2 −Sr2 −Cu1 −Ox (ただし0 ≦y
<0.5 、xは任意の自然数)などの組み合わせを用いる
と、積層膜作製が容易で、良好なチャネル層が形成でき
る。
In particular, as a material for the oxide superconducting thin film, a Bi-based oxide superconductor whose main component is 2212 phase, such as (B
i 1-y Pb y) 2 -Sr 2 -Ca 1 -Cu 2 -O x ( provided that 0 ≦ y <0.5, x is an arbitrary natural number), or an oxide superconductor of the main component is 2223, for example ( Bi 1-y Pb
y) 2 -Sr 2 -Ca 2 -Cu 3 -O x ( provided that 0 ≦ y
<0.5, x is an arbitrary natural number), and the main component of the oxide thin film is an oxide having a phase of 2212, such as (Bi
1-y Pb y) 2 -Sr 2 -Ln 1 -Cu 2 -O x ( provided that 0 ≦ y <0.5, x is an arbitrary natural number, Ln represents at least one of Y, and lanthanoid element), or A Bi-based oxide whose main component is 2201 phase, such as (Bi
1-y Pb y) 2 -Sr 2 -Cu 1 -O x ( provided that 0 ≦ y
If a combination such as <0.5, x is an arbitrary natural number) is used, a laminated film can be easily formed and a good channel layer can be formed.

【0031】さらに、ゲート絶縁膜上に2つのゲート電
極を狭い間隔で対向させて形成すると電極間ギャップを
小さくでき等化的に電界が大きくなり、電界効果を顕著
に大きくできる。
Further, when two gate electrodes are formed on the gate insulating film so as to face each other at a narrow interval, the gap between the electrodes can be reduced, and the electric field can be increased by equalization and the electric field effect can be remarkably increased.

【0032】また薄膜積層型の素子構造とすると、集積
化が可能で有るばかりでなく、上記のような積層型チャ
ネル層の設計において、また変調効率の高い薄いゲート
絶縁膜を作製する際に有効となる。
In addition, the thin film laminated type device structure is not only capable of integration, but also effective in designing the laminated type channel layer as described above and in producing a thin gate insulating film having high modulation efficiency. Becomes

【0033】また、少なくともチャネル層、ゲート絶縁
膜、電気伝導層、ゲート電極を同一真空中で形成する作
製方法によると、ゲート絶縁膜と他のチャネル層、ゲー
ト電極もしくは電気伝導層との界面に低誘電率の層が生
じず、界面状態が良好に保てるため、素子特性の再現
性、安定性、変調効率の向上に顕著な効果がある。
According to the manufacturing method of forming at least the channel layer, the gate insulating film, the electrically conductive layer, and the gate electrode in the same vacuum, the interface between the gate insulating film and another channel layer, the gate electrode, or the electrically conductive layer is formed. Since a layer having a low dielectric constant is not formed and the interface state can be kept good, it has a remarkable effect in improving the reproducibility of element characteristics, stability, and modulation efficiency.

【0034】以下に具体的実施例を挙げて、本発明をよ
り詳細に説明する。 実施例1 本発明の第1発明の実施例を図1を用いて説明する。図
1において、1はチャネル層、2はゲート絶縁膜、3は
ゲート電極、4はソース電極、5はドレイン電極であ
る。チャネル層1は、僻開した2212相のBi系酸化
物超伝導体、Bi 2 −Sr2 −Sr1 −Cu2 −O
x (xは任意の自然数)単結晶であり、その厚みは約
0.5mmである。また後の薄膜作製、素子プロセスに
際して、適宜適当な基体に固定し、取扱の便を図ってい
る。またゲート絶縁膜2は、rfスパッタリング法によ
る厚さ400nmのPb0.9 La0.1 TiO3 薄膜であ
る。堆積時のチャネル層[Bi2 −Sr2 −Sr1 −C
2 −Ox (xは任意の自然数)単結晶]は540℃に
保った。次にメタルマスクをもちいて、ゲート電極3、
ソース電極4、ドレイン電極5をスパッタ成膜によるP
tで形成した。
The present invention will be described below with reference to specific examples.
Will be described in detail. Embodiment 1 An embodiment of the first invention of the present invention will be described with reference to FIG. Figure
1, 1 is a channel layer, 2 is a gate insulating film, 3 is
Gate electrode, 4 is a source electrode, 5 is a drain electrode
It The channel layer 1 is made of a bisected 2212 phase Bi-based oxide.
Superconductor, Bi 2-Sr2-Sr1-Cu2-O
x(X is an arbitrary natural number) It is a single crystal and its thickness is about
It is 0.5 mm. Also for later thin film fabrication and device process
At this time, it is fixed to an appropriate base as appropriate to facilitate handling.
It The gate insulating film 2 is formed by rf sputtering.
400 nm thick Pb0.9La0.1TiO3In thin film
It Channel layer during deposition [Bi2-Sr2-Sr1-C
u2-Ox(X is an arbitrary natural number) Single crystal] is 540 ° C
I kept it. Next, using a metal mask, the gate electrode 3,
The source electrode 4 and the drain electrode 5 are formed by sputtering P
formed at t.

【0035】この素子は、ゲート電極3と、チャネル層
1の間に電圧を印加することによってソース電極4、ド
レイン電極5間のコンダクタンスが変化した。また、ゲ
ート絶縁膜2であるPb0.9 La0.1 TiO3 薄膜は強
誘電性を示し、電圧を取り除いた後でもコンダクタンス
の変化が持続した。さらにチャネル層1である単結晶中
の酸素量を、真空中での加熱、または酸素中での加熱冷
却によって、還元、酸化すると、顕著な電解効果の得ら
れる動作温度を変化させることができた。さらに、ゲー
ト絶縁膜2に用いたPb0.9 La0.1 TiO3 薄膜はペ
ロブスカイト構造をもち、チャネル層1にエピタキシャ
ル成長しており、膜中の欠陥がほとんどなく、良好なゲ
ート絶縁膜として機能した。
In this element, the conductance between the source electrode 4 and the drain electrode 5 was changed by applying a voltage between the gate electrode 3 and the channel layer 1. Further, the Pb 0.9 La 0.1 TiO 3 thin film as the gate insulating film 2 exhibited ferroelectricity, and the change in conductance continued even after the voltage was removed. Furthermore, when the amount of oxygen in the single crystal that is the channel layer 1 is reduced or oxidized by heating in vacuum or heating / cooling in oxygen, the operating temperature at which a remarkable electrolytic effect can be obtained could be changed. . Further, the Pb 0.9 La 0.1 TiO 3 thin film used for the gate insulating film 2 had a perovskite structure and was epitaxially grown on the channel layer 1, and there were almost no defects in the film and it functioned as a good gate insulating film.

【0036】実施例2 図2は本発明の第2発明の実施例を示す概略断面図であ
る。図2(a)は平面図、図2(b)は図2(a)のA
−A線の断面図である。まず、Nbドープ(100)S
rTiO3 基板を基体に用い、rfマグネトロンスパッ
タリング法によって、ゲート絶縁膜2となるPb−Zr
−Ti−O3 薄膜を400nm堆積させた。ゲート絶縁
膜2は、堆積した薄膜の組成が、ほぼPb(Zr0.5
0.5 )O3 となるように補償した混合酸化物粉末を用
いている。次いで、主成分が2212相の酸化物超伝導
体を含むBi系酸化物超伝導体Bi2 −Sr2 −Ca1
−Cu2 −Ox (xは任意の自然数)が堆積するように
調整した酸化物粉末のターゲットを用い、厚さ50nm
のチャネル層1を堆積させた。このチャネル層1の堆積
までを、同一真空中で、しかも基板の温度を650℃に
保ったまま行った。ひきつづき基板温度を室温にし、ソ
ース電極、ドレイン電極、ゲート電極となるPt薄膜を
真空を破らずに成膜した。
Embodiment 2 FIG. 2 is a schematic sectional view showing an embodiment of the second invention of the present invention. 2A is a plan view, and FIG. 2B is A in FIG.
It is a sectional view taken along the line A. First, Nb-doped (100) S
Pb-Zr used as a gate insulating film 2 by an rf magnetron sputtering method using a rTiO 3 substrate as a substrate.
The -ti-O 3 film was 400nm deposited. The composition of the deposited thin film of the gate insulating film 2 is approximately Pb (Zr 0.5 T
i 0.5 ) O 3 is used as the mixed oxide powder compensated. Next, a Bi-based oxide superconductor Bi 2 -Sr 2 -Ca 1 containing an oxide superconductor whose main component is a 2212 phase
-Cu 2 -O x (x is an arbitrary natural number) using an oxide powder target was adjusted so that is deposited, a thickness of 50nm
Channel layer 1 was deposited. The process of depositing the channel layer 1 was performed in the same vacuum, while keeping the substrate temperature at 650 ° C. Subsequently, the substrate temperature was set to room temperature, and Pt thin films to be the source electrode, the drain electrode, and the gate electrode were formed without breaking the vacuum.

【0037】その後、ネガレジストを用いたフォトリソ
グラフィーおよびイオンミリングにより、2つのゲート
電極3、チャネル層1、ソース電極4、およびドレイン
電極5をパターニングし、素子を完成させた。
After that, the two gate electrodes 3, the channel layer 1, the source electrode 4, and the drain electrode 5 were patterned by photolithography and ion milling using a negative resist to complete the device.

【0038】この素子は、2つのゲート電極間に電圧を
印加することによってソース電極、ドレイン電極間のコ
ンダクタンスが変化した。ソース、ドレイン間に一定電
流を流しながら、ゲート電極に制御電圧を加えることに
よって、ソース、ドレイン間の電圧が変調され、電界効
果型の素子として動作した。なおNbドープSrTiO
3 基板は電気伝導性であり、電気伝導層6としての働き
も兼ねている。また、2つのゲート電極に印加する電圧
を取り除いた後もこの効果は持続した。この電界効果
は、素子温度、20ケルビンから100ケルビンで顕著
であり、動作機構は解明されていないが、電界効果によ
るキャリアの遍在に起因する、超伝導性の誘起または抑
制であるとすると説明がつく。
In this device, the conductance between the source electrode and the drain electrode was changed by applying a voltage between the two gate electrodes. By applying a control voltage to the gate electrode while applying a constant current between the source and drain, the voltage between the source and drain was modulated, and the device operated as a field effect device. Nb-doped SrTiO 3
The three substrates are electrically conductive and also serve as the electrically conductive layer 6. Further, this effect continued even after the voltage applied to the two gate electrodes was removed. This electric field effect is remarkable at a device temperature of 20 Kelvin to 100 Kelvin, and although the operating mechanism has not been clarified, it is explained that it is induction or suppression of superconductivity due to ubiquity of carriers due to electric field effect. Get stuck.

【0039】実施例3 図3は本発明の一実施例の作製プロセス概略図である。
図3(a)は積層膜の堆積、同図(b)はレジストによ
るパターン作製、同図(c)はエッチング、同図(c)
はレジスト除去の各工程を示す図である。作製方法は実
施例2と似ているが、基体10に絶縁体である(10
0)MgO基板を用い、その上に電気伝導層を成膜した
ことが異なる部分である。実施例2とほぼ同様に、電気
伝導層6、ゲート絶縁膜2、チャネル層1、さらにはソ
ース電極、ドレイン電極等になるPtのコンタクト層ま
で同一真空中で作製した後、素子作製工程を行なった。
本実施例の電気伝導層6は、基体10上に堆積した厚さ
300nmの、主成分が2201相のBi系酸化物Bi
2 −Sr2 −Cu1 −Ox (xは任意の自然数)であ
る。基板温度は650℃とした。またゲート絶縁膜2
は、rfスパッタリング法による厚さ470nmのPb
−La−Ti−O薄膜である。チャネル層は、その上に
堆積した厚さ50nmの、主成分が2223相のBi系
酸化物超伝導体Bi 2 −Sr2 −Sr2 −Cu3 −Ox
(xは任意の自然数)とした。基板の温度は、電気伝導
層、チャネル層の堆積時は650℃に保ち、ゲート絶縁
膜3の堆積時は550℃とした。すなわち、電気伝導層
成膜後、基板温度を約100℃下降し、ゲート絶縁膜を
成膜後、再び基板温度を上昇させ、チャネル層を堆積し
た。ゲート絶縁膜は、(Pb0.9 La0.1 )TiO3
近いものであり、ターゲットは10%Pbを補償した焼
結体を用いた。ゲート絶縁膜は良好な強誘電性を示し、
室温に於て、抗電界の値は約27KV/cm、残留分極
の値は約18μC/cm2であった。また、チャネル層成
膜後は高温の成膜過程、プロセス過程が無いため、チャ
ネル層の超伝導特性の劣化がなく、良好な超伝導素子が
作製できた。なお、ゲート電極4は、電極間隔が2μm
の対向型とした。
Embodiment 3 FIG. 3 is a schematic view of the manufacturing process of one embodiment of the present invention.
FIG. 3A shows the deposition of a laminated film, and FIG.
Pattern fabrication, same figure (c) etching, same figure (c)
[Fig. 3] is a diagram showing each step of resist removal. The manufacturing method is real
Similar to Example 2, but the substrate 10 is an insulator (10
0) An MgO substrate was used and an electrically conductive layer was formed thereon.
Is the different part. In the same manner as in Example 2, electricity
The conductive layer 6, the gate insulating film 2, the channel layer 1, and the
The contact layer of Pt that becomes the source electrode, the drain electrode, etc.
After manufacturing in the same vacuum, the element manufacturing process was performed.
The electrically conductive layer 6 of this embodiment has a thickness that is deposited on the substrate 10.
Bi-based oxide Bi having a main component of 2201 phase of 300 nm
2-Sr2-Cu1-Ox(X is an arbitrary natural number)
It The substrate temperature was 650 ° C. In addition, the gate insulating film 2
Is 470 nm thick Pb formed by rf sputtering.
-La-Ti-O thin film. The channel layer is on it
Deposited 50 nm thick Bi-based compound whose main component is 2223 phase
Oxide superconductor Bi 2-Sr2-Sr2-Cu3-Ox
(X is an arbitrary natural number). Substrate temperature is electrical conduction
Layer insulation and gate layer insulation at 650 ° C for gate insulation
The film 3 was deposited at 550 ° C. That is, the electrically conductive layer
After forming the film, lower the substrate temperature by about 100 ° C to remove the gate insulating film.
After film formation, raise the substrate temperature again and deposit the channel layer.
It was The gate insulating film is (Pb0.9La0.1) TiO3To
It is close to the target, and the target is 10% Pb compensated firing.
A knot was used. The gate insulating film shows good ferroelectricity,
At room temperature, the value of coercive field is about 27 KV / cm, remanent polarization
Is about 18 μC / cm2Met. In addition, channel layering
After the film, there is no high temperature film formation process
A good superconducting element without deterioration of superconducting properties of the flannel layer
I was able to make it. The gate electrode 4 has an electrode interval of 2 μm.
Of the opposite type.

【0040】この素子は、対向する各ゲート電極に異な
った電圧または同電位の電圧を印加することによって、
ソース電極、チャネル電極間のコンダクタンスが変化し
た。ソース、ドレイン間に一定電流を流しながら、ゲー
ト電極に制御電圧を加えることによって、ソース、ドレ
イン間の電圧が変調され、電界効果型の素子として動作
した。またゲート電極に印加する電圧を取り除いた後で
もこの効果は持続し、メモリー機能を示した。この電界
効果は、素子温度、20ケルビンから110ケルビンで
顕著であり、特に対向するゲート電極に異なった電位を
与えた場合より変調効果が大きかった。
In this device, by applying different voltages or voltages of the same potential to the respective facing gate electrodes,
The conductance between the source electrode and the channel electrode changed. By applying a control voltage to the gate electrode while applying a constant current between the source and drain, the voltage between the source and drain was modulated, and the device operated as a field effect device. This effect persisted even after the voltage applied to the gate electrode was removed, indicating a memory function. This electric field effect is remarkable at a device temperature of 20 Kelvin to 110 Kelvin, and in particular, the modulation effect was larger than when different potentials were applied to the opposing gate electrodes.

【0041】また、この薄膜を用い、一本のチャネル層
上に2つのゲート電極を形成し、この電極に互いに異な
る電圧を印加した場合、各ゲート電極下のチャネル部分
のコンダクタンスは、一方が大きくなると他方が小さく
なるように変化し、相補的な変化をした。
When two gate electrodes are formed on one channel layer using this thin film and different voltages are applied to the electrodes, one of the conductances of the channel portion under each gate electrode is large. Then, the other changed so as to become smaller, and a complementary change was made.

【0042】実施例4 図4(a)は本発明の別の実施例を示す概略図である。
また、図4(b)は、図4(a)のチャネル層1の部分
拡大図である。まず、(100)MgO基板を基体10
に用い、rfマグネトロンスパッタリング法によって、
主成分が2212相の酸化物超伝導体を含むBi系酸化
物超伝導体Bi2 −Sr2 −Ca1 −Cu2 −Ox (x
は任意の自然数)が堆積するように調整した酸化物粉末
のターゲットを用い、厚さ30nmの酸化物超伝導体薄
膜11を堆積させた。ひき続き同一真空中において、主
成分が2212相のBi系酸化物Bi2 −Sr2 −Nd
1−Cu2 −Ox (xは任意の自然数)が堆積するよう
に調整した酸化物粉末のターゲットより酸化物薄膜12
を厚さ30nm堆積させた。この2層膜でチャネル層1
を構成した。
Embodiment 4 FIG. 4 (a) is a schematic view showing another embodiment of the present invention.
4B is a partially enlarged view of the channel layer 1 of FIG. 4A. First, the (100) MgO substrate is used as the base 10
Used by the rf magnetron sputtering method,
Bi-based oxide superconductor Bi 2 -Sr 2 -Ca 1 -Cu 2 -O x (x
Is an arbitrary natural number), and an oxide superconductor thin film 11 having a thickness of 30 nm was deposited using an oxide powder target adjusted to deposit. Subsequently, in the same vacuum, the Bi-based oxide Bi 2 —Sr 2 —Nd containing 2212 phase as the main component was used.
The oxide thin film 12 is formed from the target of the oxide powder adjusted so that 1- Cu 2 -O x (x is an arbitrary natural number) is deposited.
Was deposited to a thickness of 30 nm. With this two-layer film, the channel layer 1
Configured.

【0043】さらにゲート絶縁膜2となるPbTiO3
薄膜を400nm堆積させた。このゲート絶縁膜2の堆
積は、同一真空中で、しかも基板の温度を600℃に下
げて行った。
Further, PbTiO 3 which becomes the gate insulating film 2 is formed.
A thin film was deposited to 400 nm. The deposition of the gate insulating film 2 was performed in the same vacuum, and the substrate temperature was lowered to 600 ° C.

【0044】その後、ネガレジストを用いたフォトリソ
グラフィーおよびイオンミリングにより、チャネル層
1、およびゲート絶縁膜2をチャネル層形状にパターニ
ングした。さらに、ソース電極、ドレイン電極用のコン
タクトホールを、同様のイオンミリングで形成後、Pt
薄膜を堆積、ゲート電極3、ソース電極4、ドレイン電
極5をパターニングし、素子を完成させた。Pt薄膜の
パターニングはリフトオフ法にて行った。
After that, the channel layer 1 and the gate insulating film 2 were patterned into a channel layer shape by photolithography using a negative resist and ion milling. Further, after forming contact holes for the source electrode and the drain electrode by the same ion milling, Pt
A thin film was deposited and the gate electrode 3, the source electrode 4, and the drain electrode 5 were patterned to complete the device. The Pt thin film was patterned by the lift-off method.

【0045】この素子は、ゲート電極に電圧を印加する
ことによってソース電極、ドレイン電極間のコンダクタ
ンスが変化した。ソース、ドレイン間に一定電流を流し
ながら、ゲート電極に制御電圧を加えることによって、
ソース、ドレイン間の電圧が変調され、電界効果型の素
子として動作した。この電界効果は、素子温度、20ケ
ルビンから100ケルビンで顕著であり、動作機構は解
明されていないが、電界効果によるキャリアの遍在に起
因する、超伝導性の誘起または抑制であるとすると説明
がつく。またこの効果は、積層膜で顕著であり、酸化物
超伝導薄膜と酸化物薄膜の近接効果によって、より効果
的になる効果と考えられる。
In this element, the conductance between the source electrode and the drain electrode was changed by applying a voltage to the gate electrode. By applying a control voltage to the gate electrode while applying a constant current between the source and drain,
The voltage between the source and drain was modulated, and the device operated as a field effect device. This electric field effect is remarkable at a device temperature of 20 Kelvin to 100 Kelvin, and although the operating mechanism has not been clarified, it is explained that it is induction or suppression of superconductivity due to ubiquity of carriers due to electric field effect. Get stuck. Further, this effect is remarkable in the laminated film, and it is considered that the effect becomes more effective due to the proximity effect between the oxide superconducting thin film and the oxide thin film.

【0046】実施例5 図5は本発明のさらに別の実施例の概略図である。図5
(a)は平面図、同図(b)は同図(a)のB−B線の
断面図であり、図5(c)は、チャネル層1のより詳細
な模式図である。作製方法は実施例4と同様で、ゲート
絶縁膜まで同一真空中で堆積したものであるが、チャネ
ル層1の構成が異なる。本実施例のチャネル層1は、基
体10上に堆積した厚さ30nmの、主成分が2201
相のBi系酸化物Bi2 −Sr2 −Cu1 −Ox (xは
任意の自然数)を含む酸化物薄膜12と、その上に堆積
した厚さ30nmの、主成分が2223相のBi系酸化
物超伝導体Bi2 −Sr2 −Sr2 −Cu3 −Ox (x
は任意の自然数)を含む酸化物超伝導体薄膜11より構
成した。またゲート絶縁膜2は、rfスパッタリング法
による厚さ350nmのBi3 Ti4 12薄膜である。
基板の温度は、チャネル層の堆積時は650℃に保ち、
ゲート絶縁膜3の堆積時は550℃とした。さらに、ゲ
ート電極3は、電極間隔が2μmの対向型とした。 こ
の素子は、対向する各ゲート電極に異なった電圧または
同電位の電圧を印加することによって、ソース電極、チ
ャネル電極間のコンダクタンスが変化した。ソース、ド
レイン間に一定電流を流しながら、ゲート電極に制御電
圧を加えることによって、ソース、ドレイン間の電圧が
変調され、電界効果型の素子として動作した。この電界
効果は、素子温度、20ケルビンから110ケルビンで
顕著であり、特に対向するゲート電極に異なった電位を
与えた場合より変調効果が大きかった。
Embodiment 5 FIG. 5 is a schematic view of still another embodiment of the present invention. Figure 5
5A is a plan view, FIG. 6B is a cross-sectional view taken along line BB in FIG. 5A, and FIG. 5C is a more detailed schematic view of the channel layer 1. The manufacturing method is the same as in Example 4, and the gate insulating film is deposited in the same vacuum, but the configuration of the channel layer 1 is different. The channel layer 1 of this example has a thickness of 30 nm deposited on the substrate 10 and is composed mainly of 2201.
(The x arbitrary natural number) Bi-based oxide Bi 2 -Sr 2 -Cu 1 -O x phase and the oxide film 12 containing, thick 30nm deposited thereon, Bi-based principal components 2223 oxide superconductor Bi 2 -Sr 2 -Sr 2 -Cu 3 -O x (x
Is an oxide superconductor thin film 11 containing an arbitrary natural number. Further, the gate insulating film 2 is a Bi 3 Ti 4 O 12 thin film having a thickness of 350 nm formed by the rf sputtering method.
The substrate temperature was kept at 650 ° C during the deposition of the channel layer,
The temperature was set to 550 ° C. when the gate insulating film 3 was deposited. Further, the gate electrode 3 is of a facing type with an electrode interval of 2 μm. In this element, the conductance between the source electrode and the channel electrode was changed by applying different voltages or voltages of the same potential to the facing gate electrodes. By applying a control voltage to the gate electrode while applying a constant current between the source and drain, the voltage between the source and drain was modulated, and the device operated as a field effect device. This electric field effect is remarkable at a device temperature of 20 Kelvin to 110 Kelvin, and in particular, the modulation effect was larger than when different potentials were applied to the opposing gate electrodes.

【0047】実施例6 次に本発明のさらに別の実施例を説明する。作製方法は
実施例4と同様であるが、チャネル層1の構成が異な
る。本実施例のチャネル層1は、主成分が2201相の
Bi系酸化物Bi2 −Sr2 −Cu1 −Ox (xは任意
の自然数)を含む酸化物薄膜12と、主成分が2212
相のBi系酸化物超伝導体Bi2 −Sr2−Sr1 −C
2 −Ox (xは任意の自然数)を含む酸化物超伝導体
薄膜11より構成した多層膜であり、その構成は厚さ3
nmの2212相と2.4nmの2201相を交互に各
4層ずつ堆積したものである。図6はこのチャネル層の
模式図を示したものである。本実施例では、最上層は、
2201相とした。またゲート絶縁膜は、rfスパッタ
リング法による厚さ400nmのBi3 Ti4 12薄膜
である。基板の温度は、チャネル層の堆積時は650℃
に保ち、ゲート絶縁膜の堆積時は520℃とした。さら
に、ゲート電極は、電極間隔を2μmとした対向型とし
た。
Embodiment 6 Next, still another embodiment of the present invention will be described. The manufacturing method is the same as in Example 4, but the structure of the channel layer 1 is different. In the channel layer 1 of this example, an oxide thin film 12 containing a Bi-based oxide Bi 2 —Sr 2 —Cu 1 —O x (x is an arbitrary natural number) of 2201 phase as a main component, and 2212 as a main component.
Bi-based oxide phase superconductor Bi 2 -Sr 2 -Sr 1 -C
It is a multilayer film composed of an oxide superconductor thin film 11 containing u 2 —O x (x is an arbitrary natural number), and has a thickness of 3
2212 phase of 2.4 nm and 2201 phase of 2.4 nm are alternately deposited in four layers each. FIG. 6 shows a schematic view of this channel layer. In this embodiment, the top layer is
2201 phase. The gate insulating film is a Bi 3 Ti 4 O 12 thin film having a thickness of 400 nm formed by the rf sputtering method. The substrate temperature is 650 ° C. when the channel layer is deposited.
And the gate insulating film was deposited at 520 ° C. Further, the gate electrode was of a facing type with an electrode interval of 2 μm.

【0048】この素子もまた、対向するゲート電極に異
なった電圧または同電位の電圧を印加することによって
ソース電極、ドレイン電極間のコンダクタンスが変化し
た。特にこの多層膜をチャネル層に用いた素子は、チャ
ネル層の積層膜を種々の形状(積層周期、各々の積層さ
れる酸化物薄膜の膜厚など)を変えることによってその
素子特性、顕著な電解効果の得られる動作温度を変化さ
せることができた。さらに、ゲート絶縁膜に用いたBi
3 Ti4 12薄膜はBi系層状構造化合物の一つであ
り、チャネル層にエピタキシャル成長しており、膜中の
欠陥がほとんどなく、良好なゲート絶縁膜として機能し
た。
Also in this device, the conductance between the source electrode and the drain electrode was changed by applying different voltages or voltages of the same potential to the facing gate electrodes. In particular, an element using this multi-layered film as a channel layer has various characteristics (e.g., stacking period, film thickness of each oxide thin film to be stacked) of the stacked film of the channel layer, resulting in excellent characteristics of the device. It was possible to change the operating temperature at which the effect was obtained. Further, Bi used for the gate insulating film
The 3 Ti 4 O 12 thin film was one of the Bi-based layered structure compounds, was epitaxially grown on the channel layer, had almost no defects in the film, and functioned as a good gate insulating film.

【0049】以上の実施例の超伝導素子は、すべてチャ
ネル層、およびゲート絶縁膜を同一真空中で成膜してお
り、素子特性は安定し、また再現性もよいものであっ
た。以上の実施例3、4、5、6、の超伝導素子は、す
べてチャネル層、およびゲート絶縁膜を同一真空中で成
膜しており、素子特性は安定し、また再現性もよいもの
であった。
In all of the superconducting devices of the above examples, the channel layer and the gate insulating film were formed in the same vacuum, and the device characteristics were stable and the reproducibility was good. In the superconducting devices of Examples 3, 4, 5, and 6 described above, the channel layer and the gate insulating film are all formed in the same vacuum, and the device characteristics are stable and the reproducibility is good. there were.

【0050】以上説明した通り、本実施例によれば、電
界が印加されるゲート電極に強誘電性を有する材料を用
い、さらにチャネル層に酸化物超伝導体を用いた超伝導
素子とすることにより、ゲート電極に電圧を印加した場
合、チャネル層の常伝導抵抗、もしくはゼロ抵抗温度が
変化し、印加電圧を取り除いた後もこの変化が持続する
ことを確認した。またゲート絶縁膜に接して電気伝導層
を設けると(ゲート絶縁膜に対して電気伝導層をグラン
ドプレーンとすると)、より簡便な作製方法で超伝導素
子が作製できることも確認できた。
As described above, according to the present embodiment, a superconducting device using a ferroelectric material for the gate electrode to which an electric field is applied and an oxide superconductor for the channel layer is provided. Thus, it was confirmed that when a voltage is applied to the gate electrode, the normal conduction resistance or the zero resistance temperature of the channel layer changes, and this change continues even after the applied voltage is removed. It was also confirmed that if an electrically conductive layer was provided in contact with the gate insulating film (when the electrically conductive layer was a ground plane for the gate insulating film), the superconducting element could be manufactured by a simpler manufacturing method.

【0051】現在電気通信の分野では、自動車電話の普
及、デジタル画像情報の伝送、情報ネットワークの普及
などにより、大量の信号を伝達する手段として、より高
周波を用いた通信手段が望まれていた。本実施例による
超伝導素子は、従来使用できなかった高周波の電波の信
号処理、検知に利用できるため、電気通信分野の電波周
波数の利用範囲を拡大できる。またメモリー機能、相補
的な動作機能をもつ素子を構成することによって、論理
演算回路の構成が可能である。この回路はデジタル回路
であり、計算機応用、高周波デジタル通信等への応用が
可能である。
At present, in the field of telecommunications, due to the spread of automobile telephones, the transmission of digital image information, the spread of information networks, etc., a communication means using a higher frequency has been desired as a means for transmitting a large amount of signals. The superconducting element according to the present embodiment can be used for signal processing and detection of high-frequency radio waves that could not be used conventionally, so that the range of use of radio frequency in the telecommunication field can be expanded. Further, a logical operation circuit can be configured by configuring an element having a memory function and a complementary operation function. This circuit is a digital circuit, and can be applied to computers, high frequency digital communication, and the like.

【0052】これらの点で本発明の実用的効果は、電気
情報通信分野で大である。
From these points, the practical effect of the present invention is great in the field of electric information communication.

【0053】[0053]

【発明の効果】以上説明したように、電界が印加される
チャネル層に、酸化物超伝導体を用い、その積層膜に接
して設けた強誘電性のゲート絶縁膜を介して電界を印加
した場合、その積層膜の超伝導遷移点付近での常伝導抵
抗、もしくは零抵抗温度が、変化し、超伝導素子を構成
できる効果がある。また、印加電界を取り除いた後でも
この効果が持続するメモリー機能をもつ素子を作製でき
る。
As described above, an oxide superconductor is used for the channel layer to which an electric field is applied, and the electric field is applied through the ferroelectric gate insulating film provided in contact with the laminated film. In this case, the normal resistance or the zero resistance temperature in the vicinity of the superconducting transition point of the laminated film is changed, and there is an effect that a superconducting element can be formed. Further, it is possible to manufacture a device having a memory function in which this effect is maintained even after the applied electric field is removed.

【0054】上記の超伝導素子において、強誘電性を有
するゲート絶縁膜は、電界効果を保持する働きがあり、
メモリー機能を有する超伝導素子を実現できる。この素
子は単独でメモリー素子として働くため、高集積化に非
常に有利である。さらに、ゲート電極を2つ以上有する
素子は相補的に働く素子を構成でき、論理演算回路に有
効である。
In the above superconducting device, the gate insulating film having ferroelectricity has a function of retaining the electric field effect,
A superconducting device having a memory function can be realized. Since this element independently functions as a memory element, it is very advantageous for high integration. Furthermore, an element having two or more gate electrodes can form an element that works complementarily, which is effective for a logical operation circuit.

【0055】上記のような電界効果型超伝導素子を構成
する場合、チャネル層を構成する酸化物超伝導体に、キ
ャリア密度の小さい酸化物系の材料を用い、各種の元素
置換、または、超伝導体と同系の酸化物薄膜のとの積層
構造(各種積層材料、積層順、積層周期等の組合せ)に
よって超伝導性を制御できるので、特定の動作温度にお
いて最も効率よく動作させ得る超伝導素子を設計できる
効果がある。
When the field effect type superconducting element as described above is constructed, an oxide-based material having a low carrier density is used for the oxide superconductor constituting the channel layer, and various element substitutions or superconducting materials are used. The superconductivity can be controlled by the laminated structure (combination of various laminated materials, lamination order, lamination period, etc.) of the conductor and the oxide thin film of the same system, so that the superconducting element can be operated most efficiently at a specific operating temperature. There is an effect that can be designed.

【0056】また、チャネル層に用いた積層膜を構成す
る各薄膜、およびゲート絶縁膜まで含めて、同種の結晶
構造、格子定数をもつ材料を選択すると、各電極、薄膜
層が各々結晶性よく作製できるため、超伝導素子の特性
向上に効果がある。特にゲート絶縁膜は、薄くしかも結
晶性よく成膜できるため、チャネル層の電気的特性の高
性能化(高誘電率、ゲート絶縁膜の絶縁耐圧の向上、リ
ーク電流の減少等)に効果がある。
Further, if materials having the same crystal structure and lattice constant are selected, including the respective thin films constituting the laminated film used for the channel layer and the gate insulating film, the respective electrodes and the thin film layers have good crystallinity. Since it can be manufactured, it is effective in improving the characteristics of the superconducting element. In particular, since the gate insulating film can be formed thin and with good crystallinity, it is effective in improving the electrical characteristics of the channel layer (high dielectric constant, improvement of dielectric strength of gate insulating film, reduction of leak current, etc.). .

【0057】さらに、ゲート絶縁膜上に2つのゲート電
極を狭い間隔で対向させて形成すると電極間ギャップを
小さくでき等化的に電界が大きくなり、電界効果を顕著
に大きくなる効果がある。
Further, when two gate electrodes are formed on the gate insulating film so as to face each other at a narrow interval, the gap between the electrodes can be reduced, and the electric field is increased by equalization, so that the electric field effect is significantly increased.

【0058】また薄膜積層型の素子構造とすると、集積
化が可能で有るばかりでなく、上記のような積層型チャ
ネル層の設計において、また変調効率の高い薄いゲート
絶縁膜を作製する際に絶大な効果を有する。
Further, if the thin film laminated type element structure is used, not only the integration is possible, but also in the design of the laminated type channel layer as described above and when the thin gate insulating film having a high modulation efficiency is produced, it is extremely large. Have a significant effect.

【0059】また、少なくともチャネル層、ゲート絶縁
膜、電気伝導層、ゲート電極を同一真空中で形成する作
製方法によると、ゲート絶縁膜と他のチャネル層、ゲー
ト電極もしくは電気伝導層との界面に低誘電率の層が生
じず、界面状態が良好に保てるため、素子特性の再現
性、安定性、変調効率の向上に顕著な効果がある。
According to the manufacturing method of forming at least the channel layer, the gate insulating film, the electrically conductive layer and the gate electrode in the same vacuum, the interface between the gate insulating film and another channel layer, the gate electrode or the electrically conductive layer is formed. Since a layer having a low dielectric constant is not formed and the interface state can be kept good, it has a remarkable effect in improving the reproducibility of element characteristics, stability, and modulation efficiency.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例1の超伝導素子の概略断面図で
ある。
FIG. 1 is a schematic sectional view of a superconducting device of Example 1 of the present invention.

【図2】本発明の実施例2の超伝導素子の概略断面図で
ある。
FIG. 2 is a schematic sectional view of a superconducting device of Example 2 of the present invention.

【図3】本発明の実施例3の超伝導素子の作製プロセス
図である。
FIG. 3 is a manufacturing process diagram of a superconducting device of Example 3 of the present invention.

【図4】本発明の実施例4の超伝導素子の概略断面図
(a)と、チャネル層の模式図(b)である。
FIG. 4 is a schematic cross-sectional view (a) of a superconducting device of Example 4 of the present invention and a schematic view (b) of a channel layer.

【図5】本発明の実施例5の超伝導素子の概略断面図
(a)(b)と、チャネル層(c)の模式図である。
FIG. 5 is a schematic cross-sectional view (a) and (b) of a superconducting device of Example 5 of the present invention and a schematic view of a channel layer (c).

【図6】本発明の実施例6のチャネル層の模式図であ
る。
FIG. 6 is a schematic diagram of a channel layer according to a sixth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 チャネル層 2 ゲート絶縁膜、 3 ゲート電極、 4 ソース電極、 5 ドレイン電極、 6 電気伝導層 7 コンタクト層 8 ネガレジスト 10 基体 11 酸化物薄膜 12 酸化物超伝導薄膜 1 channel layer 2 gate insulating film, 3 gate electrode, 4 source electrode, 5 drain electrode, 6 electric conduction layer 7 contact layer 8 negative resist 10 substrate 11 oxide thin film 12 oxide superconducting thin film

───────────────────────────────────────────────────── フロントページの続き (72)発明者 瀬恒 謙太郎 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kentaro Setsune 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (14)

【特許請求の範囲】[Claims] 【請求項1】 チャネル層と、前記チャネル層に接する
ソース電極とドレイン電極とゲート絶縁膜、および前記
ゲート絶縁膜に接するゲート電極を少なくとも備えた超
伝導素子であって、前記チャネル層が少なくとも酸化物
超伝導体を含み、かつ前記ゲート絶縁膜が強誘電性を有
する膜であることを特徴とする超伝導素子。
1. A superconducting element comprising at least a channel layer, a source electrode and a drain electrode in contact with the channel layer, a gate insulating film, and a gate electrode in contact with the gate insulating film, wherein the channel layer is at least oxidized. 1. A superconducting device comprising a material superconductor, wherein the gate insulating film is a film having ferroelectricity.
【請求項2】 チャネル層、ゲート絶縁膜、およびゲー
ト電極が薄膜で形成され、基体上に積層構造で形成され
ている請求項1に記載の超伝導素子。
2. The superconducting element according to claim 1, wherein the channel layer, the gate insulating film, and the gate electrode are formed of a thin film and are formed in a laminated structure on the substrate.
【請求項3】 電気伝導層と、前記電気伝導層に接する
強誘電性を有するゲート絶縁膜と、前記ゲート絶縁膜に
接するチャネル層と、前記チャネル層に接するソース電
極とドレイン電極とゲート電極を少なくとも備えた超伝
導素子であって、前記チャネル層が少なくとも酸化物超
伝導体を含み、かつ前記ゲート絶縁膜が強誘電性を有す
る膜であることを特徴とする超伝導素子。
3. An electrically conductive layer, a ferroelectric gate insulating film in contact with the electrically conductive layer, a channel layer in contact with the gate insulating film, a source electrode, a drain electrode and a gate electrode in contact with the channel layer. A superconducting device comprising at least the above, wherein the channel layer contains at least an oxide superconductor, and the gate insulating film is a film having ferroelectricity.
【請求項4】 電気伝導層、ゲート絶縁膜、チャネル
層、及びゲート電極が薄膜で形成され、基体上に積層構
造で形成されている請求項3に記載の超伝導素子。
4. The superconducting device according to claim 3, wherein the electrically conductive layer, the gate insulating film, the channel layer, and the gate electrode are formed of thin films and are formed in a laminated structure on the base.
【請求項5】 ゲート電極が少なくとも2つである請求
項1または3に記載の超伝導素子。
5. The superconducting device according to claim 1, wherein the number of gate electrodes is at least two.
【請求項6】 チャネル層が、少なくともBiを含む酸
化物超伝導体を含み、かつゲート絶縁膜が、少なくとも
Pbを含む強誘電体またはBiを含む強誘電体を含む請
求項1または3に記載の超伝導素子。
6. The method according to claim 1, wherein the channel layer contains an oxide superconductor containing at least Bi, and the gate insulating film contains a ferroelectric containing at least Pb or a ferroelectric containing Bi. Superconducting element.
【請求項7】 チャネル層が、少なくとも下記式(化
1)で表される酸化物超伝導体または酸化物常伝導体を
含み、かつゲート絶縁膜が、少なくとも(Pb1- x La
x )(Zr1-y Tiy 1-x/4 3 (0≦x≦0.2、
0≦y≦1.0)で表される強誘電体、またはBi3
4 12で表される強誘電体を含む請求項1または3に
記載の超伝導素子。 【化1】
7. The channel layer contains at least an oxide superconductor or an oxide normal conductor represented by the following formula (Formula 1), and the gate insulating film contains at least (Pb 1 -x La).
x ) (Zr 1-y Ti y ) 1-x / 4 O 3 (0 ≦ x ≦ 0.2,
0 ≦ y ≦ 1.0) or a ferroelectric substance represented by Bi 3 T
The superconducting element according to claim 1, which contains a ferroelectric represented by i 4 O 12 . [Chemical 1]
【請求項8】 チャネル層が、少なくともCuとBiを
含む酸化物超伝導体とCuとBiを含む酸化物とからな
る積層膜から形成されている請求項1または3に記載の
超伝導素子。
8. The superconducting element according to claim 1, wherein the channel layer is formed of a laminated film composed of an oxide superconductor containing at least Cu and Bi and an oxide containing Cu and Bi.
【請求項9】 基体上にチャネル層を成膜し、前記チャ
ネル層上にゲート絶縁膜と、さらに前記ゲート絶縁膜上
にゲート電極を成膜し、その積層膜を用いて超伝導素子
を作製する超伝導素子の製造方法。
9. A channel layer is formed on a substrate, a gate insulating film is formed on the channel layer, and a gate electrode is formed on the gate insulating film, and a superconducting element is manufactured using the laminated film. Method for manufacturing superconducting device.
【請求項10】 チャネル層の成膜温度が少なくとも6
00℃以上であり、かつ、ゲート絶縁膜の成膜温度が6
00℃以下である請求項9に記載の超伝導素子の製造方
法。
10. The film forming temperature of the channel layer is at least 6
The temperature is 00 ° C. or higher, and the gate insulating film formation temperature is 6
The method for producing a superconducting device according to claim 9, wherein the temperature is 00 ° C. or lower.
【請求項11】 少なくともチャネル層、ゲート絶縁
膜、ゲート電極を同一真空中で成膜する請求項9に記載
の超伝導素子の製造方法。
11. The method for manufacturing a superconducting device according to claim 9, wherein at least the channel layer, the gate insulating film, and the gate electrode are formed in the same vacuum.
【請求項12】 基体上に電気伝導層を成膜し、前記電
気伝導層上にゲート絶縁膜を成膜し、前記ゲート絶縁膜
上にチャネル層を成膜し、前記チャネル層上にゲート電
極を成膜し、その積層膜を用いて超伝導素子を作製する
超伝導素子の製造方法。
12. An electrically conductive layer is formed on a substrate, a gate insulating film is formed on the electrically conductive layer, a channel layer is formed on the gate insulating film, and a gate electrode is formed on the channel layer. A method of manufacturing a superconducting device, comprising forming a film, and manufacturing a superconducting device using the laminated film.
【請求項13】 ゲート絶縁膜の成膜温度が600℃以
下であり、しかも前記ゲート絶縁膜を成膜後、基板温度
を600℃以上に加熱し、チャネル層を成膜する請求項
9または12に記載の超伝導素子の製造方法。
13. The film forming temperature of the gate insulating film is 600 ° C. or lower, and after forming the gate insulating film, the substrate temperature is heated to 600 ° C. or higher to form the channel layer. A method for manufacturing the superconducting device according to.
【請求項14】 電気伝導層、ゲート絶縁膜、チャネル
層、ゲート電極を同一真空中で成膜する請求項9または
12に記載の超伝導素子の製造方法。
14. The method for manufacturing a superconducting device according to claim 9, wherein the electrically conductive layer, the gate insulating film, the channel layer, and the gate electrode are formed in the same vacuum.
JP4321583A 1992-06-29 1992-12-01 Superconducting element and manufacture thereof Pending JPH06169112A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP4321583A JPH06169112A (en) 1992-12-01 1992-12-01 Superconducting element and manufacture thereof
US08/080,726 US5828079A (en) 1992-06-29 1993-06-24 Field-effect type superconducting device including bi-base oxide compound containing copper
EP93110358A EP0577074B1 (en) 1992-06-29 1993-06-29 Field-effect type super-conducting device
DE69328567T DE69328567T2 (en) 1992-06-29 1993-06-29 Superconducting device of the field-effect type
DE69306316T DE69306316T2 (en) 1992-06-29 1993-06-29 Superconducting device of the field-effect type
EP95118306A EP0701292B1 (en) 1992-06-29 1993-06-29 Field-effect type superconducting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4321583A JPH06169112A (en) 1992-12-01 1992-12-01 Superconducting element and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH06169112A true JPH06169112A (en) 1994-06-14

Family

ID=18134176

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4321583A Pending JPH06169112A (en) 1992-06-29 1992-12-01 Superconducting element and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH06169112A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014086990A1 (en) * 2012-12-07 2014-06-12 Thales Varistor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014086990A1 (en) * 2012-12-07 2014-06-12 Thales Varistor
FR2999328A1 (en) * 2012-12-07 2014-06-13 Thales Sa ADJUSTABLE RESISTANCE
US9412504B2 (en) 2012-12-07 2016-08-09 Thales Varistor

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