JPH06169067A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To provide a semiconductor memory device which facilitates the prevention of the reduction of an internal holding voltage caused by a reading current and the setting of a large current as a reading current. CONSTITUTION:A pair of P-N-P transistors Q3 and Q4 are used as the loads of a pair of information holding N-P-N transistors Q1 and Q2 in a P-N-P load cell. In addition to a pair of reading N-P-N transistors Q7 and Q8 in the load cell, a pair of exclusive writing transistors Q5 and Q6 are provided. The collectors of the reading N-P-N transistors Q7 and Q8 are fixed to a ground potential and the collectors of the reading N-P-N transistors Q7 and Q8 are used as nodes different from the voltage holding nodes (a) and (b). With this constitution, a reading current is not applied to the voltage holding nodes (a) and (b).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device which is a bipolar SRAM and includes a so-called PNP load cell that uses a PNP transistor as a load of an information holding transistor.

[0002]

2. Description of the Related Art FIG. 6 shows one type of bipolar SRAM.
As shown in, PN is used as a load of multi-emitter type NPN transistors Q51 and Q52 for holding information.
A PNP load cell using P transistors Q53 and Q54 is well known. The PNP load cells are arranged in a matrix, and P is provided on the upper word line UWL for selecting cells.
The emitters of the NP transistors Q53 and Q54 are commonly connected to the lower word line LWL and one of the emitters of the multi-emitter type NPN transistors Q51 and Q52, respectively.
NPN transistors Q52 and Q are connected to the bit lines BL0 and BL1.
The other one of the emitters of 51 is connected to form a memory circuit.

[0003]

However, in the PNP load cell having the above-described configuration, as shown in FIG. 7, the read current I _{read at the} time of performing the information read operation flows through the voltage holding nodes a and b. Transistor Q53,
Q54 collector resistance _RC or h when a large current flows
Due to the decrease in _fe (grounded emitter closed-circuit small-signal forward current amplification factor), the internal holding voltage drops, so it was necessary to set the read current to an appropriate value.

Further, the internal holding voltage is shifted by the voltage drop caused by the read current I _read flowing through the parasitic resistance R _P , R _X such as the emitter resistance of the PNP transistors Q53, Q54 and the connection resistance with the word line UWL. Since there is a possibility that the read current I _read may not be set, a large current cannot be set as the read current I _read , and it is necessary to secure a large read margin. In general, since many memory cells are connected to the bit lines BL0 and BL1 and a parasitic capacitance due to wiring is added,
The larger the read current I _read that drives this is, the faster the voltage of the bit lines BL0 and BL1 is opened, and the faster access time is obtained. _Therefore, the larger the read current I _read is, the more preferable.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor memory device capable of preventing a decrease in internal holding voltage due to a read current and setting a large current as a read current. To do.

[0006]

A semiconductor memory device according to the present invention includes a pair of information holding NPN transistors having a flip-flop circuit configuration, and a pair of information holding NPN transistors connected to a word line. Load PNP transistor and a pair of write NPNs in which each collector is connected to each voltage holding node of a pair of information holding NPN transistors and each base is connected to a word line.
A pair of read NPN transistors each having a base commonly connected to each of the pair of information holding NPN transistors and each collector fixed to a reference potential, and each emitter of the pair of write NPN transistors is provided. In addition to being connected to the write bit line, the emitters of the pair of read NPN transistors are used by being connected to the read bit line provided separately from the write bit line.

[0007]

In the semiconductor memory device having the PNP load cell structure, a pair of write-only transistors are provided separately from the pair of read NPN transistors, and the collector of the read NPN transistor is fixed to the reference potential. By making the collector different from the voltage holding node of the memory cell, the read current is prevented from flowing through the voltage holding node. As a result, it is possible to prevent a decrease in the internal holding voltage due to the read current flowing through the voltage holding node, and it is possible to flow a large current as the read current, which shortens the access time (speeds up) and stabilizes the stability. Can be improved.

Further, by connecting the collector of the write-only transistor to the voltage holding node and connecting the base thereof to the word line, when a memory circuit is constructed by using this cell, the word line of high potential is surely applied. Since the write current flows from the connected write-only transistor, the word line can be satisfactorily operated even if the word line amplitude is made as small as possible. Therefore, the word line amplitude, which was required to be about 1.1v in the past, can be set to about 0.6v even if a margin of about 0.3v is added in consideration of variations and the like, and the access speed can be further increased. .

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a PNP load cell according to the present invention. In FIG. 1, a pair of NPN transistors Q1 and Q2 holding information are connected to each other in a flip-flop circuit configuration, and a pair of PNP transistors Q3 and Q4 are used as their loads. The emitters of the pair of PNP transistors Q3 and Q4 are commonly connected to the upper word line UWL, and the emitters of the pair of NPN transistors Q1 and Q2 are commonly connected to the lower word line LWL.

To the collectors of the pair of NPN transistors Q1 and Q2, that is, the voltage holding nodes a and b, the collectors of the pair of write-only NPN transistors Q5 and Q6 are connected. This pair of NPN transistors Q5,
The bases of Q6 are commonly connected to the upper word line UWL,
In addition, each emitter has write bit lines WBL0 and WBL1.
Respectively connected to.

On the other hand, a pair of NPN transistors Q1 and Q
The bases of a pair of read-only NPN transistors Q7 and Q8 are commonly connected to the respective bases of 2. The ground potential, that is, the maximum potential within the operating range of the memory cell is applied to the collectors of the pair of NPN transistors Q7 and Q8, and the emitters are read bit lines RBL.
1 and RBL0 are respectively connected.

Thus, the pair of write-only NPN transistors Q5 and Q6 are provided, and the collectors of the pair of read-only NPN transistors Q7 and Q8 are different from the voltage holding nodes a and b. As shown in FIG. 2, the read current I _read does not flow through the voltage holding nodes a and b but from the collector ground node of the pair of read-only NPN transistors Q7 and Q8. Become.

As a result, the pair of PNP transistors Q
The internal holding voltage does not decrease due to the decrease in collector resistance R _{C of Q3} and h _fe when a large current flows,
In addition, since the holding voltage is not shifted by the parasitic resistances R _P and R _X such as the emitter resistance and the connection resistance with the word line UWL, a large current can be flown as the read current I _read , and thus the high speed operation can be achieved. This makes it possible to read and improve the stability of reading.

The PNP according to the present invention configured as described above
FIG. 3 shows a circuit example in which a load circuit is used to configure a memory circuit selection circuit. In the selection circuit of FIG. 3, the first memory cell 11 now connected to the word line UWL1
Is in the Select state, the second memory cell 12 connected to the word line UWL2 is in the Deselect state, the base potential of the transistor Q11 is Low, and the base potential of the transistor Q21 is High. Think

In this state, when the conventional memory cell having no write-only transistors Q15 and Q25 (see FIG. 6) is used, the word line UWL amplitude is the low side voltage value of the memory cell 11 in the selected state. And the voltage value on the High side of the memory cell 12 in the non-selected state. Therefore, conventionally, in consideration of variations and the like, assuming that Vf of the transistor is about 0.8v, the word line UWL amplitude is at least 1.1v (= 0.8v + 0.3v) when a margin of about 0.3v is added. ) Was necessary.

However, when the PNP load cell according to the present invention is used, write-only transistors Q15 and Q25 are used.
Is connected to the word lines UWL1 and UWL2 respectively, and the write current always flows from the write-only transistor Q15 whose base is connected to the high potential (selected side) word line UWL1. Good operation can be achieved even if the UWL amplitude is made as small as possible. Therefore, the word line UWL amplitude, which was conventionally required to be 1.1 v or more, can be set to about 0.6 v even if a margin of about 0.3 v is added in consideration of variations and the like, which shortens the access time (high speed). Can be changed.

In the selection circuit of FIG. 3, the bit lines RL1, RL1 are connected between the read bit lines RL1, RL2.
A clamp circuit 13 that clamps the voltage between RL2 to a predetermined potential is connected. In the clamp circuit 13, each base is connected in common, each collector is fixed to the ground potential (reference potential), and each emitter is connected to the bit line RL.
1, a pair of NPN transistors Q5 connected to RL2
It is composed of 1 and Q52.

In this clamp circuit 13, a pair of N
The base potential of the PN transistors Q51 and Q52 is the holding voltage of the selected memory cell (holding voltage in the selected state).
It is set by the resistor Rcl so that the potential becomes substantially the intermediate potential. In this way, by setting the base potentials of the transistors Q51 and Q52 that configure the clamp circuit 13 to a substantially intermediate potential of the holding voltage in the selected state, the bit line RL
Since the selection amplitudes of 1 and RL2 can be halved, it is possible to contribute to the increase of the reading speed.

Next, the basic cell of the PNP load cell according to the present invention will be described. FIG. 4 is a circuit diagram showing half of the basic cell shown in FIG. 1. When the basic cells are arranged and connected in line symmetry, the memory cell of FIG. 1 is completed. This half cell is composed of a total of four transistors including an information holding NPN transistor Q1, a load PNP transistor Q3, a write-only NPN transistor Q5, and a read-only NPN transistor Q7.

FIG. 5 is a block diagram of a half cell, which is (A).
FIG. 3A is a plan view showing an example of a pattern layout, and FIG. 3B is a sectional view taken along line BB ′ of FIG. First, the base of the write-only NPN transistor Q5 is formed of the P ⁺ region 21, and a contact (UWL) is formed through the P-Poly 22.
It is connected to 23. The emitter is the N ⁺ region 24
Is formed by the N-epi layer 26 and is connected to the contact (WE) 25.
It is connected to the.

On the other hand, the emitter of the load PNP transistor Q3 is formed by the P ⁺ region 21 and is formed of P-Poly2.
It is connected to the contact (UWL) 23 via 2. The base is formed of the N-epi layer 26 and connected to the contact (NC), and the collector is formed of the P ⁺ region 28 and connected to the contact 30 via the P-Poly 29. That is, the load PNP transistor Q3 has a lateral PNP structure.

Next, an NPN transistor Q for holding information.
The emitter of 1 is formed of the N ⁺ region 31 and connected to the contact (CE) 32. The base is formed of the P ⁺ region 28, is connected to the contact 30 through the P-Poly 29, and the collector is formed of the N-epi layer 26 and is connected to the contact (NC). The structure of the transistors Q1, Q3 and Q5 is shown in FIG.
As is clear from the pattern layout of, the emitter of the PNP transistor Q3 and the base of the NPN transistor Q5 are formed in the same diffusion region (P ⁺ region 21),
The base of the NPN transistor Q1 and the collector of the PNP transistor Q3 are formed in the same region (P ⁺ region 28), and the collector of the NPN transistor Q1 and the collector of the NPN transistor Q5 and the base of the PNP transistor Q3 are formed in the same region (N-epi). Layer 26).

On the other hand, a read-only NPN transistor Q
7 is formed in another region insulated from the transistors Q1, Q3 and Q5 because it is necessary to ground the collector. That is, the emitter of the read-only NPN transistor Q7 is formed in the N ⁺ region 33 and connected to the contact (RE) 34, and the base is formed in the P ⁺ region 35 and connected to the contact 30 via the P-Poly 29. The collector is formed of the N-epi layer 36 and is grounded (GND) through a contact 37.

The half-cell having the above structure has a substrate (P-Sub) 38, as is apparent from the cell sectional view of FIG.
It is formed further on the N-epi layer 26 formed above and is separated from other cells by the P-insulating layer 39. In this example, the cells are electrically separated by the insulating layer 39 formed of the P ⁺ diffusion layer, but the invention is not limited to this. A method of separation is also possible.

According to the above-described cell structure, the layout area of the half cell becomes large because the collector of the read-only NPN transistor Q7 is different from the voltage holding node, but the NPN transistor Q7 is large. Since the collector is grounded and does not become a load at the time of word selection, it does not hinder an increase in read speed.

[0026]

As described above, according to the present invention,
In a semiconductor memory device having a PNP load cell configuration, a pair of write-only transistors are provided separately from a pair of read NPN transistors, the collector of the read NPN transistor is fixed to a reference potential, and the collector of the read NPN transistor is used as a cell. Since the read current does not flow through the voltage holding node of the memory cell by setting it as a node different from the voltage holding node of, the decrease of the internal holding voltage due to the read current flowing through the voltage holding node can be prevented and the read voltage can be prevented. A large current can be passed as the current. This makes it possible to shorten the access time (speed up) and improve the stability.

Moreover, since the collector of the write-only transistor is connected to the voltage holding node and the base thereof is connected to the word line, when the memory circuit is constructed by using the present memory cell, the word line of high potential is surely held. Since a write current flows from the write-only transistor connected to, and the word line can be satisfactorily operated even if the amplitude of the word line is made as small as possible, there is an effect that the access speed can be further increased.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of FIG.

FIG. 3 is a circuit diagram of a selection circuit of a memory circuit configured by using a PNP load cell according to the present invention.

FIG. 4 is a circuit diagram of a half cell of a PNP load cell according to the present invention.

FIG. 5 is a configuration diagram of a half cell of a PNP load cell according to the present invention, in which (A) is a pattern layout diagram thereof,
(B) is a sectional view taken along line BB ′ of (A).

FIG. 6 is a circuit diagram of a conventional example.

FIG. 7 is an equivalent circuit diagram of FIG.

[Explanation of symbols]

 11 first memory cell 12 second memory cell 13 clamp circuit Q1, Q2 information holding NPN transistor Q3, Q4 load PNP transistor Q5, Q6 write NPN transistor Q7, Q8 read NPN transistor a, b voltage hold node

Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H01L 27/10 481 7210-4M 6741-5L G11C 11/40 305

Claims (4)

[Claims] 1. A pair of information holding NPN transistors having a flip-flop circuit configuration, a pair of load PNP transistors connected between the pair of information holding NPN transistors and a word line, and each collector having the pair. A pair of write NPN transistors connected to respective voltage holding nodes of the information holding NPN transistor and having respective bases connected to the word line, and a base commonly connected to each of the pair of information holding NPN transistors. And a pair of read NPN transistors each having a collector fixed to a reference potential, each emitter of the pair of write NPN transistors being connected to a write bit line, and a pair of read NPN transistors of the pair. Each emitter has a read-out bit provided separately from the write-in bit line. The semiconductor memory device characterized by being used is connected to the bets line. 2. The semiconductor memory device according to claim 1, wherein the reference potential is a maximum potential within an operating range. 3. The pair of read NPN transistors are formed in an area electrically separated from the pair of information holding NPN transistors, the pair of load PNP transistors, and the pair of write NPN transistors. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device. 4. A pair of transistors in which each base is connected in common, each collector is fixed to a reference potential, and each emitter is connected to the read bit line, and a voltage between the read bit lines is set. 2. The semiconductor memory device according to claim 1, further comprising a clamp circuit for clamping at a predetermined potential, wherein the base potential of the pair of transistors is set to a substantially intermediate potential of the holding voltage in the selected state.