JPH06168841A - Debinder method of laminated electronic part - Google Patents

Debinder method of laminated electronic part

Info

Publication number
JPH06168841A
JPH06168841A JP4341485A JP34148592A JPH06168841A JP H06168841 A JPH06168841 A JP H06168841A JP 4341485 A JP4341485 A JP 4341485A JP 34148592 A JP34148592 A JP 34148592A JP H06168841 A JPH06168841 A JP H06168841A
Authority
JP
Japan
Prior art keywords
temperature
debinding
furnace
debinder
pressure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4341485A
Other languages
Japanese (ja)
Inventor
Hiroshi Saito
斎藤  博
Yoshio Akimoto
欣男 秋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP4341485A priority Critical patent/JPH06168841A/en
Publication of JPH06168841A publication Critical patent/JPH06168841A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To provide a debinder method in which crack or peeling does not occur after a debinder of a chip element. CONSTITUTION:A slurry is formed by mixing a dielectric porcelain powder and a binder solution, and a conductive pattern serving as an internal electrode is printed on green sheets obtained from the slurry, and a stacked body is formed by stacking up these sheets. After the stacked body is cut to a chip element with a predetermined size, the stacked body is loaded into a debinder oven, an internal pressure of the oven is increased to 10 atm, and then the temperature is increased at the rate of 20 deg.C per hour, and after the oven temperature reaches 200 deg.C, the pressure is started to reduce and is returned to an atmospheric pressure. Then, the oven temperature is kept at the peak temperature set according to the used binder for a certain time, and a debinder is completed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、積層コンデンサ等の積
層電子部品の製造過程における脱バインダー方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for debinding a laminated electronic component such as a laminated capacitor.

【0002】[0002]

【従来の技術】積層コンデンサ等の積層電子部品は、積
層体内部に、厚み方向に重畳して形成される導電体を有
する。このような積層電子部品を製造するには、一般
に、有機バインダー(エチルセルロース、PVAな
ど)、可塑剤(ポリエチレングリコールなど)、分散剤
(グリセリン、オレイン酸エチルなど)および溶剤(ア
セトン、トルエン、エチルアルコール、水など)よりな
るバインダー溶液と原料粉末とを混合してスラリーを作
り、これから得られるグリーンシートに、スクリーン印
刷等で導電パターンを印刷したものを積み重ねることに
よって行われる。
2. Description of the Related Art A laminated electronic component such as a laminated capacitor has a conductor formed inside the laminated body so as to be superposed in the thickness direction. In order to manufacture such laminated electronic components, organic binders (ethyl cellulose, PVA, etc.), plasticizers (polyethylene glycol, etc.), dispersants (glycerin, ethyl oleate, etc.) and solvents (acetone, toluene, ethyl alcohol) are generally used. , Water, etc.) and a raw material powder are mixed to form a slurry, and a green sheet obtained from this is stacked with conductive patterns printed by screen printing or the like.

【0003】得られた積層体を所望寸法に切断分割して
チップ状にし、このチップ素子を焼成する前に通常、有
機バインダー等を除去する脱バインダーが行われる。こ
の脱バインダーは、おもに加熱ガス中で行われることが
多い。
The obtained laminated body is cut and divided into desired dimensions to form chips, and the binder is usually removed before the chip element is fired to remove the organic binder and the like. This debinding is often performed mainly in a heated gas.

【0004】[0004]

【発明が解決しようとする課題】ところで、脱バインダ
ー後のチップ素体を調べて見ると、側面にクラックやは
がれが発生していることがあり、この原因を探求した結
果、チップ素体が膨脹することがわかった。
By the way, when examining and examining the chip body after debinding, cracks and peeling may occur on the side surface. As a result of investigating the cause, the chip body expands. I found out that

【0005】すなわち、図2はある導電パターンが形成
されたチップ素体と、形成されずに積層されたチップ素
体とについて、常圧下で昇温させたときの膨脹の割合を
示すグラフであって、この例の場合、前者の曲線1が示
すように、膨脹は加熱ガスの温度が200℃のときにピ
ークに達し、一方、比較として導電パターンのないチッ
プ素体を同様に測定したところ、後者の曲線2が示すよ
うに、膨脹は見られなかった。
That is, FIG. 2 is a graph showing the rate of expansion of a chip element body on which a certain conductive pattern is formed and a chip element body stacked without being formed, when the temperature is raised under normal pressure. In the case of this example, as the former curve 1 shows, the expansion reaches a peak when the temperature of the heating gas is 200 ° C. On the other hand, as a comparison, when the chip body having no conductive pattern is similarly measured, No swelling was observed, as the latter curve 2 shows.

【0006】このような観察結果から、上記膨脹は導電
パターン中のバインダーがチップ素体から抜けるときに
おこると考えられる。
From the above observation results, it is considered that the expansion occurs when the binder in the conductive pattern comes off from the chip body.

【0007】したがって、本発明の目的は、チップ素体
の脱バインダー後に、クラックやはがれが発生しない脱
バインダー方法を提供することにある。
Therefore, an object of the present invention is to provide a debinding method in which cracks and peeling do not occur after debinding a chip element.

【0008】[0008]

【課題を解決するための手段】本発明者達は、前記チッ
プ素体の膨脹はバインダーがチップ素体から抜けるとき
におこる点に鑑み、研究を進めた結果、チップ素体の膨
脹が最大になる温度までは脱バインダー炉の内圧を大気
圧よりも高くして置き、該最大になる温度からは炉内圧
を減じて大気圧に戻すようにすれば、チップ素体の膨脹
を抑えることができ、前述の課題が解決されることを見
いだし本発明に到達した。
DISCLOSURE OF THE INVENTION In view of the fact that the expansion of the chip body occurs when the binder comes out of the chip body, the inventors of the present invention conducted research and found that the expansion of the chip body was maximized. If the internal pressure of the debinding furnace is set higher than the atmospheric pressure until the temperature reaches the maximum temperature, and the internal pressure of the furnace is reduced from the maximum temperature to return to the atmospheric pressure, the expansion of the chip body can be suppressed. The present invention has been achieved by finding that the above-mentioned problems are solved.

【0009】したがって本発明は、原料粉末とバインダ
ー溶液とを混練して得られるスラリーから調製されたグ
リーンシートを積層し、得られた積層体の内部に重畳し
て形成された導電パターンを有するチップ素材を脱バイ
ンダー炉に装入し、昇温して脱バインダーを行う積層電
子部品の脱バインダー方法において、室温からチップ素
体の膨脹が最大になる温度までは脱バインダー炉の内圧
を大気圧よりも高く維持し、該膨脹が最大になる温度か
らは炉内圧を減圧して大気圧に戻すとともに昇温をつづ
け、炉内温度を使用されたバインダーの特性によって設
定されるピーク温度に一定時間キープして脱バインダー
を終了することを特徴とする積層電子部品の脱バインダ
ー方法を提供するものである。
Therefore, according to the present invention, a chip having a conductive pattern formed by stacking green sheets prepared from a slurry obtained by kneading a raw material powder and a binder solution and superposing the green sheets inside the obtained stack. In the debinding method for laminated electronic components, in which the material is charged into the debinding furnace and the temperature is increased to perform debinding, the internal pressure of the debinding furnace is higher than atmospheric pressure from room temperature to the temperature at which the expansion of the chip body is maximized. Is kept high, the furnace pressure is reduced from the temperature at which the expansion is maximized, the furnace pressure is returned to atmospheric pressure, and the temperature is continuously raised, and the furnace temperature is kept at a peak temperature set by the characteristics of the binder used for a certain period of time. The present invention provides a method for debinding a laminated electronic component, which comprises terminating the debinding.

【0010】[0010]

【作用】本発明の方法では、チップ素体の膨脹が激し
い、室温から膨脹が最大となる温度Tmax までの間は、
高圧下で脱バインダーを行うので、チップ素体の膨脹を
抑えつつ導電パターン中のバインダーを除去できる。
In the method of the present invention, the expansion of the chip body is severe, and the temperature is from room temperature to the temperature T max at which the expansion is maximum.
Since the binder removal is performed under high pressure, the binder in the conductive pattern can be removed while suppressing the expansion of the chip body.

【0011】該Tmax から先は、膨脹の起こることはな
いので、大気圧に戻してチップ素体中のバインダーを除
去しやすいようにする。何故高圧から常圧に戻す必要が
あるかと言えば、もしも高圧下で最後まで行うと、チッ
プ内にガスがそのまま残ることになり、脱バインダーが
スムーズに進行しなくなり、炭化したりすることで次の
焼成時にデラミネーションの発生や焼結性悪化を引き起
こす。そこで、電極バインダーが初期分解を起こし、内
部ガスが容易に外まで抜ける状態になった後は、常圧に
もどすことが望ましいのである。
Since there is no expansion after T max , the pressure is returned to atmospheric pressure so that the binder in the chip body can be easily removed. The reason why it is necessary to return from high pressure to normal pressure is that if it is done under high pressure to the end, gas will remain in the chip as it is, debinding will not proceed smoothly and carbonization will occur. Causes delamination and deterioration of sinterability during firing. Therefore, after the electrode binder has undergone initial decomposition and the internal gas is easily released to the outside, it is desirable to return to normal pressure.

【0012】[0012]

【実施例】図1は、本実施例に用いられた脱バインダー
炉における炉内圧および炉内温度と時間の関係を示すプ
ロファイルであり、この図を参照しながら、本実施例で
は積層チップコンデンサを例として以下説明する。 (1)誘電体磁器粉末とバインダー溶液とを混練してセ
ラミックスラリーを作製し、このスラリーからドクター
ブレード法を用いてシート状に加工し、セラミックグリ
ーンシートを形成する。 (2)得られたセラミックグリーンシートに、スクリー
ン印刷により導電ペーストを塗布して内部電極となる導
電パターンを形成する。 (3)導電パターンを形成した該シートを一定形状に打
ち抜き、これを複数枚積み重ねて積層体とする。 (4)積層体を所定寸法のチップ素体に切断分割し、こ
れらチップ素体を脱バインダー炉に装入する。 (5)チップ素体装入後、図1に見られるように、まず
常温で炉の内圧を10気圧まで上昇させ、その後20℃
/hrの割合で昇温し、炉内温度が200℃になったと
ころで減圧しはじめ、大気圧に戻す。
EXAMPLE FIG. 1 is a profile showing the relationship between the furnace pressure and the furnace temperature in the debinding furnace used in this example and the time. With reference to this figure, in this example, the multilayer chip capacitor is An example will be described below. (1) A dielectric ceramic powder and a binder solution are kneaded to prepare a ceramic slurry, and the slurry is processed into a sheet using a doctor blade method to form a ceramic green sheet. (2) A conductive paste is applied to the obtained ceramic green sheet by screen printing to form a conductive pattern to be an internal electrode. (3) The sheet on which the conductive pattern is formed is punched into a certain shape, and a plurality of the sheets are stacked to form a laminated body. (4) The laminated body is cut and divided into chip elements having a predetermined size, and these chip elements are loaded into a binder removal furnace. (5) After loading the chip body, as shown in FIG. 1, first, the internal pressure of the furnace is raised to 10 atm at room temperature and then 20 ° C.
The temperature is raised at a rate of / hr, and when the temperature inside the furnace reaches 200 ° C., decompression is started and the pressure is returned to atmospheric pressure.

【0013】一方、炉温は使用されるバインダーの特性
によって設定されるピーク温度Tpで一定時間キープし
たのち、脱バインダーを終了する。
On the other hand, the furnace temperature is kept at the peak temperature Tp set by the characteristics of the binder used for a certain period of time, and then the binder removal is completed.

【0014】ここで、最初にかける高圧および減圧を始
める温度は、いずれも導電ペーストに使用されるバイン
ダーによって選択されるものであり、上記10気圧およ
び200℃に限定されない。
The temperature at which the high pressure and the reduced pressure to be applied first are selected depending on the binder used in the conductive paste, and are not limited to the above 10 atm and 200 ° C.

【0015】[0015]

【発明の効果】以上説明したように、本発明の方法によ
れば、脱バインダー処理中のチップ素体の膨脹が抑えら
れるので、脱バインダー後にクラックやはがれの発生の
ない良好な積層電子部品を得ることができる。
As described above, according to the method of the present invention, the expansion of the chip element body during the debinding process can be suppressed, so that a good laminated electronic component free from cracks and peeling after debinding can be obtained. Obtainable.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に用いられた脱バインダー炉
における炉内圧および炉内温度と時間の関係を示すプロ
ファイルである。
FIG. 1 is a profile showing a relationship between furnace pressure and furnace temperature in a debinding furnace used in one example of the present invention, and time.

【図2】導電パターンが形成されたチップ素体と、形成
されずに積層されたチップ素体とについて、常圧下で昇
温させたときの膨脹の割合を示すグラフである。
FIG. 2 is a graph showing a rate of expansion of a chip element body on which a conductive pattern is formed and a chip element body that is stacked without being formed when the temperature is raised under normal pressure.

【符号の説明】[Explanation of symbols]

1 導体パターンが形成されたチップ素体の膨脹率
を示す曲線 2 導体パターンが形成されずに積層されたチップ
素体の膨脹率を示す曲線 Tp ピーク温度
1 curve showing expansion coefficient of chip element with conductor pattern formed 2 curve showing expansion coefficient of chip element without laminated conductor pattern T p peak temperature

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 原料粉末とバインダー溶液とを混練して
得られるスラリーから調製されたグリーンシートを積層
し、得られた積層体の内部に重畳して形成された導電パ
ターンを有するチップ素材を脱バインダー炉に装入し、
昇温して脱バインダーを行う積層電子部品の脱バインダ
ー方法において、室温からチップ素体の膨脹が最大にな
る温度までは脱バインダー炉の内圧を大気圧よりも高く
維持し、該膨脹が最大になる温度からは炉内圧を減圧し
て大気圧に戻すとともに昇温をつづけ、炉内温度を使用
されたバインダーの特性によって設定されるピーク温度
に一定時間キープして脱バインダーを終了することを特
徴とする積層電子部品の脱バインダー方法。
1. A green sheet prepared from a slurry obtained by kneading a raw material powder and a binder solution is laminated, and a chip material having a conductive pattern formed inside the obtained laminated body is removed. Charge into the binder furnace,
In a method for debinding a laminated electronic component in which debindering is performed by raising the temperature, the internal pressure of the debinding furnace is kept higher than atmospheric pressure from room temperature to a temperature at which the expansion of the chip body is maximized, and the expansion is maximized. From this temperature, the furnace pressure is reduced to return to atmospheric pressure and the temperature continues to rise, and the furnace temperature is kept at the peak temperature set by the characteristics of the binder used for a certain period of time to finish debinding. Debinding method for laminated electronic parts.
JP4341485A 1992-11-28 1992-11-28 Debinder method of laminated electronic part Withdrawn JPH06168841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4341485A JPH06168841A (en) 1992-11-28 1992-11-28 Debinder method of laminated electronic part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4341485A JPH06168841A (en) 1992-11-28 1992-11-28 Debinder method of laminated electronic part

Publications (1)

Publication Number Publication Date
JPH06168841A true JPH06168841A (en) 1994-06-14

Family

ID=18346427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4341485A Withdrawn JPH06168841A (en) 1992-11-28 1992-11-28 Debinder method of laminated electronic part

Country Status (1)

Country Link
JP (1) JPH06168841A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006100448A (en) * 2004-09-28 2006-04-13 Kyocera Corp Manufacturing method of electronic component
KR100596288B1 (en) * 1999-06-30 2006-07-03 다이요 유덴 가부시키가이샤 Manufacturing method of laminated ceramic electronic parts

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100596288B1 (en) * 1999-06-30 2006-07-03 다이요 유덴 가부시키가이샤 Manufacturing method of laminated ceramic electronic parts
JP2006100448A (en) * 2004-09-28 2006-04-13 Kyocera Corp Manufacturing method of electronic component

Similar Documents

Publication Publication Date Title
JP4268844B2 (en) Manufacturing method of multilayer ceramic electronic component and multilayer ceramic electronic component
JP5423977B2 (en) Manufacturing method of multilayer ceramic electronic component
EP1415960B1 (en) Method for making raw dielectric ceramic powder, dielectric ceramic and monolithic ceramic capacitor
JPH06168841A (en) Debinder method of laminated electronic part
JP2003059759A (en) Multilayer ceramic electronic component and its manufacturing method
JP4001241B2 (en) Multilayer ceramic electronic component and paste for multilayer ceramic electronic component
JP2003209304A (en) Manufacturing method for laminated piezoelectric ceramic element
JP5530172B2 (en) Method for manufacturing internal electrode of electronic component
JP3166953B2 (en) Manufacturing method of ceramic electronic components
JP2000216042A (en) Manufacture of laminated ceramic capacitor
JPH06132664A (en) Manufacture of ceramic multilayer board
JP3239718B2 (en) Manufacturing method of multilayer ceramic electronic component
JPH1197280A (en) Method of manufacturing multilayer ceramic capacitor
JP3956695B2 (en) Manufacturing method of multilayer ceramic electronic component
JPH04328813A (en) Manufacture of laminated ceramic capacitor
JP3523399B2 (en) Manufacturing method of ceramic electronic components
JP3322027B2 (en) Manufacturing method of multilayer ceramic electronic component
KR100596288B1 (en) Manufacturing method of laminated ceramic electronic parts
JP2969658B2 (en) Manufacturing method of multilayer ceramic capacitor
JP3289646B2 (en) Manufacturing method of multilayer ceramic capacitor
JPH07162151A (en) Manufacture of multilayered ceramic board
JP2003092227A (en) Internal electrode material and method for manufacturing the same
JP2004250241A (en) Setter for firing and method for firing
JP3396494B2 (en) Method of manufacturing ceramic substrate with through hole
JP2002260952A (en) Manufacturing method of laminated ceramic electronic component

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20000201