JP3289646B2 - Manufacturing method of multilayer ceramic capacitor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer ceramic capacitor.

[0002]

2. Description of the Related Art A method of manufacturing a multilayer ceramic capacitor (hereinafter referred to as a chip capacitor) will be described below.

As shown in FIG. 4, an internal electrode 4 containing palladium as a main component is provided on a green sheet 3, and 5 is a cutting position.

FIG. 5 is a longitudinal sectional view of a chip capacitor, in which dielectric ceramics 6 and internal electrodes 7 containing palladium as a main component are alternately laminated, an ineffective layer 8 is provided on an outer layer thereof, and external electrodes are provided on both ends thereof. An electrode 9 is formed.

[0005] The chip condenser is obtained by calcining the mixed ceramic raw material at a temperature of about 1050 to 1150 ° C, pulverizing the mixed ceramic raw material to a particle size of 1 to 2 µm by a ball mill or the like, and then drying. Next, a binder, a solvent and a plasticizer are added to the calcined raw material to form a slurry, and a green sheet 3 of 100 μm or less is formed. An internal electrode 4 is printed on the surface of the green sheet 3.
When a plurality of green sheets 3 on which the internal electrodes 4 are printed are laminated, and cut at a cutting position 5 in a chip-con shape, a predetermined number of the internal electrodes 7 are displaced so as to be alternately exposed to different end faces, and then laminated at 400 kg / A green laminate is formed by pressure bonding at a pressure of not less than cm ² . Next, the green laminate is cut into a predetermined chip size and fired at a temperature of 1300 ° C. or more. Thereafter, the end face of the sintered body was polished to expose the internal electrode 7, and an external electrode 9 was formed on the end face to obtain a finished product.

[0006]

However, in the above-mentioned conventional manufacturing method, when the number of laminated green sheets 3 is large or thin, the thermal expansion and contraction behavior of the internal electrodes 7 in the firing process of the chip capacitor causes the after-sintering. There was a problem that delamination (hereinafter referred to as delamination), which is an internal structural defect, occurs between the internal electrode 7 of the chip capacitor and the dielectric ceramic 6.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a method for manufacturing a chip-con which alleviates the thermal expansion and contraction behavior of the internal electrode 7 during the firing process.

[0008]

According to the present invention, there is provided a ceramic material for forming a green sheet layer comprising 90 to 50% of calcined material and 10% remaining.
50% is not yet calcination of raw materials (hereinafter referred to as raw materials) Toka
And the average particle size is in the range of 0.9 to 2.0 μm
By using the mixed raw material , the thermal expansion and contraction behavior of the internal electrode during the sintering process of the chipcon is reduced by the firing and contraction behavior of the green sheet layer.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a method for manufacturing a chip capacitor in which a plurality of green sheets and internal electrodes are alternately laminated, wherein the internal electrode
Green material.
The layer is composed of 90-50% calcined raw material as ceramic raw material.
The remaining 10-50% of uncalcined raw materials and average grain
Using a mixed raw material having a diameter in the range of 0.9 to 2.0 μm
It is characterized by forming. As a ceramic raw material for forming a green sheet layer, a mixed raw material including a calcined raw material of 90 to 50% and a raw material of the remaining 10 to 50% is used.
By doing so , the added raw material absorbs the thermal expansion behavior of the internal electrode generated in the early stage of sintering of the chip con,
The sintering shrinkage of the raw material starts almost at the same time as the shrinkage of the internal electrodes in the later stage of sintering, and shrinks in the same way as the internal electrodes. The occurrence can be prevented.

The mixed raw material has an average particle size of 0.9 to 2.0.
By setting the range to 0 μm , delamination and
The occurrence of short-circuit failure can be prevented . This defines the particle size required to make the thermal expansion and contraction of the palladium used as the internal electrode material in the sintering process and the sintering and contraction of the green sheet layer substantially the same. Ingredient
Physically, the average particle size of the mixed raw material is smaller than 0.9 μm
If the green sheet density is large, the green sheet
Of the internal electrode with palladium
The difference in the shrinkage rate increases, and as a result
Generate The average particle size of the mixed raw material is 2.0 μm
If it is larger, the density of the green sheet is small and uneven.
First, the sintering shrinkage of the green sheet increases and
Since the contraction and shrinkage become non-uniform,
The difference in the sintering shrinkage ratio increases, and as a result, the dielectric ceramic
Cracks inside the rack and delamination, especially short-circuit failure
Is more likely to occur.

An embodiment of the present invention will be described below. (Embodiment 1) FIG. 1 is a model diagram showing a dispersion state of a powder obtained by mixing a calcined raw material and a raw material as raw materials for forming a green sheet layer, and FIG. 2 is a powder diagram using only a calcined raw material. FIG. 3 is a model diagram showing a dispersion state of powder using only raw materials. 1 to 3, 1 is a calcined raw material and 2 is a raw material.

As starting materials, barium carbonate, titanium oxide, neodymium oxide, and samarium oxide were each weighed, mixed, and dried to obtain raw material 2. Next, the raw material 2 was calcined at a temperature of 1100 ° C. for 2 hours. Thereafter, a predetermined amount of raw material 2 is added to the calcined raw material 1 in a range of 0 to 70%.
While mixing, the calcined raw material 1 and the raw material 2 are uniformly mixed, and the calcined raw material 1 having a large particle size is ground. At this time, the average particle size of the calcined raw material 1 was 4.5 μm, and the average particle size of the raw material 2 was 0.7 μm. The average particle size is 1.0
The mixing and pulverization time was adjusted so as to be in the range of ~ 1.3 µm. After dewatering and drying the mixed raw material, polyvinyl butyral resin as a binder, butyl acetate as a solvent, and dibutyl phthalate as a plasticizer are added, and wet-mixed with a ball mill to prepare a slurry. The slurry is formed into a green sheet 3 having a thickness of 25 μm by a roll coater method, and then cut into a size of 160 × 140 mm. Next, an internal electrode 4 having a width of 0.55 mm, a length of 3.2 mm, an interval between adjacent internal electrodes 4, a width of 0.38 mm and a length of 0.52 mm in the pattern shown in FIG. Print. Next, one green sheet 3 is stacked and pressed, and the printing pattern is shifted by 0.93 mm in the width direction to print the internal electrode 4 mainly containing palladium.
After this operation was repeated 40 times, 10 green sheets 3 were further stacked as an invalid layer 8 on and under the green sheets 3 to 400 kg / cm.
^The laminate was formed by pressure bonding under a pressure of ² . Next, the laminate was cut at a cutting position 5 at a length of 1.86 mm and a width of 0.93 mm.
After cutting into a chip-con shape, it was put into a high-purity alumina sheath to which zirconia powder was sprayed, and calcined in air at a temperature of 1300 ° C. for 2 hours. Each of the 50 chip-con sintered bodies was hardened and polished with an epoxy resin, and the number of occurrences of internal structural defects of the chip-con was investigated. The results are shown in (Table 1). Further, both ends of each 1000 chip-con sinters were polished, silver paste was applied to the both ends, and baked at a temperature of 800 ° C. to measure the capacitance. The results are also shown in (Table 1).

[0013]

[Table 1]

As is clear from Table 1, calcined raw material 1
Of a chip-con using a raw material obtained by adding and mixing the raw material 2 with the remaining raw material 2 of 90 to 50%, the occurrence of delamination, which is an internal structural defect, and the short-circuit failure between the internal electrodes 7 There was no outbreak. In contrast, the calcined raw material 1
Is greater than 95% or less than 40%, it can be seen that delamination and short-circuit failure have occurred. This is because the sintering shrinkage behavior of the dielectric ceramic 6 using the green sheet 3 obtained from the raw material obtained by mixing the calcined raw material 1 and the raw raw material 2 in an appropriate amount ratio depends on the firing process of the palladium used as the internal electrode 7. It is considered that the occurrence of delamination was prevented by absorbing and relaxing the thermal expansion and contraction behavior. On the other hand, when the calcined raw material is more than 90%, the dielectric ceramic 6 cannot absorb the expansion of the internal electrode 7 in the initial sintering process of the palladium, and peels off from the surface of the dielectric ceramic 6 to cause the latter stage of sintering. Process internal electrode 7
It is considered that delamination occurred due to the shrinkage of.
When the raw material 2 is more than 50%, the dielectric ceramic 6
It is presumed that delamination and short-circuit failure occurred due to large sintering shrinkage.

(Embodiment 2) As in Embodiment 1,
After weighing and adding a predetermined amount of the raw material 2 to the calcined raw material 1 in a range of 0 to 70%, the raw material 2 is pulverized and mixed so that the average particle diameter of the ceramic raw material becomes 0.8 to 2.2 μm. The dielectric ceramic materials obtained by adjusting the pulverization times were processed in the same manner as in the first embodiment to produce a sintered body of a chip capacitor and a finished product. The sintered body and the finished product are described in Embodiment 1.
Was evaluated in the same manner as described above, and the results are shown in (Table 2).

[0016]

[Table 2]

As is clear from (Table 2), the calcined raw material 1
In the range of 50 to 90%, there is no occurrence of delamination and short-circuit failure when the mixed raw material has an average particle size of 0.9 to 2.0 μm. If contrast calcined material 1 is more than 90%, or less than 50% mixed
Regardless of the average particle size of the mixed raw material, delamination or short-circuit failure has occurred in any case. The calcined raw material 1 is 50 ~
If the average particle size is smaller than 0.9 μm or larger than 2.0 μm even in the range of 90%, it can be seen that delamination and short-circuit failure have occurred. This is mixed
When the average particle size of the interleaf material is 0.9μm less than the calcined material 1 after milling of grain size and the raw material 2 particle size is substantially equal ku Small
Therefore , the green sheet density is
DOO sintering shrinkage is reduced, palladium internal electrodes 7
It is considered that the difference in the sintering shrinkage ratio between the dielectric ceramic 6 and the internal electrode 7 is large , resulting in delamination between the dielectric ceramic 6 and the internal electrode 7. When the average particle size of the mixed raw material is larger than 2.0 μm, the particle size difference between the calcined raw material 1 and the raw raw material 2 is large , and the particle size of the calcined raw material 1 after pulverization is large.
The green sheet density is low
As the shrinkage increases , the sintering shrinkage becomes uneven inside the dielectric ceramic 6, and as a result, the dielectric ceramic 6
It is thought that cracks occur inside and delamination, particularly short-circuit failure, is likely to occur. From the above, the average particle size after mixing and grinding the calcined raw material 1 and the raw material 2 is 0.9 to 2.
By controlling the thickness within the range of 0 μm, occurrence of delamination and short-circuit failure can be prevented.

[0018]

As described above, the multilayer ceramic capacitor of the present invention in which the calcined raw material and the raw material are mixed in an appropriate amount and the pulverized particle size is controlled, the occurrence of delamination and short circuit is suppressed. The Rukoto.

[Brief description of the drawings]

FIG. 1 is a model diagram showing a state in which a calcined raw material and a raw material are mixed according to an embodiment of the present invention.

FIG. 2 is a model diagram using only calcined raw materials.

FIG. 3 is a model diagram using only raw materials.

FIG. 4 is a plan view showing a printed state of an internal electrode.

FIG. 5 is a longitudinal sectional view of the multilayer ceramic capacitor.

[Explanation of symbols]

 Reference Signs List 1 Calcination raw material 2 Raw material 3 Green sheet 4 Internal electrode 5 Cutting position 6 Dielectric ceramic 7 Internal electrode 8 Invalid layer 9 External electrode

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01G 4/00-4/42

Claims (1)

(57) [Claims] 1. A method for manufacturing a multilayer ceramic capacitor, comprising : sintering a laminate formed by alternately laminating a plurality of green sheet layers and internal electrode layers at a high temperature to form an external electrode at an end thereof; Is mainly composed of palladium
Material is formed by using a for the green sheet layer Sera
90-50% of the calcined raw material and the remaining 10-
50% uncalcined raw material having an average particle size of 0.9
A method for manufacturing a multilayer ceramic capacitor, wherein the multilayer ceramic capacitor is formed by using a mixed raw material having a range of about 2.0 μm .