JP2000277367A - Multilayer ceramic capacitor - Google Patents
Multilayer ceramic capacitorInfo
- Publication number
- JP2000277367A JP2000277367A JP11080702A JP8070299A JP2000277367A JP 2000277367 A JP2000277367 A JP 2000277367A JP 11080702 A JP11080702 A JP 11080702A JP 8070299 A JP8070299 A JP 8070299A JP 2000277367 A JP2000277367 A JP 2000277367A
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- Prior art keywords
- multilayer ceramic
- ceramic capacitor
- internal electrode
- capacitor
- dielectric layer
- Prior art date
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Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、誘電体層と内部電
極層とを交互に積層してなる積層セラミックコンデンサ
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic capacitor comprising alternately laminated dielectric layers and internal electrode layers.
【0002】[0002]
【従来技術】従来、積層セラミックコンデンサは、誘電
体層と内部電極層とを交互に積層してコンデンサ本体を
形成し、内部電極層の一部分を交互に積層体の対向する
側面に露出させ、コンデンサ本体の両端に外部電極を形
成して構成されていた。2. Description of the Related Art Conventionally, a multilayer ceramic capacitor has a capacitor body formed by alternately laminating dielectric layers and internal electrode layers, and exposing a part of the internal electrode layers alternately to opposing side surfaces of the laminate. External electrodes were formed on both ends of the main body.
【0003】このような積層セラミックコンデンサの一
般的な製造方法は、先ず、例えば、誘電体セラミック粉
末を有機バインダーに分散させたセラミックスラリーを
シート状に成形してセラミックグリーンシートを作製
し、スクリーン印刷法などにより、このセラミックグリ
ーンシートの上に導電ペーストで内部電極パターンを印
刷する。[0003] A general method of manufacturing such a multilayer ceramic capacitor is as follows. First, for example, a ceramic slurry in which dielectric ceramic powder is dispersed in an organic binder is formed into a sheet to form a ceramic green sheet, and screen printing is performed. An internal electrode pattern is printed on the ceramic green sheet with a conductive paste by a method or the like.
【0004】そして、この内部電極パターンが印刷され
たセラミックグリーンシートを複数積層し、この積層体
の両側に内部電極パターンが印刷されていないセラミッ
クグリーンシートを複数枚それぞれ積層する。こうして
得られた積層成形体を内部電極層が端面に露出するよう
にチップ状に切断し、これを焼成する。Then, a plurality of ceramic green sheets on which the internal electrode patterns are printed are laminated, and a plurality of ceramic green sheets on which the internal electrode patterns are not printed are laminated on both sides of the laminate. The laminated molded body thus obtained is cut into chips so that the internal electrode layers are exposed at the end faces, and is fired.
【0005】そして、この焼結された積層体を研磨する
ことで、その端面に内部電極層を露出させ、この端面に
導電ペーストを塗布し、これを焼き付けて外部電極を形
成することにより、積層チップコンデンサを作製してい
た。[0005] Then, the sintered laminate is polished to expose an internal electrode layer on its end face, a conductive paste is applied to this end face, and this is baked to form an external electrode. I was making chip capacitors.
【0006】コンデンサ本体11は、図5に示すよう
に、誘電体層12と内部電極層13とを交互に積層して
構成されている。As shown in FIG. 5, the capacitor body 11 is formed by alternately stacking dielectric layers 12 and internal electrode layers 13.
【0007】また、他の積層セラミックコンデンサの製
造方法として、セラミックの積層体を焼成する前に、そ
の端部に予め導電ペーストを塗布し、積層体と導電ペー
ストを同時焼成するという製造方法もある。Further, as another method of manufacturing a multilayer ceramic capacitor, there is a manufacturing method in which a conductive paste is applied in advance to an end portion of a ceramic laminate before firing, and the laminate and the conductive paste are simultaneously fired. .
【0008】さらに、積層体を得る方法も、セラミック
グリーンシートを使用する、いわゆるシート法の他に、
セラミックペーストと導電ペーストとを交互に印刷して
いく、いわゆる印刷法も採用されている。[0008] Further, a method for obtaining a laminate is not only a so-called sheet method using ceramic green sheets, but also a method using a ceramic green sheet.
A so-called printing method in which a ceramic paste and a conductive paste are alternately printed is also employed.
【0009】このような積層セラミックコンデンサで
は、上記積層方法により所望の容量を得ることができ
る。In such a multilayer ceramic capacitor, a desired capacitance can be obtained by the above-described lamination method.
【0010】[0010]
【発明が解決しようとする課題】しかしながら、上記従
来の積層セラミックコンデンサでは、内部電極層と誘電
体層との焼成収縮率、熱膨張率の違いによって発生する
内部応力が大きく、積層数が増すにつれて内部応力が大
きくなり、デラミネーション等の構造欠陥が発生しやす
く、また、静電容量の温度特性が悪化するという問題が
あった。However, in the above-mentioned conventional multilayer ceramic capacitor, the internal stress generated due to the difference in the firing shrinkage and the thermal expansion coefficient between the internal electrode layer and the dielectric layer is large, and as the number of stacked layers increases, There has been a problem that internal stress is increased, structural defects such as delamination are likely to occur, and temperature characteristics of capacitance are deteriorated.
【0011】即ち、内部電極層は金属から構成されてお
り、誘電体層はセラミックスから構成されており、その
焼成段階では内部電極層が誘電体層よりも早い時期に収
縮しようとするため、内部電極層の収縮により誘電体層
の表皮部分が圧縮応力を受ける。That is, the internal electrode layer is made of metal, and the dielectric layer is made of ceramics. At the firing stage, the internal electrode layer tends to shrink earlier than the dielectric layer. The skin portion of the dielectric layer receives compressive stress due to the contraction of the electrode layer.
【0012】また、焼結後の冷却工程では、内部電極層
の熱膨張係数は誘電体層よりも大きいため、内部電極層
は誘電体層よりも早い時期に収縮しようとするため、や
はり、内部電極層の収縮により誘電体層の表皮部分が圧
縮応力を受ける。In the cooling step after sintering, the internal electrode layer tends to shrink earlier than the dielectric layer because the coefficient of thermal expansion of the internal electrode layer is larger than that of the dielectric layer. The skin portion of the dielectric layer receives compressive stress due to the contraction of the electrode layer.
【0013】そして、従来の積層セラミックコンデンサ
では、図5に示すように、誘電体層12は平坦であった
ため、誘電体層12の表皮部分(内部電極層13との境
界部分)に生じた圧縮応力が重畳されて残留し、このよ
うな残留応力は積層数が増加するほど大きくなり、構造
欠陥が発生したり、静電容量の温度特性が悪化するとい
う問題があった。In the conventional multilayer ceramic capacitor, as shown in FIG. 5, since the dielectric layer 12 is flat, the compression generated on the surface of the dielectric layer 12 (boundary portion with the internal electrode layer 13). Stress is superimposed and remains, and such a residual stress increases as the number of layers increases, causing a problem that a structural defect is generated or a temperature characteristic of capacitance is deteriorated.
【0014】本発明は、残留応力を低減することによ
り、デラミネーション等の構造欠陥の発生を抑制できる
とともに、静電容量の温度特性を向上できる積層セラミ
ックコンデンサを提供することを目的とする。An object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing the occurrence of structural defects such as delamination and improving the temperature characteristics of capacitance by reducing residual stress.
【0015】[0015]
【課題を解決するための手段】本発明者は、上記課題に
ついて鋭意検討した結果、積層セラミックコンデンサの
誘電体層に複数の突起状変形領域を形成すると、この変
形領域において内部応力の一部が解放され、積層セラミ
ックコンデンサの残留応力を小さくすることができるこ
とを見出し、本発明に至った。Means for Solving the Problems As a result of intensive studies on the above-mentioned problems, the present inventor has found that when a plurality of projecting deformation regions are formed in a dielectric layer of a multilayer ceramic capacitor, a part of the internal stress is reduced in the deformation regions. It has been found that it has been released and the residual stress of the multilayer ceramic capacitor can be reduced, and the present invention has been achieved.
【0016】即ち、本発明の積層セラミックコンデンサ
は、誘電体層と内部電極層とを交互に積層してなるコン
デンサ本体の両端に外部電極を設けた積層セラミックコ
ンデンサであって、前記誘電体層に、積層方向に突出す
る複数の突出部を所定間隔を置いて形成したものであ
る。That is, the multilayer ceramic capacitor of the present invention is a multilayer ceramic capacitor in which external electrodes are provided at both ends of a capacitor body in which dielectric layers and internal electrode layers are alternately stacked, wherein the dielectric layers are A plurality of protrusions projecting in the stacking direction are formed at predetermined intervals.
【0017】ここで、突出部の積層方向への突出高さh
が0.5〜10.0μmであることが望ましい。また、
複数の突出部は、10〜300μmの間隔xを置いて形
成されていることが望ましい。Here, the height h of the protrusion in the stacking direction of the protrusion is h.
Is desirably 0.5 to 10.0 μm. Also,
It is desirable that the plurality of protrusions be formed at intervals x of 10 to 300 μm.
【0018】[0018]
【作用】本発明の積層セラミックコンデンサは、内部電
極層は金属から構成されており、誘電体層はセラミック
スから構成されているため、焼成段階および焼結後の冷
却工程では、内部電極層の収縮により誘電体層の表皮部
分が圧縮応力を受けるが、本発明の積層セラミックコン
デンサでは、誘電体層に、積層方向に突出する複数の突
出部を所定間隔を置いて形成したので、誘電体層の表皮
部分に生じた圧縮応力が突出部で各方向に分散され、残
留応力が低下する。これにより、デラミネーション等の
構造欠陥が抑制され、さらに静電容量の温度特性を向上
できる。In the multilayer ceramic capacitor of the present invention, since the internal electrode layer is made of metal and the dielectric layer is made of ceramic, the internal electrode layer shrinks during the firing step and the cooling step after sintering. However, in the multilayer ceramic capacitor of the present invention, a plurality of protrusions protruding in the laminating direction are formed at predetermined intervals on the dielectric layer. The compressive stress generated in the skin portion is dispersed in each direction at the protrusion, and the residual stress decreases. Thereby, structural defects such as delamination are suppressed, and the temperature characteristics of capacitance can be further improved.
【0019】また、突出部の積層方向への突出高さhを
0.5〜10.0μmとすることにより、あるいは複数
の突出部を10〜300μmの間隔xを置いて形成する
ことにより、残留応力をさらに有効に低減できる。The height h of the protrusion in the stacking direction of the protrusions is set to 0.5 to 10.0 μm, or the plurality of protrusions are formed at an interval x of 10 to 300 μm so that the residual Stress can be more effectively reduced.
【0020】[0020]
【発明の実施の形態】本発明の積層セラミックコンデン
サは、図1に示すように、コンデンサ本体1の両端に外
部電極2を形成して構成されており、コンデンサ本体1
は、図2に示すように、誘電体層3と内部電極層4とを
交互に積層して構成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, a multilayer ceramic capacitor according to the present invention is formed by forming external electrodes 2 at both ends of a capacitor main body 1.
Is formed by alternately stacking dielectric layers 3 and internal electrode layers 4 as shown in FIG.
【0021】そして、誘電体層3には、図2乃至図4に
示すように、積層方向に突出する複数の突出部7が所定
間隔xを置いて形成されている。この突出部7は半球面
形状とされ、突出部7の積層方向への突出高さhは0.
5〜10.0μmとされており、この突出部7の誘電体
層平面方向の最大幅Lは、5〜100μmとされてい
る。また、複数の突出部7は、誘電体層3に10〜30
0μmの間隔xを置いて形成されている。As shown in FIGS. 2 to 4, a plurality of protrusions 7 protruding in the laminating direction are formed on the dielectric layer 3 at predetermined intervals x. The protruding portion 7 has a hemispherical shape, and the protruding height h of the protruding portion 7 in the laminating direction is 0.
The maximum width L of the protrusion 7 in the dielectric layer plane direction is 5 to 100 μm. The plurality of protrusions 7 are provided on the dielectric layer 3 by 10 to 30.
It is formed with an interval x of 0 μm.
【0022】ここで、突出部7の積層方向への突出高さ
hを0.5〜10.0μmとしたのは、この範囲ならば
内部応力を充分に低減できるからである。つまり、突出
高さhが0.5μm以下の場合、内部応力が十分に緩和
されず、静電容量の温度特性変化率の向上効果が小さい
からである。一方、10.0μmを越えると、グリーン
シートの破損によるショート故障が発生しやすくなるか
らである。突出部7の積層方向への突出高さhは、2.
0〜5.0μmであることが望ましい。Here, the protruding height h of the protruding portion 7 in the laminating direction is set to 0.5 to 10.0 μm because the internal stress can be sufficiently reduced in this range. That is, when the protrusion height h is 0.5 μm or less, the internal stress is not sufficiently relaxed, and the effect of improving the rate of change in temperature characteristics of capacitance is small. On the other hand, if it exceeds 10.0 μm, short-circuit failure due to breakage of the green sheet is likely to occur. The height h of the protrusion 7 in the stacking direction is 2.
Desirably, it is 0 to 5.0 μm.
【0023】また、複数の突出部7を10〜300μm
の間隔xを置いて形成したのは、間隔Xが10μmより
も小さい場合にはグリーンシートの破損によるショート
故障が発生しやすくなり、一方、300μmを越えると
内部応力が十分に緩和されず、静電容量の温度特性変化
率が大きくなりやすいからである。間隔xは、20〜1
00μmであることが望ましい。Further, the plurality of protrusions 7 are
When the interval X is smaller than 10 μm, a short failure due to breakage of the green sheet easily occurs. On the other hand, when the interval X exceeds 300 μm, the internal stress is not sufficiently relaxed, and This is because the rate of change in the temperature characteristic of the capacitance tends to increase. The interval x is 20 to 1
Desirably, it is 00 μm.
【0024】さらに、突出部7の誘電体層平面方向の最
大幅Lを5〜100μmとしたのは、最大幅Lが5μm
よりも小さい場合には、グリーンシートの破損によるシ
ョート故障が発生しやすく、100μmを越えると内部
応力が十分に緩和されず、静電容量の温度特性変化率が
大きくなりやすいからである。最大幅Lは10〜50μ
mが望ましい。Further, the maximum width L of the protrusion 7 in the dielectric layer plane direction is set to 5 to 100 μm because the maximum width L is 5 μm.
If it is smaller than this, short-circuit failure due to breakage of the green sheet is likely to occur, and if it exceeds 100 μm, the internal stress is not sufficiently relaxed, and the rate of temperature characteristic change of capacitance tends to increase. Maximum width L is 10-50μ
m is desirable.
【0025】本発明の積層セラミックコンデンサは、例
えば、先ず、誘電体層となるグリーンシートを作製す
る。グリーンシートは、例えば、チタン酸バリウムを主
成分とし、酸化イットリウム、炭酸マンガン及び酸化マ
グネシウムを加えた誘電体粉末に、水及び分散剤を加
え、ボールミルにて混合粉砕した後、有機バインダーを
混合し、得られたスラリーを所定厚みのテープ状に成形
することで得られる。In the multilayer ceramic capacitor of the present invention, for example, first, a green sheet to be a dielectric layer is prepared. The green sheet contains, for example, barium titanate as a main component, yttrium oxide, a dielectric powder to which manganese carbonate and magnesium oxide are added, water and a dispersant, and after mixing and grinding in a ball mill, an organic binder is mixed. The obtained slurry is formed into a tape having a predetermined thickness.
【0026】誘電体層の材料としては、チタン酸バリウ
ムを主成分とし、この主成分100モル部に対して、酸
化マグネシウムを0.5〜8モル部、炭酸マンガンを
0.05〜0.5モル部、酸化イットリウムを0.3〜
4モル部添加含有したものを用いることが誘電率などの
特性を向上する点から望ましい。As a material of the dielectric layer, barium titanate is used as a main component, and 0.5 to 8 mole parts of magnesium oxide and 0.05 to 0.5 manganese carbonate are added to 100 mole parts of the main component. Molar parts, yttrium oxide 0.3 ~
It is desirable to use those containing 4 mol parts in terms of improving properties such as dielectric constant.
【0027】導体ペーストは、例えば、ニッケル粉末に
有機可塑剤を加えたペーストを作製する。As the conductor paste, for example, a paste obtained by adding an organic plasticizer to nickel powder is prepared.
【0028】そして、上記誘電体層のグリーンシートの
上面に、例えば、スクリーン印刷法によりニッケルの導
体ペーストを塗布する。次に、規則的な凸部(半球面形
状)を持った第1圧子と、この第1圧子の凸部に対応す
る凹部を持った第2圧子とにより、導体ペーストを塗布
したグリーンシートを挟持し、グリーンシート表面に突
出部を所定間隔で形成する。次に、この突出部を重ねる
ようにして、突出部が形成されたグリーンシートを積層
する。Then, a conductive paste of nickel is applied to the upper surface of the green sheet of the dielectric layer by, for example, a screen printing method. Next, the first indenter having regular convex portions (hemispherical shape) and the second indenter having concave portions corresponding to the convex portions of the first indenter sandwich the green sheet coated with the conductive paste. Then, protrusions are formed on the surface of the green sheet at predetermined intervals. Next, the green sheets on which the protrusions are formed are stacked so that the protrusions overlap.
【0029】そして、得られた積層成形体を所定寸法に
切断した後、酸素分圧3×10-8〜3×10-3Pa、温
度1150〜1300℃で0.5〜3時間焼成し、次
に、酸素分圧1×10-2〜2×104 Pa、温度900
〜1150℃で1〜5時間熱処理する。Then, after cutting the obtained laminated molded body into predetermined dimensions, it is baked at an oxygen partial pressure of 3 × 10 −8 to 3 × 10 −3 Pa at a temperature of 1150 to 1300 ° C. for 0.5 to 3 hours. Next, an oxygen partial pressure of 1 × 10 −2 to 2 × 10 4 Pa and a temperature of 900
Heat treatment at 1150 ° C. for 1 to 5 hours.
【0030】次に、銅粉末に有機可塑剤を加えたペース
トを作製し、このペーストを、前記内部電極層と交互に
電気的に接続するように焼結体に焼き付けて積層セラミ
ックコンデンサを作製する。Next, a paste in which an organic plasticizer is added to copper powder is prepared, and the paste is baked on a sintered body so as to be alternately electrically connected to the internal electrode layers, thereby preparing a multilayer ceramic capacitor. .
【0031】尚、上記例では、グリーンシートに、規則
的な凸部を持った第1圧子と、この第1圧子の凸部に対
応する凹部を持った第2圧子とにより、突出部を形成し
たが、突出部が形成できる方法であれば、どのような方
法を採用しても良い。In the above example, a protruding portion is formed on the green sheet by the first indenter having a regular convex portion and the second indenter having a concave portion corresponding to the convex portion of the first indenter. However, any method may be adopted as long as the protrusion can be formed.
【0032】また、上記例では、突出部7を半球面形状
とした例について説明したが、本発明では、積層方向に
突出するものであれば、例えば、円錐形状、四角錘形状
々、どのような形状であっても良い。In the above example, the protruding portion 7 has a hemispherical shape. However, in the present invention, if the protruding portion 7 protrudes in the stacking direction, for example, a conical shape, a quadrangular pyramid shape, etc. Shape may be used.
【0033】[0033]
【実施例】先ず、チタン酸バリウムを主成分とし、この
主成分100モル部に対して、酸化イットリウムを1モ
ル部、酸化マグネシウムを2モル部、炭酸マンガンを
0.1モル部添加した誘電体粉末に、水及び分散剤を加
え、ZrO2 ボールを用いたボールミルにて混合粉砕し
た後、有機バインダーを混合し、得られたスラリーを厚
み13μmのテープ状に成形した。DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a dielectric material containing barium titanate as a main component, 1 mole portion of yttrium oxide, 2 mole portions of magnesium oxide, and 0.1 mole portion of manganese carbonate with respect to 100 mole portions of the main component. Water and a dispersant were added to the powder, mixed and pulverized by a ball mill using ZrO 2 balls, and then an organic binder was mixed. The resulting slurry was formed into a 13 μm-thick tape.
【0034】一方、内部電極として、ニッケル粉末に有
機可塑剤を加えたペーストを用意し、上記テープ上にス
クリーン印刷法にて形成した。次に、100μm間隔の
規則的な直径20μmの半球形状の凸部を持った第1圧
子と、この第1圧子の凸部に対応する凹部を持った第2
圧子とにより、導体ペーストを塗布したテープを挟持
し、テープ表面に半球面状の突出部を形成した。On the other hand, as an internal electrode, a paste prepared by adding an organic plasticizer to nickel powder was prepared, and formed on the tape by a screen printing method. Next, a first indenter having a regular hemispherical protrusion having a diameter of 20 μm at intervals of 100 μm, and a second indenter having a recess corresponding to the protrusion of the first indenter.
The tape coated with the conductive paste was sandwiched by the indenter, and a hemispherical protrusion was formed on the tape surface.
【0035】次に、この突出部を重ねるようにして突出
部の形成されたテープを積層した。Next, the tape having the protruding portions was laminated so that the protruding portions were overlapped.
【0036】このとき各々の層にわたって突出部が重な
るようにして積層成形体を形成した。At this time, a laminated molded body was formed such that the protrusions overlapped over each layer.
【0037】比較のため、突出部を形成しないテープを
積層した積層成形体も用意した。For the purpose of comparison, a laminated molded article in which tapes having no projections were laminated was also prepared.
【0038】得られた成形体を切断した後、酸素分圧1
×10-6Pa、温度1260℃で2時間焼成し、次に、
酸素分圧1×10Pa、温度1000℃で1時間熱処理
を行った。次に、焼結体の両端面に銅ペーストを800
℃で焼き付け、内部電極と電気的に接続する外部電極を
形成し、誘電体層厚み9μm、有効誘電体層数100
層、外形寸法2mm×1.2mm×1.2mm、有効電
極面積0.78mm2 の積層コンデンサを得た。尚、突
出部の積層方向への突出高さh、誘電体層平面方向の最
大幅L、複数の突出部間の間隔xを種々変化させ、積層
コンデンサを作製した。After cutting the obtained molded body, the oxygen partial pressure was set to 1
Baking at × 10 −6 Pa and a temperature of 1260 ° C. for 2 hours,
Heat treatment was performed at an oxygen partial pressure of 1 × 10 Pa and a temperature of 1000 ° C. for 1 hour. Next, a copper paste was applied to both end surfaces of the sintered body for 800 minutes.
C. to form an external electrode that is electrically connected to the internal electrode. The thickness of the dielectric layer is 9 μm, and the number of effective dielectric layers is 100.
A multilayer capacitor having a layer, outer dimensions of 2 mm × 1.2 mm × 1.2 mm, and an effective electrode area of 0.78 mm 2 was obtained. In addition, the height h of the protrusions in the stacking direction, the maximum width L in the plane direction of the dielectric layer, and the distance x between the plurality of protrusions were variously changed to manufacture a multilayer capacitor.
【0039】次にこれらの試料を、LCRメーター42
84Aを用いて、周波数1.0kHz、入力信号レベル
1.0Vrmsにて+25℃及び+125℃における静
電容量を測定した。また、外観検査によりデラミネーシ
ョンの発生の有無を観察した。その結果を表1に記載し
た。Next, these samples were transferred to an LCR meter 42
The capacitance was measured at + 25 ° C. and + 125 ° C. using 84A at a frequency of 1.0 kHz and an input signal level of 1.0 Vrms. In addition, the occurrence of delamination was observed by appearance inspection. The results are shown in Table 1.
【0040】[0040]
【表1】 [Table 1]
【0041】この表1から、誘電体層が平面状に形成さ
れた、つまり突出部が形成されていない比較例の場合
(試料No.1)、+25℃の静電容量に対する125℃
の静電容量の変化率は平均−16%であったのに対し
て、本発明の試料では、−14%以下で静電容量の温度
変化率が小さいものであった。さらに、比較例の試料で
は試料300個のうち3個にデラミネーションが発生し
ていたのに対して、本発明の試料ではデラミネーション
の発生はなかった。As shown in Table 1, in the case of the comparative example in which the dielectric layer was formed in a planar shape, that is, in which the protrusion was not formed (Sample No. 1), 125 ° C. with respect to the capacitance of + 25 ° C.
The rate of change of the capacitance was -16% on average, whereas the rate of change of the temperature of the capacitance was small at -14% or less in the sample of the present invention. Furthermore, in the sample of the comparative example, delamination occurred in three out of 300 samples, whereas no delamination occurred in the sample of the present invention.
【0042】[0042]
【発明の効果】本発明の積層セラミックコンデンサは、
誘電体層に、積層方向に突出する複数の突出部を所定間
隔を置いて形成したので、誘電体層の表皮部分に生じた
圧縮応力が突出部で各方向に分散され、残留応力が低下
し、これにより、デラミネーション等の構造欠陥が抑制
され、さらに静電容量の温度特性を向上できる。The multilayer ceramic capacitor of the present invention has the following features.
Since a plurality of protrusions protruding in the stacking direction are formed at predetermined intervals on the dielectric layer, the compressive stress generated in the skin portion of the dielectric layer is dispersed in the protrusions in each direction, and the residual stress is reduced. Thereby, structural defects such as delamination are suppressed, and the temperature characteristics of capacitance can be further improved.
【0043】また、突出部の積層方向への突出高さhを
0.5〜10.0μmとすることにより、あるいは複数
の突出部を、10〜300μmの間隔xを置いて形成す
ることにより、残留応力をさらに有効に低減できる。The height h of the protrusions in the stacking direction is 0.5 to 10.0 μm, or a plurality of protrusions are formed at intervals x of 10 to 300 μm. The residual stress can be reduced more effectively.
【図1】本発明の積層セラミックコンデンサを示す側面
図である。FIG. 1 is a side view showing a multilayer ceramic capacitor of the present invention.
【図2】図1のコンデンサ本体の断面図である。FIG. 2 is a sectional view of the capacitor body of FIG. 1;
【図3】図2の横断面図である。FIG. 3 is a cross-sectional view of FIG.
【図4】突出部およびその近傍を示す斜視図である。FIG. 4 is a perspective view showing a protruding portion and its vicinity.
【図5】従来の積層セラミックコンデンサのコンデンサ
本体の断面図である。FIG. 5 is a sectional view of a capacitor body of a conventional multilayer ceramic capacitor.
1・・・コンデンサ本体 2・・・外部電極 3・・・誘電体層 4・・・内部電極層 7・・・突出部 DESCRIPTION OF SYMBOLS 1 ... Capacitor main body 2 ... External electrode 3 ... Dielectric layer 4 ... Internal electrode layer 7 ... Protrusion
Claims (3)
なるコンデンサ本体の両端に外部電極を設けた積層セラ
ミックコンデンサであって、前記誘電体層に、積層方向
に突出する複数の突出部を所定間隔を置いて形成したこ
とを特徴とする積層セラミックコンデンサ。1. A multilayer ceramic capacitor in which external electrodes are provided at both ends of a capacitor body in which dielectric layers and internal electrode layers are alternately laminated. A multilayer ceramic capacitor, wherein the protrusions are formed at predetermined intervals.
〜10.0μmであることを特徴とする請求項1記載の
積層セラミックコンデンサ。2. The projection height h of the projection in the stacking direction is 0.5.
The multilayer ceramic capacitor according to claim 1, wherein the thickness of the multilayer ceramic capacitor is in the range of ~ 10.0m.
xを置いて形成されていることを特徴とする請求項1ま
たは2記載の積層セラミックコンデンサ。3. The multilayer ceramic capacitor according to claim 1, wherein the plurality of protrusions are formed at intervals x of 10 to 300 μm.
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7505247B2 (en) * | 2005-03-30 | 2009-03-17 | Samsung Electro-Mechanics Co., Ltd. | Multi-layer ceramic capacitor and production method thereof |
JPWO2013175945A1 (en) * | 2012-05-24 | 2016-01-12 | 株式会社村田製作所 | Multilayer ceramic electronic components |
US9922767B2 (en) | 2014-09-30 | 2018-03-20 | Murata Manufacturing Co., Ltd. | Ceramic electronic component and manufacturing method therefor |
CN109119247A (en) * | 2017-06-26 | 2019-01-01 | 太阳诱电株式会社 | Laminated ceramic capacitor |
JP2019029379A (en) * | 2017-07-25 | 2019-02-21 | Tdk株式会社 | Electronic component and manufacturing method thereof |
-
1999
- 1999-03-25 JP JP08070299A patent/JP3706497B2/en not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7505247B2 (en) * | 2005-03-30 | 2009-03-17 | Samsung Electro-Mechanics Co., Ltd. | Multi-layer ceramic capacitor and production method thereof |
JPWO2013175945A1 (en) * | 2012-05-24 | 2016-01-12 | 株式会社村田製作所 | Multilayer ceramic electronic components |
US9922767B2 (en) | 2014-09-30 | 2018-03-20 | Murata Manufacturing Co., Ltd. | Ceramic electronic component and manufacturing method therefor |
CN109119247A (en) * | 2017-06-26 | 2019-01-01 | 太阳诱电株式会社 | Laminated ceramic capacitor |
JP2019029379A (en) * | 2017-07-25 | 2019-02-21 | Tdk株式会社 | Electronic component and manufacturing method thereof |
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