JPH06168098A - Decimal number checking device - Google Patents

Abstract

PURPOSE:To attain the high speed of check processing for an unpack type or a pack type decimal number. CONSTITUTION:Non-decimal number detection. incorrect zone detection and non-normalized code detection are executed in parallel for each digit of a decimal number by a decimal number check circuit 22 constituted of a non-decimal number detection circuit, an incorrect zone detection circuit, and an unnormalized code detection circuit. Then, the detected result of each digit is edited by a decimal number check signal selection and editing circuit 25 correspondingly about the non-decimal number detection, the incorrect zone detection, and the unnormalized code detection, and the validity of the decimal number is checked in conformity with this edited result. Accordingly, the check processing can be executed in parallel for plural digits to constitute the decimal number, and the check of the decimal number can be executed at high speed compared with the case that it is checked one digit at a time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decimal number checking device, and more particularly to a technique for speeding up a decimal number checking instruction and a speed for checking a decimal number when executing a decimal arithmetic instruction.

[0002]

2. Description of the Related Art Decimal numbers have a packed format and an unpacked format, which are given as follows. (1) Decimal number in packed format For example, in the case of 4-byte data, "ddddddds" d: decimal number s: sign This packed format decimal number has 4 bits as one digit, and the code is stored in the least significant digit. (2) Decimal number in unpack format For example, in the case of 4-byte data, "zdzdzdsd" d: Decimal number s: Code z: Zone

In this unpacked decimal number, 8 bits is 1
Digit, and zone (0x0
3), a decimal number is stored in the lower 4 bits. The code is stored in the zone part of the least significant digit. The specifications for such a decimal check are as follows. (B) Normalization of code When the code is positive, it is 0x3, and when it is negative, it is 0xB. (B) Decimal number check instruction specification The operand access method of an instruction that handles a decimal number is a descending order access in which the word on the LSB side of the operand is accessed toward the word on the MSB side. (C) Pack format decimal number check instruction According to the pack format, it is checked whether the code part is normalized or there is a non-decimal number in the digit part, and the status indicator is set. (D) Unpacked decimal check instruction

According to the unpack format,
The state indicator is set by checking whether the code part is normalized, the digit part has a non-decimal number, and the zone part has no illegal zone. Conventionally, in a CPU having a register file inside the CPU, pack format decimal number check instruction processing has been performed as shown in the flow of FIG.

That is, the operand data is read into the register file in the CPU (step S11), and one digit of the operand data read into the register file is taken out to the digit check register RML (step S1).
2) The code is normalized / positive / negative is checked (step S13), the next digit is taken out, and a decimal number is checked (steps S14 and S15).

When the operand data remains, the operation of extracting the next digit and checking the decimal number is repeated twice every time until all the operand data are processed (steps S17, S18, S19, S20, S2).
1). Then, when all the operand data have been processed or a non-decimal number is found, the instruction processing is ended (step S22). The check result of the subroutine is reflected in the status indicator.

The unpacked decimal check command processing is basically the same as the packed decimal check instruction processing, but as shown in FIG. 6, the first digit is a decimal check (step S31). The second digit repeats the sign normalization / plus / minus check (step S32), and then the decimal number check (step S33) and the zone check (step S34). The check result of the subroutine of FIG. 6 is reflected in the status indicator as in the case of FIG.

As described above, in the conventional decimal number check processing, the operand data is inspected digit by digit. Therefore, the number of execution steps of firmware increases. Further, even when a decimal number check is performed using a conventional arithmetic unit, there are problems such as a large number of firmware execution steps.

[0009]

Conventionally, since the operand data is inspected one digit at a time, the number of execution steps of the firmware increases, and if the number of digits forming the decimal number increases, the decimal number check is often performed. It had the drawback of requiring time.

The present invention has been made in view of the above point, and a decimal number check device capable of performing a decimal number check at high speed by enabling parallel checking of a plurality of digits forming a decimal number. The purpose is to provide.

[0011]

Means and Actions for Solving the Problems
In a decimal number check device for checking the legitimacy of a packed or unpacked decimal number consisting of a plurality of digits, a plurality of digits constituting the decimal number are input in parallel, and each corresponding digit in the plurality of digits is input. In order to perform non-decimal number detection, illegal zone detection, and denormalization code detection in parallel, it is composed of multiple non-decimal number detection circuits, illegal zone detection circuits, and denormalization code detection circuits. The decimal number checking means and the detection result of each digit obtained from the decimal number checking means are edited in correspondence with the non-decimal number detection, the illegal zone detection, and the denormalization code detection, respectively, and the decimal result is edited according to the edited result. And a means for checking the correctness of the base number.

In this decimal number checking device, a non-decimal number is detected for each digit by a decimal number checking means composed of a plurality of non-decimal number detecting circuits, an illegal zone detecting circuit, and a denormalization code detecting circuit. , Illegal zone detection,
And denormalized code detection is performed in parallel. And the detection result of each digit is non-decimal number detection, illegal zone detection,
And the denormalized code detection are edited correspondingly, and the correctness of the decimal number is checked according to the edited result. Therefore, the check process can be executed in parallel for a plurality of digits forming a decimal number, and the decimal number check can be performed at a higher speed than in the case of checking the digits one by one.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a decimal number check device according to an embodiment of the present invention. This decimal number check device includes a byte shifter 21 and a decimal number check circuit 2.
2, an instruction decode circuit 23, a first operand shift timing generation circuit 24, and a decimal number check signal selection editing circuit 25.

The byte shifter 21 is for performing fill control and byte shift of memory read data, and fill control is performed so that operand data read from the memory is aligned with a word boundary (when the fill character is in unpacked decimal number, 0x30, 0x00 for packed decimal, and shift operation is performed. As a result, all the decimal digits of 4 bytes, for example, are supplied to the decimal number check circuit 22 in parallel.

The decimal number check circuit 22 is for detecting a non-decimal number, an illegal zone, and a denormalization code of the read data which has been shifted to have all the digits aligned.
The decimal number check circuit 22 performs a decimal number check on each digit (4 bit unit) of the byte-shifted data, and outputs a non-decimal number circuit,
An illegal zone detection circuit that performs a zone check on the upper 4 bits of each byte of the input data and outputs a signal indicating detection of an illegal zone, and an upper 4 bits / lower 4 bits of the lower 1 byte (LSB side) of the input data
And a denormalization code detection circuit that outputs a signal indicating the detection of the denormalization code. The result of non-decimal number, illegal zone, and denormalization code detection is output to the decimal number check signal selection editing circuit 25.

The instruction decoding circuit 23 is for checking whether the instruction being processed is in the unpacked format or the packed format. The detection result is a decimal check signal selection editing circuit 2
5 is output.

The 1st operand shift timing generation circuit 24 is for generating a signal indicating the step in which the first operand data including the code field is shifted, and the signal is a signal indicating the presence of the denormalized code. Is output to the decimal check signal selection / editing circuit 25.

The decimal check signal selection / editing circuit 25 is for detecting a data abnormality, and the instruction decoding circuit 23
Is controlled by the decode result signal from the 1st operand shift timing generation circuit 24,
Output of the decimal number check circuit 22 (non-decimal number discovery signal, illegal zone discovery signal, denormalization code discovery signal) and 2 described later
One flag as input, along with the check format (packed format / unpacked format), a signal indicating whether a non-decimal number exists in one word of read operand data, a signal indicating whether an illegal zone exists, a non- It outputs a signal indicating whether the normalization code was present. FIG. 2 shows an example of a concrete configuration of the decimal number check circuit 22 for 4-byte data.

The decimal number check circuit 22 comprises a non-decimal number detection circuit (d) 31, an illegal zone detection circuit (z) 32, and a denormalized code detection circuit (s) 33. The decimal number check circuit 22 receives the data shifted by the byte shifter 21 so as to match the word boundary, and outputs a non-decimal number detection signal of 8 bits, an illegal zone detection signal of 4 bits, and 2b.
The denormalized code detection signal of it is output.

Here, inputs IN <0: 3>, ..., IN
<28:31> is 4 bits on the MSB side of the decimal number, ...
..., 4 bits on the LSB side, respectively, and the output D <0: 7> is a non-decimal number detection signal, Z <0: 3.
> Is an illegal zone detection signal, and S <0: 1> is a denormalization code detection signal. The non-decimal number detection circuit (d) 31 outputs the following signal (D) with respect to the input signal (IN). D <n> = IN <4n> * (IN <4n + 1> + IN <4n + 2>) n = 0 to 7 The illegal zone detection circuit 32 outputs the following signal (Z) with respect to the input signal (IN). Z <m> = {(IN <8m>) ** (IN <8m + 1>) * IN <8m + 2> * IN <8m + 3>} _m = 0 to 3 Here, ￣ indicates the inversion logic. Denormalization code detection circuit 3
3 outputs the following signal (S) in response to an 8-bit input (IN <24:31>). S <k> = {(IN <4k + 25>)-* IN <4k + 26> * IN <4k + 27>}-k = 0 to 1 In FIG. 3, the decimal number check signal selection editing circuit 25 for 4-byte data is concrete. An example of the configuration is shown.

The first word (word on the LSB side of the operand) of both the packed format / unpacked format has a code field. Also, the format differs between packed and unpacked formats when performing decimal check. Therefore, the decimal check signal selection / editing circuit 25 uses a signal indicating the first word of the operand or an unpacked instruction as a control signal, and outputs the decimal check circuit 22 and each of the two types of abnormality detection flags. Write data to the flag is generated from the data, the check result is stored, and this is output as an abnormality detection signal.

That is, the decimal check signal selection editing circuit 25 includes a pack format non-decimal number detection circuit 41, an unpack format non-decimal number detection circuit 42, a selector 43, a flag register 44, an illegal zone detection circuit 45, and a flag register 46. , A selector 47, and a flag register 48 are provided. The pack format non-decimal number detection circuit 41 detects a pack format non-decimal number in word units (4 bytes), and executes the following logic. ERRDP = D <0> + D <1> + D <2> + D <3> + D <4> + D <5> + D <6> + (D <7> * $ 1st￣) + FERRD

Here, the value of the flag register 44 (FER
The reason why RD) is added to the logical sum is that errors are accumulated for a series of decimal read instructions and error detection is performed in instruction units. Also, D <7> * $ 1st￣ is
Since the value of D <7> is a sign when the 1st operand is shifted, it is for invalidating D <7> at that time. The unpacked non-decimal number detection circuit 42 detects an unpacked non-decimal number in word units (4 bytes), and executes the following logic. ERRDU = D <1> + D <3> + D <5> + D <7> + FERRD

Here, the value of the flag register 44 (FER
The reason why RD) is added to the logical sum is that errors are accumulated for a series of decimal read instructions and error detection is performed in instruction units.

The selector 43 selects the output of the unpacked non-decimal number detection circuit 42 in the case of the unpacked decimal number check instruction, and selects the output of the packed type non-decimal number detection circuit 41 otherwise. Flag register 44
Indicates the detection of a non-decimal number, and is written when the data is aligned by the shift. The illegal zone detection circuit 45 executes the following logic in order to detect the illegal zone in units of words. ERRZ = Z <0> + Z <1> + Z <2> + (Z <3> * $ 1st￣) + FERRZ

Here, the value of the flag register 46 (FER
The reason why RZ) is added to the logical sum is that errors are accumulated for a series of decimal-numbered read instructions and error detection is performed in units of instructions. In addition, D <3> * $ 1st
Since the value of D <3> is a sign when the 1st operand is shifted, it is for invalidating D <3> at that time.

The flag register 46 indicates the detection of an illegal zone, and is written when the data is prepared by the shift when the unpacked decimal number check instruction is executed. Further, the writing of the flag register 46 is disabled in the pack format.

The selector 47 selects a denormalized code check signal in the decimal format. Flag register 4
8 indicates the detection of the denormalized code, which is written when the first operand is shifted.

Next, referring to the flow chart of FIG.
The operation of the decimal number check process will be described. Here, CP
Assume a system in which read data is read in the second step after U sends a memory read command and shift operation is performed.

At the time of executing an instruction, the non-decimal number detection flag register 44, the illegal zone detection flag register 46, and the denormalization code detection flag register 48 are cleared before the control of the instruction processing becomes the firmware operation in advance.

When the instruction execution control is a firmware operation, it is first checked whether or not the memory data need to be pre-read in order to perform the shift operation, and if so, the pre-reading is performed (steps S41 and S42). Next, the first memory read command for operand read is sent (step S43).

Then, it is checked whether or not there is data remaining to be read in the next step (step S44), and if there is remaining data, a memory command for reading the next operand data is sent out, and at the same time, the operand data required two steps before is read. A radix check is performed, and the process branches to a step for checking whether there is data to be read (step S4).
5).

At this time, the 1st operand shift timing generation circuit 24 notifies the decimal number check signal selection / editing circuit 25 that the word processed in this step is the first operand data, and the decimal number check circuit 22. Has been decoded at the start of instruction execution, it is processed as the first operand (word having a sign part) in a format suitable for the instruction format.
The result is stored in the three flag registers 44, 46 and 48. However, in the case of packed format decimal number processing instructions,
The write to the illegal zone detection flag register 46 is disabled.

Further, when the operand data remains, the memory read command is sent, the decimal number is checked, and the branch is performed (step S45). In the subsequent decimal check, since there is no notification from the 1st operand shift timing generation circuit 24, the code part is not checked. That is, no write to the denormalization code detection flag register 48 occurs. The above loop is repeated until the memory read command for the last word of the operand data is sent.

When the memory read command for the last word of the operand data is sent, the process branches at step S44 and the decimal number of the last word is checked (step S46). At this time, the lacking part in the last word is 0x00 for packed decimal processing and 0x30 for unpacked decimal processing by fill control.
Will not affect the check result.

After that, the status indicator is set (step S
47), the instruction processing is ended (step S48). In this method, the decimal number check process is completed only by reading the operand data.

In the above description, one memory command is used for 1
Although the word is read, the same operation can be performed in the case where a memory command in which a plurality of words are sequentially read by one memory command can be used.

In addition, in the decimal number operation instruction, the decimal number check can be performed before the operand is read by performing the fill control in each instruction in the packed format process or the unpacked format process. At this time, a decimal number check is performed using the non-decimal number detection flag. If this method is used, the decimal number check processing is completed by reading the operand data.

As described above, in this embodiment, the decimal number check circuit 22 composed of the non-decimal number detection circuit 31, the illegal zone detection circuit 32, and the denormalization code detection circuit 33 causes each digit of the decimal number to be changed. On the other hand, non-decimal number detection, illegal zone detection, and denormalization code detection are performed in parallel. The detection result of each digit corresponds to the non-decimal number detection, the illegal zone detection, and the denormalization code detection, respectively, and the decimal number check signal selection editing circuit 25
Edited by, and the decimal correctness is checked according to the edited result. Therefore, the check process can be executed in parallel for a plurality of digits forming a decimal number, and the decimal number check can be performed at a higher speed than in the case of checking the digits one by one.

[0041]

As described above, according to the present invention, a plurality of digits forming a decimal number can be checked in parallel, and the decimal number check can be performed at high speed. Therefore, it is possible to obtain effects such as a reduction in the number of steps for the decimal check command processing and a reduction in the number of steps for the decimal check of the operand data when executing the decimal operation instruction.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a decimal number check device according to an embodiment of the present invention.

FIG. 2 is a block diagram of the decimal check device of FIG.
The figure which shows an example of the concrete structure of the decimal number check circuit with respect to byte data.

3 is a block diagram of the decimal check device of FIG.
The figure which shows an example of the concrete structure of the decimal number check signal selection edit circuit with respect to byte data.

FIG. 4 is a flowchart illustrating an operation of a decimal number check process using the decimal number check device of FIG.

FIG. 5 is a flowchart illustrating an operation of a conventional packed decimal check process.

FIG. 6 is a flowchart illustrating an operation of a conventional unpacked decimal number check process.

[Explanation of symbols]

21 ... Byte shifter, 22 ... Decimal number check circuit, 23
... instruction decode circuits 23, 24 ... 1st operand shift timing generation circuits 24, 25 ... Decimal number check signal selection editing circuit, 31 ... Non-decimal number detection circuit, 32 ... Illegal zone detection circuit, 33 ... Denormalized code detection circuit, 41 ... Pack type non-decimal number detection circuit, 42 ... Unpack type non-decimal number detection circuit, 45 ... Illegal zone detection circuit.

Claims (1)

[Claims] 1. A decimal number check device for checking the legitimacy of a packed or unpacked decimal number consisting of a plurality of digits, wherein a plurality of digits constituting the decimal number are input in parallel and Multiple non-decimal digit detection circuits, illegal zone detection circuits, and denormalization codes so that non-decimal digit detection, illegal zone detection, and denormalization code detection are performed in parallel for each corresponding digit. A decimal number check means composed of a detection circuit and a detection result of each digit obtained from the decimal number check means are edited in correspondence with the non-decimal number detection, the illegal zone detection, and the denormalization code detection, respectively, A decimal number check device comprising means for checking the validity of a decimal number according to the edited result.