JPH0616620B2 - Digital phase lock circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a digital phase synchronization circuit in digital data transmission.

(Prior Art) FIG. 2 is a block diagram showing a conventional digital phase synchronization circuit, which is composed of a variable delay line 1, a phase detection circuit 2, and a control circuit 3. The general operation is as follows. First, the phase detection circuit 2 detects the phase of the input data Din, the control circuit 3 determines the phase shift according to the detection information, and the variable delay line 1 obtains a predetermined delay amount based on the determination result. To synchronize the phase of the input data Din.

FIG. 3 is a circuit diagram of the variable delay line 1 and the phase detection circuit 2 shown in FIG. 2, and FIG. 4 is an explanatory diagram for explaining the phase detection and correction operation. In FIG. 3 and FIG. 4, the phase detection circuit 2 outputs S1, S which are outputs of flip-flops (hereinafter, simply FF) 2a, 2b, 2c at time intervals of τ.
It has three samples 2 and S3, and the output data Dout is the sample S2 which is the output of the FF 2b. Control circuit 3
Then, the samples S1, S2 and S3 are compared and the input data Din is phase-corrected by the variable delay line 1 until S1 = S2 = S3 = 1. Further, since the output data Dout is the sample S2 which is the output of the FF2b, the phase fluctuation is immediately detected for the phase fluctuation of the input data Din within the time τ from the sample S2 in the phase-synchronized state. Since the input data Din is corrected by the variable delay line 1 including the buffer 1a, no data error occurs. ("1986 INTER N
ATITONAL ZURICH SEMINAR ON DIGITAL COMMUNICATION
S '' PROCEEDINGS IEEE Catalog 86 CH2277-2 C4 (P97
~ P100)).

(Problems to be Solved by the Invention) However, in the circuit having the above configuration, since the buffer 1a is used as the variable delay line 1, it is difficult to define the delay time of the buffer itself, particularly the minimum value. There is a problem that the variable delay line circuit must be adjusted to obtain the total delay time as designed. This is a big problem because adjustment is difficult especially inside the LS1 where the buffer needs to be chained to form a delay line.

In view of the above problems, it is an object of the present invention to provide a digital phase locked loop circuit that does not require circuit adjustment and is excellent in operation.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a plurality of digital phase synchronization circuits for inputting digital input data and outputting as output data when phase synchronization is established. A clock signal phase variable circuit that repeatedly generates a clock string signal composed of a clock signal and selects the phase of each clock string signal by the selection means according to the phase selection designation, and a clock signal in the clock string signal at each input time point of the clock signal. When the input data is high level, the synchronous state is detected, when the input data includes the low level state, the asynchronous state is detected, and if phase synchronization is established, the output data is output. And a phase detection circuit for outputting the phase detection designation for the selection means when the synchronous state is detected, and the asynchronous And a synchronization control circuit for establishing phase synchronization by updating and controlling the phase selection designation for the selection means so that each clock signal of the clock train signal continuously input when the state is detected corresponds to the synchronization state.

(Operation) According to the present invention, the phase detection circuit monitors the logic level of the digital input data in synchronization with each input time point of the clock signal of the clock sequence signal sent from the clock signal phase varying circuit, and detects each input time point. It is detected that the input data is in the synchronous state when it is at the high level, and is in the asynchronous state when the input data includes the low level state during each input time. If this detection result indicates that the synchronization state is detected, the synchronization control circuit fixes the phase selection designation for the selection means to fix the phase of the clock signal, and the output data is output from the phase detection circuit. When the asynchronous state is detected, the synchronous control circuit updates and controls the phase selection designation for the selecting means so that each clock signal of the clock string signal that is continuously input corresponds to the synchronous state, and the phase synchronization is established.

(Embodiment) FIG. 1 is a circuit diagram showing an embodiment of a digital phase synchronization circuit according to the present invention. In the figure, 10 is a clock signal phase variable circuit, 20 is a phase detection circuit, and 30 is a synchronization control circuit. .

The clock signal phase variable circuit 10 includes a 4-phase clock signal generation circuit 11, a 4/1 selector (hereinafter, simply selector) 1
2, shift register 13 and 2-bit counter (hereinafter,
The counter 14 is simply included. The 4-phase clock signal generation circuit 11 receives the clock signal CLK0 as an input C
It is input to P11, and four-phase clock train signals are output from the outputs Q0 to Q3, respectively. Of the outputs Q0 to Q3 of the four-phase clock signal generation circuit 11, the selector 12 has an output Q0 as an input, an output Q1 as an input, and an output Q as an input.
2. Input the output Q3 to the input, input 12A,
According to the value of 12B, one input is selected from among the inputs 1 to and output from the output 12X. For example, if a low level "0" is input to the input 12A and a high level "1" is input to the input 12B, the input, that is, the output Q1 of the 4-phase clock signal generation circuit 11 is selected and output from the output 12X. It The shift register 13 has a selector 12 at an input 13A.
Input the output 12X and input the clock signal CLK0 C
By inputting as a synchronizing signal to P13 and sequentially shifting the input 13A, a clock signal C1 is output from the output Qa, a clock signal C2 is output from the output Qb, a clock signal C3 is output from the output Qc, and a clock signal C4 is output from the output Qd. The counter 14 operates by inputting the clock signal CLK1 to the input CP14. The output 14Q0 is the input 12A of the selector 12 and the output 14Q1 is the input 12 of the selector 12.
Enter in B. The selector 12 and the counter 14 are
The selecting means is adapted to select the phase of each clock column signal in accordance with the phase selection designation by the synchronization control circuit 30.

The phase detection circuit 20 includes a D-type flip-flop (hereinafter simply referred to as DFF) 21 to 25, an inverter 26, and a 2-input AND.
27 and a 4-input AND 28, 29. The DFF 21 latches the logical level value of the input data Din at the time when the clock signal C1 is input to the input CP21 from the output Qa of the shift register 13 from the input 21D, and outputs the latched result from the output 21Q to a 4-input AND 28.
And 29. The DFF 22 is the shift register 1
The logic level value of the input data Din at the time when the clock signal C2 from the output Qb of 3 is input to the input CP22 is latched from the input 22D, and the latch result is output from the output 22Q to the 4-input AND 28 and 29. The DFF 23 is
Clock signal C3 from output Qc of shift register 13
Is latched from the input 23D to the logical level value of the input data Din at the time when is input to the input CP23, and the latched result is output from the output 23Q to the 4-input AND 28 and from the output 23 to the 4-input AND 29. Further, the DFF 24 latches the logic level value of the input data Din at the time when the clock signal C4 from the output Qd of the shift register 13 is input to the input CP24, and the latch result is output from the output 24Q to the 4-input AND 29 and output 24. 4 inputs AND28
Output to. The inverter 26 inputs the clock signal CLK0, inverts its input level, and outputs it to the 2-input AND 27. The two-input AND 27 inputs the clock signal C2 from the output of the inverter 26 and the output Qb of the shift register 13, and outputs the logical product result to the DFF 25. The DFF 25 inputs and latches the input data Din by inputting the output of the 2-input AND 27 to the input CP25, and outputs the latched result as the output data Dout. The 4-input AND 28 outputs the output 21Q of the DFF 21,
The output 22Q of the DFF 22, the output 23Q of the DFF 23, and the output 24 of the DFF 24 are logically ANDed,
The result of the logical product is output to the synchronization control circuit 30. Also,
The 4-input AND 29 is the output 21Q and DFF2 of the DFF21.
2 output 22Q, DFF 23 output 23 and DFF2
The outputs of the four outputs 24Q are logically ANDed, and the logical AND result is output to the synchronization control circuit 30.

The synchronization control circuit 30 includes DFFs 31 and 32, a set-priority flip-flop (hereinafter, simply SFF) 33, and a 2-input AN.
D34, 37, 39, shift register 35, and inverters 36, 38. The DFF 31 latches the output of the 4-input AND 28 from the input 31D by inputting the clock signal C4 from the output Qd of the shift register 13 to the input CP31, and the latched result is SF
Output to the input S of F33. The DFF 32 inputs the clock signal C4 from the output Qd of the shift register 13 to the CP
By inputting to 32, the output of the 4-input AND 29 is latched from the input 32D, and the latched result is output to 32Q.
Output to the input R of the SFF 33. SFF33 is D
When the output from the output 31Q of the FF31 is input to the input S at the high level "1", the set state is set, and the low level "0" is output from the output 33, while the output of the output 32Q of the DFF32 is input at the high level "1". When it is input to R, the reset state is set, and the output 33 outputs a high level "1". Two
The input AND 34 forms a logical product of the clock signal CLK1 and the output of the output 33 of the SFF 33, and the logical product result is obtained by the counter 14, the shift register 35, and the 2-input AN.
Output to D37. The shift register 35 inputs the clock signal CLK1 into the input 35A and outputs the clock signal CLK1.
0 is input to the input CP35 as a synchronizing signal, and is shifted by 4 clocks in terms of the clock signal CLK0 and output from the output Q'd. The inverter 36 inputs the output from the output Q′d of the shift register 35, inverts the input level, and outputs it to the 2-input AND 37. The 2-input AND37 is
The logical product of the output of the inverter 36 and the output of the 2-input AND 34, that is, the clock signal CLK1 is formed, and the logical product result is output to the inverter 38. The inverter 38 inputs the output of the 2-input AND 37, inverts the input level, and outputs it to the 2-input AND 39. 2-input AND39
Forms a logical product of the output of the inverter 38 and the clock signal C4 from the output Qd of the shift register 13, and outputs the logical product result to the input CP31 of the DFF31.

Next, the operation of the above configuration will be described with reference to FIGS. 1 and 5 (a),
This will be described with reference to (b) and (c).

First, input data Din and clock signals CLK0, CL
The conditions before and after K1 will be described with reference to FIG. 6. In each of the devices A and B provided with the clock signal generating circuit,
In synchronization with the clock signal generated by the clock signal generation circuit A1 in the device, data is transmitted from the transmitter A2 of the device A to B
The data is sent to the device, and the data is input to the device D in the device B.
The input data Din is input to the receiving unit B2 as in, and the input data Din is synchronized with the clock signal CLK0 generated by the clock signal generation circuit B1 in the device B. Note that the clock signal generation circuit A1 of the device A and the clock generation circuit B1 of the device B are independently synchronized with each other and provided with high-precision oscillators, or both are in a clock frequency synchronized relation. To do.

Under the above prerequisites, the clock signal phase variable circuit 1
In 0, the four-phase clock signal generation circuit 11 inputs the clock signal CLK0 to the input CP11, and the clock signal CLK
Generates a 4-phase clock string signal synchronized with 0 and outputs Q0
It is output from the input of the selector 12 through Q3. Here, the selector 12 is the output 14 of the counter 14.
Q0, 14Q1 are input to the inputs 12A, 12B, and one of the inputs ~ is selected based on the value and output 12
It is output from X to the input 13A of the shift register 13. For example, as shown in FIG.
Q0 is low level "0", output 14 Q1 is high level "1"
If the state is (counter value "2"), the input of the selector 12, that is, the output Q0 of the 4-phase clock signal generation circuit 11
Of Q3, the output of the output Q1 shown by hatching in the figure is selected, and the shift register 13 sequentially shifts in synchronization with the clock signal CLK0 and outputs the clock column signals C1 to C4. Next, the outputs 14Q0 and 14Q of the counter 14
When both 1s are counted up to a high level "1" (counter value "3"), the input of the selector 12, that is, the output Q of the four-phase clock signal generation circuit 11 shown by hatching in the figure.
When the output of 0 is selected and the counter value is "2", the shift register 13 outputs the clock column signals C1 to C4 in the same manner. Here, as is apparent from FIG. 5 (a), the clock train signal C1 when the counter value of the counter 14 is "2"
It can be seen that the phases of .about.C4 and the clock string signals C1 to C4 when the counter value of the counter 14 is "3" are changed. That is, every time the counter 14 counts up, the clock sequence signals C1 to C4 are changed to the clock signal CLK0.
It will be shifted by the time T of one clock in conversion. The clock signal C1 thus generated is DFF2.
1 input CP21, the clock signal C2 is the input CP22 of the DFF22, and the 2-input AND27 is the clock signal C.
3 is the input CP23 of the DFF 23, the clock signal C4 is the input CP24 of the DFF 24, and the input CP32 of the DFF 32.
And a two-input AND 39, each of which inputs the clock signals C1 to C4 whose phases are shifted by the time T each time the counter 14 counts up if the counter 14 is operating.
Is supplied.

Further, in the phase detection circuit 20 and the synchronization control circuit 30, the DFFs 21 to 24 latch the input data Din in synchronization with the clock signals C1 to C4, and the latch result is the output 21Q of the DFF 21 and the output 22 of the DFF 22.
Q, output 23 of DFF 23 and output 24 of DFF 24
4 inputs AND28 that both are high level "1"
If the detection result is detected by the DFF31 and the detection result can be latched by the DFF31, it means that the synchronous state is detected, the output 31Q of the DFF31 is input to the input S of the SFF33 at the high level "1", and the SFF33 is set. When the SFF 33 enters the set state, the output 33 of the SFF 33 becomes the low level “0”, and therefore the clock signal CLK1 is not output from the 2-input AND 34, which causes the counter 1
4 is stopped and the phases of the clock train signals C1 to C4 are fixed.

On the other hand, the output 21Q of the DFF 21 and the output 22 of the DFF 22
Q, output 23 of DFF 23 and output 24 of DFF 24
4 inputs AND29 that both Q are high level "1"
When the detection result is latched by the DFF 32 and the asynchronous state is detected, the output 32Q of the DFF 32 is input to the input R of the SFF 33 at the high level “1”, and the SFF 33 is reset. When the SFF 33 enters the reset state, the output of the output 33 of the SFF 33 becomes the high level "1", and therefore the clock signal CLK1
Is output via the 2-input AND 34, and the counter 14 starts counting operation and counts up.

The above synchronous and asynchronous states will be described with reference to FIG. 5 (a). In the state of the count value "2" in which the output of the output Q1 of the four-phase clock signal generation circuit 11 is selected, the phase of the input data Din shown in the figure is shown. If the signal is received at, the clock signal C4 causes the DFF31 to latch the phase 4
The AND condition of the input AND 28 is not satisfied, and therefore the SF
F33 cannot be set. Next, when the counter 14 counts up by the clock signal CLK1 and the count value becomes “3”, the output Q0 of the four-phase clock signal generation circuit 11 is selected, and the clock signals C1 to C4 generated as a result select the input data. When Din is latched, the AND condition of the 4-input AND 28 is satisfied in the phase that can be latched in the DFF 31 by the clock signal C4, whereby the SFF 33 is set via the DFF 31. As a result, the clock signal CLK1 becomes 2
It is not output from the input AND 34, and the operation of the counter 14 is stopped by this.
The phase of ~ C4 is fixed and the synchronization state is established. Also, D
The output data Dout output from the output Q of the FF 25 is the middle of the clock signal C2, that is, the AN of the clock signal CLK0 and the clock signal C2, as indicated by the arrow C2 'in the figure.
Output at the falling edge of D condition. This condition considers the jitter of the input data Din after the synchronization state is established.

Further, FIG. 5 (b) is a timing chart showing a state where the SFF 33 is reset. In the figure, (1) is Fig. 5 (a).
When the input data Din fluctuates more than + (1.5T-ts) from the middle of the clock signal C2 from the state of (1), the input data Din of the clock signal C2 is reproduced. If it fluctuates more than − (1.5T-th) from the middle, (3)
Shown in. Here, ts is D that latches the input data Din.
The setup time of FF21 to 24, th is DFF21
Hold time of 24. That is, the AND condition of the 4-input AND 29 is satisfied at the time when the input signal Din can be latched by the clock signal C4 due to the change of the input data Din, and the SFF 33 enters the reset state via the DFF 32 and the asynchronous state is detected.

When the synchronization state is detected, when the input data Din is received in the phase relationship shown in FIG. 5 (c) and the synchronization is established immediately after the counter 14 counts up, the phases of the clock sequence signals C1 to C4 change. , The phase is shifted and fixed by the time T from the phase where synchronization is established. Therefore, in order to avoid this state, it is necessary to prohibit the synchronization state detection immediately after the counter 14 counts up. Therefore, the shift register 35 shifts the clock signal of the counter 14, that is, the clock signal CLK1 by 4 clocks in terms of the clock signal CLK0. Then, the output Q'd of this shift register 35
AND 37 of the clock signal CLK1
Therefore, the clock signal C4 within 4 clocks immediately after the counter 14 counts up is input by 2 inputs A.
The synchronization state detection by the DFF 31 is prohibited by suppressing it by the ND 39. According to Fig. 5 (c), 2-input AND
The output of 37 suppresses the clock signal C4 indicated by diagonal lines in the figure.

As described above, in this circuit configuration, the phases of the clock sequence signals C1 to C4 for latching the input data Din are changed until the synchronization is established, and after the synchronization is established, the phases of the clock sequence signals C1 to C4 are fixed. This functions as a digital phase lock circuit. The clock signals CLK0,
The relationship between the bit rates of CLK1 and the input data Din is an example, and the present invention is not limited to this example.

As described above, according to the present invention, the phase of the clock train signal for latching the input data is changed until the synchronization is established, and if the synchronization is established, the phase of the clock train signal is changed. Since it is fixed, there is no need to provide a delay circuit for delaying the input data until the synchronization is established. Therefore, there is no need to adjust the circuit, and the time and effort can be saved, and a circuit suitable for LSI implementation can be obtained.
Further, there is an advantage that it is possible to provide a digital phase locked loop having excellent operation.

[Brief description of drawings]

1 is a circuit diagram showing an embodiment of a digital phase synchronizing circuit according to the present invention, FIG. 2 is a block diagram showing a conventional digital phase synchronizing circuit, FIG. 3 is a circuit diagram of a variable delay line and a phase detecting circuit, FIG. 4 is an explanatory diagram for explaining the phase detection and correction operation, and FIGS. 5 (a), (b) and (c) are timing charts for explaining the operation of each part of the digital phase locked loop according to the present invention. FIG. 6 is an explanatory diagram for explaining the preconditions of the input data and the clock signal. In the figure, 10 ... Clock signal phase variable circuit, 11 ... 4
Phase clock signal generator, 12 ... 4/1 selector, 1
3, 35 ... Shift register, 14 ... 2-bit counter, 20 ... Phase detection circuit 21, 22, 23, 24,
25, 31, 32 ... D-type flip-flop (DF
F), 26, 36, 38 ... Inverter, 27, 34,
37,39 …… 2 inputs AND, 28,29 …… 4 inputs A
ND, 30 ... Synchronous control circuit, 33 ... Set priority flip-flop (SFF).

Claims (1)

[Claims] 1. A digital phase synchronization circuit for inputting digital input data and outputting it as output data when phase synchronization is established, wherein a clock train signal consisting of a plurality of clock signals is repeatedly generated and according to a phase selection designation. A clock signal phase variable circuit that selects the phase of each clock column signal by the selection means, and detects that the input signal is in a high-level synchronous state over each input time point of the clock signal in the clock column signal, A phase detection circuit that detects an asynchronous state when the input data includes a low level state during the input time, and outputs output data when phase synchronization is established; and a selection when the synchronization state is detected Means for fixing the phase selection designation to the means and continuously input when the asynchronous state is detected Each clock signal is provided a synchronization control circuit for establishing phase synchronization update controlling the phase selection specified for the selected unit to correspond to the synchronization state, the digital phase locked loop, characterized in that.