JPH06164661A - Radio receiver - Google Patents

Abstract

PURPOSE:To harmonize transmission characteristics with energy consumption. CONSTITUTION:A control circuit 22 controls a switching circuit 21 based on a delay detecting signal from a delay detection circuit 12 and a quasi- synchronous detecting signal sampling value from a quasi-synchronous detection circuit 3, operates the delay detection circuit 12 and a judge circuit 13 provided with less energy consumption when the quality of a radio line is satisfactory, and operates the quasi-synchronous detection circuit 3 and an equalizer 7, which reduce signal errors although the energy consumption is more, when the quality of the radio line is degraded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used in a radio receiver for digital radio communication. INDUSTRIAL APPLICABILITY The present invention is used for a receiver of a radio signal that is digitally modulated such as amplitude / phase modulation. The present invention is suitable for use as a mobile station device of a mobile radio communication system. The present invention is intended to suppress the deterioration of transmission characteristics due to intersymbol interference and to make the power consumption economical.

[0002]

2. Description of the Related Art FIG. 4 shows a radio receiver using a conventional quasi-coherent detection circuit. FIG. 5 shows a radio receiver using a differential detection circuit according to another embodiment.

Digital QAM (Quadrature Amplitude)
As a detection circuit of a radio receiver for Modulation (Quadrature Amplitude Modulation) signals, a device having a configuration shown in FIGS. 4 and 5 is widely known as a technique for suppressing deterioration of transmission characteristics due to intersymbol interference. FIG. 4 includes a quasi-synchronous detection circuit 3 that receives a received signal as an input, and an equalizer 7 that determines a signal from an output sampling value of the quasi-synchronous detection circuit 3. On the other hand, FIG. 5 includes a differential detection circuit 12 that receives a received signal as an input, and a determination circuit 13 that determines a signal output from the differential detection circuit 12.

FIG. 6 is a diagram showing an example of a burst signal received by this receiver. As a training signal, for example, a signal of a pattern defined by each system is arranged with 10 symbols, and during the training signal period. The operation of the receiving circuit is set and the subsequent data signal is received. The data signal is composed of, for example, 56 symbols, and the duration of the burst signal is, for example, about 3.3 milliseconds.

In the detection circuit including the equalizer 7 shown in FIG.
The received signal in the intermediate frequency band given to the input terminal 1 is amplified by the linear amplifier 2 with automatic gain control (AGC),
The in-phase component and the quadrature component of the signal are extracted by the quasi-synchronous detection circuit 3, and the analog-digital conversion circuit 4 respectively
And the sampling value is obtained from 5 and stored in the memory 6
Accumulate in. The contents of the memory 6 are given to the equalizer 7 to make a signal determination.

Here, the quasi-synchronous detection circuit (reference numeral 3 in FIG. 4) is a synchronous detection circuit in which the reception local frequency is set equal to the carrier frequency on the transmission side, but is not in phase synchronization. Further, as the equalizer 7, the maximum likelihood sequence estimation (Maximum Likelihood Sequence) is performed.
nce Estimation: MLSE) is known. This equalizer calculates the likelihood corresponding to a possible signal sequence, and selects the signal sequence having the largest value in signal determination. This equalizer exponentially increases the number of all possible signal sequences when the signal sequence becomes long.Therefore, in order to reduce the number of sequences and reduce the amount of calculation, the Viterbi algorithm that performs state estimation uses a Viterbi algorithm. Shape equalizers are known.

On the other hand, the detection circuit shown in FIG.
The received signal in the intermediate frequency band is input from the limiter amplifier 1
By 1, the received signal is non-linearly amplified to a constant level. When this output is differentially detected by the differential detection circuit 12, the in-phase component and the quadrature component of the differential detection signal are obtained at this output. The decision circuit 13 makes a hard decision to obtain the in-phase component and the quadrature component of the decision signal at the output terminals 8 and 9, respectively.

[0008]

Comparing the characteristics of the above-mentioned two detection circuits, in the circuit shown in FIG. 4 including the quasi-synchronous detection circuit and the equalizer, the delay dispersion of the propagation path corresponds to the symbol synchronization T of the modulated wave. It has excellent performance with little deterioration in transmission characteristics even when it is large, but since the circuit after the sampling value is extracted is composed of a digital circuit, it has the drawback of high power consumption during operation. is there. In addition, a linear amplifier with automatic gain control also consumes a large amount of power. On the other hand, in a wireless receiver including a differential detection circuit, the differential detection circuit can be realized by a very simple analog circuit, consumes less power than an equalizer, and has a smaller circuit scale than a wireless receiver including an equalizer. Although it has the advantage of being small, when the delay dispersion of the propagation path is larger than the symbol synchronization T of the modulated wave, there is a drawback that the transmission characteristics are significantly deteriorated.

As a receiver mounted in a mobile station apparatus of the mobile radio communication system, it is extremely important that the power consumption is small, and therefore, a differential detection circuit is often used, but in a rural area, a zone radius is large and a base station is large. Since the station transmission power is set large and the delay dispersion of the propagation path becomes large, it is a big problem which detection circuit is adopted in the mobile station device. On the other hand, in recent years, digital circuits have become extremely small, and it has become possible to mount a considerably complicated decision circuit in a mobile station device.

The present invention has been made under such circumstances, and an object of the present invention is to provide a radio receiver in which transmission characteristics and power consumption are harmonized.

[0011]

The present invention comprises a first detection circuit including a differential detection circuit which receives a received signal as an input, and a determination circuit which determines a signal output from the differential detection circuit.
A quasi-synchronous detection circuit that receives the received signal as an input, and a second detection circuit that includes an equalizer that determines a signal from an output sampling value of the quasi-synchronous detection circuit, and one of the two detection circuits is provided. Means for calculating the respective evaluation values of the two detection circuits by taking in the output of the differential detection circuit and the output sampling value, and control means for controlling the selection means according to the evaluation values. Is provided with a control circuit including.

According to the present invention, the evaluation value is an intersymbol interference amount and a signal determination error for the first detection circuit, and a signal determination error for the second detection circuit. Can be configured to calculate this evaluation value for each preset switching timing.

Further, according to the present invention, the control means is configured to detect the second detection signal when the intersymbol interference amount exceeds a preset threshold value in a state where the first detection circuit is selected. It is possible to include means for selecting a circuit and controlling so as to select a detection circuit having a smaller signal determination error when the second detection circuit is selected.

Further, in addition to the second detection circuit, a digital delay detection circuit, a judgment circuit for making a signal judgment of the output of the digital delay detection circuit, the output sampling value to the equalizer and the digital delay detection circuit. A distribution circuit for distributing to the circuit, the control means, when the first detection circuit is selected, when the intersymbol interference amount exceeds a preset threshold value, the second In the state where the detection circuit is selected and the second detection circuit is selected, when it is determined that the signal determination error is small for the first detection circuit, the digital signal in the second detection circuit is selected. It is possible to include means for selecting the delay detection circuit and further controlling to select the first detection circuit at the switching timing.

[0015]

In the apparatus of the present invention, when the quality of the wireless line is good, the differential detection circuit with low power consumption is operated, and when the quality of the wireless line deteriorates, an equalizer with large power consumption but few signal errors is provided. The transmission characteristics and power consumption are harmonized by operating the detection circuit that includes them.

Instead of inputting the detection outputs of the first detection circuit and the second detection circuit to the control circuit,
The evaluation value can be calculated by taking in the output of the delay detection circuit for the first detection circuit, taking in the output sampling value of the quasi-synchronous detection circuit for the second detection circuit, and performing the respective operations.

[0017]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a wireless receiver according to an embodiment of the present invention.

In FIG. 1, the wireless receiver of this embodiment is
A first detection circuit including a limiter amplifier 11 and a delay circuit 12 as a delay detection circuit that receives a reception signal as an input, and a determination circuit 13 that determines a signal output from the delay detection circuit 12 is provided. As a quasi-synchronous detection circuit, a linear amplifier 2, a quasi-synchronous detection circuit 3, analog-digital converters 4, 5 and a memory 6, and a quasi-synchronous detection circuit 3
Of the delay detection circuit 12 and a second detection circuit including an equalizer 7 that makes a signal determination from the output sampling value of the output signal of the second detection circuit, and a selection circuit 23 as selection means for selecting one of the two detection circuits. A control circuit 22 and a switching circuit 21 are provided as a control circuit including a means for calculating an output and the output sampling value and calculating each evaluation value of the two detection circuits, and a control means for controlling the selection circuit 23 according to the evaluation value. It is characterized by having.

The evaluation value is the intersymbol interference amount and the signal determination error for the first detection circuit, and the signal determination error for the second detection circuit, and the control circuit 22 determines the evaluation value. Is configured to be calculated for each preset switching timing.

Further, the control circuit 22 selects the second detection circuit when the intersymbol interference amount exceeds a preset threshold value while the first detection circuit is selected. In the state where the second detection circuit is selected, there is included means for controlling so as to select the detection circuit with the smaller signal determination error.

The operation of the radio receiver having such a configuration will be described.

In FIG. 1, a received signal in the intermediate frequency band is input from the input terminal 1. The switching circuit 21 is controlled by the control circuit 22 described later, and inputs the received signal to the limiter amplifier 11 or the linear amplifier 2. The limiter amplifier 11 non-linearly amplifies the received signal to a constant level, and the delay detection circuit 12
Performs delay detection on the output signal of the limiter amplifier 11 and outputs the in-phase component and the quadrature component of the delay detection signal. The decision circuit 13 receives the delayed detection signal as an input, performs signal decision by hard decision, and outputs the in-phase component and the quadrature component of the first decision signal. Here, the limiter amplifier 11, the differential detection circuit 12, and the determination circuit 13 correspond to a first detection circuit.

On the other hand, the linear amplifier 2 linearly amplifies the received signal to a level suitable for detection, and the quasi-coherent detection circuit 3 quasi-coherently detects the output signal of the linear amplifier 2 and outputs its in-phase component and quadrature component. . Analog-digital converter 4,
Reference numeral 5 samples the quasi-synchronous detection signal and outputs it as a quasi-synchronous detection signal sampling value. The memory 6 temporarily holds the quasi-synchronous detection signal sampling value and outputs it to the equalizer 7. The equalizer 7 receives the quasi-synchronized detection signal sampling value as an input, performs signal determination by equalization, and outputs the in-phase component and the quadrature component of the second determination signal. Here, the linear amplification 2, the quasi-synchronous detection circuit 3, the analog / digital converters 4, 5, the memory 6 and the equalizer 7 correspond to a second detection circuit.

The control circuit 22 receives the delayed detection signal and the quasi-synchronous detection signal sampling value as input, and selects and operates the one having better transmission characteristics in the first detection circuit and the second detection circuit at each switching timing. . Then, the switching circuit 21 is controlled based on this selection. The selection circuit 23 selects the first determination signal or the second determination signal based on the selection of the control circuit 22, and outputs it as an output signal from the output terminals 8 and 9. Here, the control circuit 22 and the switching circuit 21 correspond to a control circuit, and the selection circuit 23 corresponds to a selection unit.

Next, the operation of the control circuit 22 will be described. In the following description, the modulation method is differential encoding PSK, and the signal sampling period is the symbol period T of the modulated wave. In addition, all signals are represented using a complex representation with the in-phase component in the real part and the quadrature component in the imaginary part.

When the first detection circuit is already selected and is operating, the control circuit 22 obtains the intersymbol interference amount included in the differential detection signal. This is a physical quantity representing the degree of waveform distortion due to intersymbol interference, and when this value is large, the second detection circuit has better transmission characteristics than the first detection circuit. Therefore, when the preset threshold value is exceeded, the second detection circuit is controlled to perform a switching operation at the switching timing. For example, when the switching timing is set to the burst timing, the second detection circuit is selected and operated at the next burst timing.

Next, a method of calculating the intersymbol interference amount will be described. However, the sampling value at the time t = kT (k is an integer) of the differential detection reception signal is z (k). Since the differential detection signal has passed through the limiter amplifier 11, the amplitude is constant. Assuming that the phase difference between the complex symbols at time t = kT and time (k-1) T is d (k), z (k) d * if there is no deterioration factor such as intersymbol interference and noise.
(K) is a constant real number regardless of time, and has no correlation with d (k-1). Here, * represents a complex conjugate. When waveform distortion occurs due to intersymbol interference, correlation appears in this z (k) d * (k) and d (k-1). Therefore, z (k) d
The correlation between * (k) and d (k-1) can be regarded as the intersymbol interference amount. For example, the specified signal section is d
If (k) is a training signal section with a known signal length N _T , this correlation ρ is given by the following equation.

[0028]

[Equation 1] When the second detection circuit is already selected and is operating, the control circuit 22 sets the BER (bit error ratio).
Based on the judgment formula obtained from the theoretical formula of o), the one having better BER characteristics is selected from the first detection circuit and the second detection circuit. In the following description, the equalizer 7 is a Viterbi equalizer. In the case of differential encoding QPSK modulation, this judgment formula is D = γ _E −2.0γ _D , and when the judgment formula D is negative, the first detection circuit is selected,
When it is non-negative, the second detection circuit is selected. Where γ _E ,
γ _D is the signal energy to noise power density E _b / N ₀ per bit of the equalizer 7 and the delay detection circuit 12, and considers the tracking error that cannot be eliminated as the intersymbol interference and the propagation path fluctuation as a noise component. Ask by. Here, a method for approximately obtaining γ _E and γ _D in the training signal section of the signal length N _T symbol will be described. Assuming that the power of the noise component is very small, the judgment formula D can be replaced with the following judgment formula D ′.

[0029]

[Equation 2] Here, e _E (k) is a signal determination error of the equalizer 7, which is a difference between the quasi-synchronized detection signal sampling value and its estimated value. e _D (k) is a signal determination error of the differential detection circuit 12 and is obtained from the quasi-synchronous detection signal sampling value. In addition,
This value is an error signal when signal determination is performed with reference to the carrier phase of the quasi-synchronized detection signal sampling value at time 1T past, and intersymbol interference, tracking error with respect to channel fluctuation, and noise are double estimated. The power is twice the value to be obtained.

When the determination formula D'is negative, the first detection circuit has better transmission characteristics than the second detection circuit.
The first detection circuit is controlled to perform a switching operation at the switching timing. For example, when the switching timing is set to the burst timing, the first detection circuit is selected and operated at the next burst timing. When the determination expression D'is non-negative, the second detection circuit is operated even at the next burst timing.

As described above, when the second detection circuit is already selected and operating, the control circuit 22 determines from the determination formula D'based on the quasi-synchronous detection signal sampling value from the quasi-synchronous detection circuit 3. It is possible to judge and select which of the first detection circuit and the second detection circuit has the better transmission characteristic.

FIG. 2 is a block diagram of a radio receiver according to the second embodiment of the present invention. In FIG. 2, a received signal in the intermediate frequency band is input from the input terminal 1. The switching circuit 21 is controlled by the control circuit 32 described later, and inputs the received signal to the limiter amplifier 11 or the linear amplifier 2. Limiter amplifier 1
Reference numeral 1 denotes a non-linear amplification of the received signal to a constant level, and the differential detection circuit 12 differentially detects the output signal of the limiter amplifier 11 and outputs the in-phase component and the quadrature component of the differential detection signal. The decision circuit 13 receives the delayed detection signal as an input, performs signal decision by hard decision, and outputs the in-phase component and the quadrature component of the first decision signal. On the other hand, the linear amplifier 2 linearly amplifies the received signal to a level suitable for detection, and the quasi-synchronous detection circuit 3
Quasi-coherently detects the output signal of the linear amplifier 2 and outputs its in-phase component and quadrature component. The analog-digital converters 4 and 5 sample the quasi-synchronous detection signal and output it as a quasi-synchronous detection signal sampling value. The memory 6 temporarily holds the quasi-synchronous detection signal sampling value and inputs it to the switching circuit 34. The switching circuit 34 converts the quasi-synchronous detection signal sampling value into the equalizer 7 or the digital differential detection circuit 3.
Enter in 5. The equalizer 7 receives the quasi-synchronized detection signal sampling value as an input, performs signal determination by equalization, and outputs the in-phase component and the quadrature component of the second determination signal. The digital differential detection circuit 35 and the determination circuit 36 receive the quasi-synchronous detection signal sampling value as input, perform signal determination by differential detection, and output the in-phase component and the quadrature component of the third determination signal.

The control circuit 32 receives the delay detection signal and the quasi-synchronization detection signal sampling value as input, and selects and operates one of the nonlinear receiving means and the linear receiving means, whichever has better transmission characteristics, at each switching timing. Then, the switching circuit 21 is controlled based on this selection. The selection circuit 33 selects the first determination signal, the second determination signal, or the third determination signal based on the selection of the control circuit 32, and outputs it as an output signal from the output terminals 8 and 9.

Next, the operation of the control circuit 32 will be described.

When the differential detection circuit 12 is already selected and is operating, the first detection circuit composed of the differential detection circuit 12 and the determination circuit 13 is operating. Control circuit 32
Controls the quasi-synchronous detection circuit 3 to switch at the switching timing when the intersymbol interference amount included in the differential detection signal described in the first embodiment exceeds a preset threshold value. That is, when the switching timing is set to the burst timing, the quasi-synchronous detection circuit 3 is selected and operated at the next burst timing.

When the quasi-synchronous detection circuit 3 is already selected and operated, the equalizer 7 is a Viterbi type equalizer.
The control circuit 32 selects and operates one of the equalizer 7, the digital delay detection circuit 35, and the judgment circuit 36, whichever has a better BER characteristic, based on the judgment formula D ′ described in the first embodiment. Specifically, when the judgment formula D ′ is negative, the digital delay detector 35 and the judgment circuit 36 are selected and operated. When it is non-negative, the equalizer 7 is selected, and the quasi-coherent detection circuit 3 is selected and operated even at the next burst timing.

The case where the switching timing coincides with the burst timing has been described above, but it is also possible to set the burst timing to a timing obtained by dividing the burst timing by an integer.

FIG. 3 is a BE of a radio receiver according to the second embodiment of the present invention.
It is a figure which shows a R characteristic graph.

In order to confirm the effect of the present invention, calculation simulation was performed on the second embodiment. First, the simulation conditions will be described. Transmission speed is 40 kb
/ S, modulation method is roll-off 0.5 differential encoding QPS
K. The propagation path is a two-wave Rayleigh model with delay time τ, and the ratio of signal energy to noise power density per bit E _B / N ₀ = 30 dB and maximum Doppler frequency f _D is 8
It was set to 0 Hz. The structure of the burst signal was such that a training signal of 10 symbols was followed by a data signal of 64 symbols. The equalizer is a Viterbi type equalizer, and for the channel estimation, RLS (recursive least squares) is used.
) Use an algorithm. The forgetting factor of the RLS algorithm was 0.8, and the number of states of the Viterbi algorithm was 4.

[0040]

As described above, according to the present invention, since the differential detection circuit is appropriately used depending on the propagation situation, excellent transmission characteristics can be obtained even when the delay dispersion of the propagation path is small and the fluctuation is large, and the consumption is low. There is an excellent effect that electricity can be achieved. Therefore, it is possible to realize a wireless receiver that balances transmission characteristics and power consumption.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a wireless receiver according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a wireless receiver according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a BER characteristic graph of the wireless receiver according to the second embodiment of the present invention.

FIG. 4 is a block configuration diagram of a wireless receiver using a conventional quasi-coherent detection circuit.

FIG. 5 is a block configuration diagram of a wireless receiver using another conventional differential detection circuit.

FIG. 6 is a diagram showing a burst signal received by a wireless receiver.

[Explanation of symbols]

 1 Input Terminal 2 Linear Amplifier 3 Quasi-Synchronous Detection Circuit 4, 5 Analog / Digital Converter (AD Converter) 6 Memory 7 Equalizer 8, 9 Output Terminal 11 Limiter Amplifier 12 Delay Detection Circuit 13, 36 Judgment Circuit 21, 34 Switching circuit 22, 32 Control circuit 23, 33 Selection circuit 35 Digital differential detection circuit

Claims (4)

[Claims] 1. A differential detection circuit having a received signal as an input,
A first detection circuit including a determination circuit that performs a signal determination of the output of the delay detection circuit, a quasi-synchronous detection circuit that receives the received signal as an input, and a signal determination from an output sampling value of the quasi-synchronous detection circuit. A second detection circuit including an equalizer for performing, and a selection means for selecting one of the two detection circuits, the two detection circuits for taking in the output of the differential detection circuit and the output sampling value 2. A radio receiver comprising: a control circuit including means for calculating each evaluation value of 1. and control means for controlling the selecting means according to the evaluation value. 2. The evaluation value is an intersymbol interference amount and a signal determination error for the first detection circuit, and a signal determination error for the second detection circuit, and the control circuit has the evaluation value. 2. The wireless receiver according to claim 1, wherein the wireless receiver is configured to calculate for each preset switching timing. 3. The control means selects the second detection circuit when the intersymbol interference amount exceeds a preset threshold value in a state where the first detection circuit is selected. 2. The radio receiver according to claim 1, further comprising: a control unit that controls the detection circuit having the smaller signal determination error to be selected when the second detection circuit is selected. 4. The second detection circuit further includes a digital differential detection circuit, a determination circuit for determining a signal of an output of the digital differential detection circuit, the output sampling value to the equalizer and the digital differential detection circuit. A distribution circuit for distributing to the circuit, the control means, when the first detection circuit is selected, when the intersymbol interference amount exceeds a preset threshold value, the second In the state where the detection circuit is selected and the second detection circuit is selected, when it is determined that the signal determination error is small for the first detection circuit, the digital signal in the second detection circuit is selected. 3. A means for controlling the delay detection circuit to be selected and further to select the first detection circuit at a switching timing.
The wireless receiver described.