JPH06164600A - Transmission equipment - Google Patents

Abstract

PURPOSE:To efficiently and selectively turn plural control means into an operating state through a simple configuration, and besides, to improve reliability against a fault. CONSTITUTION:When a switching request for a 0-system is supplied from the outside, the request is supplied to control parts 3,5. The 0-system control part 3 supplies command information for operation setting to a switching circuit 2 through a 0-system bus, and the 1-system control part 5 supplies the command information for non-operation setting to the switching circuit 2 through a 1- system bus. The switching circuit 2 judges on the basis of the command information supplied from the bus, and supplies a select signal R for switching and controlling the 0-system into the operating state and the 1-system into a non- operating state to the control parts 3,5, a memory part 7, and a circuit coping part 10 by a high level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission device, and in particular, a plurality of control means are redundantly provided inside the device, and these control means are selectively put into an operating state to control a line accommodation means. Regarding

[0002]

2. Description of the Related Art In recent years, high-speed digital data transmission has become possible. For example, in digital data transmission using a dedicated line, 64 kbps, 128 kbps, 256k
bps, 512 kbps, 1 Mbps, 4.5 Mbps
It is possible to transmit data by using.

In order to realize the high-speed digital transmission of the dedicated line, there is a dedicated line transmission device that accommodates a plurality of dedicated lines and sets the lines. An example of such a dedicated line transmission device can be shown in the functional block diagram shown in FIG.

In FIG. 2, the conventional dedicated line transmission device is composed of a line interface 207, a memory unit 205, and a control unit 201. And the line interface 20
Reference numeral 7 accommodates a plurality of digital transmission lines. For example, a plurality of PBXs (private branch exchanges) are connected to these lines.

The control memory 208 of the line interface 207 sets the line for each line accommodated therein.
For example, the data transmission speed of the line. This line setting is performed by a command from the CPU 202 of the control unit 201.
The line is set up via the bus.

[0006] For example, when a request for changing the transmission rate of 64 kbps to 128 kbps is sent offline from a PBX subscriber connected to the line to the station in which the transmission device is installed, a request from the outside is made according to this change request. Information is supplied to the control unit 201.

Based on this request information, the CPU 202 performs RO
Processing is performed using the program of M203, and the transmission speed is changed from 64 kbps to 128 kbps based on the above request information.
Line setting change information for changing and setting to
07 to the control memory 208. With this line setting change information, it is possible to set the line corresponding to the request from the subscriber.

Further, the state of the accommodated line and the state of the inside of the apparatus are based on the data taken in from the bus, and the memory section 20.
The memory 206 of 5 manages the status table and the line management table.

However, in such a transmission device, since many lines are accommodated and controlled, the line subscriber is greatly affected when a failure occurs. Therefore, higher reliability is required.

In order to increase the reliability of such a transmission device, the controller 2 has a relatively high possibility of failure as compared with other parts.
01 is required to be duplicated. With such a configuration, if one fails, the other is used for operation to improve the reliability of line support.

[0011]

However, when the control unit 201 is actually duplicated to improve the reliability of line correspondence, various realization problems have occurred.

For example, one of the control units 201 is selectively controlled to switch to the operating state, and the remaining control units 2 are operated.
There is a problem of how to switch control 01 to make it stand by.

Further, there is a problem such as how to perform switching control so that simultaneous control of line correspondence by both control units 201 is not performed. In other words, a control configuration that enables alternative operation control by any of the normal control units 201 is required.

In addition, there is a problem such as what kind of control configuration prevents the operation from being stopped when the control section 201 in the operating state fails.

Such a problem becomes more and more serious when the number of control units 201 redundantly provided is three or more.

In order to solve the above-mentioned problem, it is also possible to deal with it by providing a judgment algorithm and a judgment circuit for making the control of the line corresponding unit 207 of each control unit 201 alternative. Considering this, in this case, there is a possibility that the judgment algorithm and the judgment circuit of each control unit 201 may be complicated, and that the hardware scale also becomes large.

Therefore, a transmission device having a structure capable of efficiently performing the above-mentioned control with hardware having a simple structure without providing each control unit 201 with the above-mentioned complicated judgment algorithm and judgment circuit is provided. Is needed.

The present invention has been made in view of the above problems, and an object thereof is to enable a plurality of control means to be selectively put into an operating state efficiently with a simple structure, and An object of the present invention is to provide a transmission device with high reliability against failures.

[0019]

The transmission device of the present invention comprises:
In order to achieve the above object, a line accommodating means for accommodating a line and setting a line and a plurality of control means for controlling the line accommodating means via a bus and being in an alternative operating state are provided. In the transmission device for controlling the line accommodating means by any one of the control means, it is realized by the following characteristic means and configuration.

That is, the control means outputs the switching command information to the bus according to the switching request information from the outside, and either the switching command information from the bus or when the control means in the operating state becomes abnormal. When the switching command information is given, the corresponding control means is switched to be operable and the other control means are controlled to be inoperative, and an abnormality from the control means is caused. When a signal is given, this control means is switched to non-operation,
The present invention is characterized by including a switching unit that operably switches and controls any other normal control unit.

[0021]

According to the transmission device of the present invention, the control means outputs the switching command information to the bus in response to the switching request information from the outside, and when the switching command information is given to the switching means via the bus, the switching command information is sent. Based on the above, any of the corresponding control means can be operably switched and the other control means can be non-operationally switched. Can be controlled.

Therefore, a situation in which control of a plurality of control means simultaneously competes cannot occur.

Further, when one of the plurality of control means is selectively put into an operating state, and this control means outputs an abnormal signal and gives it to the switching means, the switching means causes the abnormal signal. It is possible to control the control means that has output the non-operation to switch to the non-operation, and to switch the normal control means of any of the other control means to the operational status. It is possible to continue without stopping the operation by switching to.

Therefore, even if a failure occurs during the operation of the control means as an alternative, the operation is not stopped, so that a highly reliable transmission device can be realized.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment in which the transmission device of the present invention is applied to a transmission device for a dedicated line will be described with reference to the drawings.

FIG. 1 is a functional block diagram of a transmission device for a dedicated line according to this embodiment.

In the functional block diagram of FIG. 1, this transmission device comprises a switching request generation unit 1, a switching circuit 2, a 0 system control unit 3, a 1 system control unit 5, a memory unit 7, and a line interface unit 10. Has been done.

When the switching request generating unit 1 receives a switching request (for example, a 0 system switching request or a 1 system switching request) from the outside, it supplies a switching request signal to the 0 system control unit 3 and the 1 system control unit 5. To do.

The 0-system control unit 3 is, for example, the CPU 301.
And a ROM 302 for storing a program, a RAM 303 for storing data, etc. When a switching request signal is supplied, the CPU 301 processes using the program of the ROM 302 to select the 0 system control unit 3. If it is a related switching request signal, the 0-system control unit 3 outputs switching command information (addresses and setting data for the switching circuit 2) for enabling operation to the 0-system bus.

If the switching request signal is not related to the selection of the 0-system control section 3, the information for making the 0-system control section 3 inoperative (address and setting data for the switching circuit 2) is sent to the 0-system bus. Output.

Moreover, the 0-system control section 3 outputs a CPU abnormality signal (or failure signal) GG when the CPU 301 recognizes an internal abnormality, and supplies it to the other 1-system control section 5 and the switching circuit 2.

Further, like the 0-system control unit 3, the 1-system control unit 5 has, for example, a CPU 501 and an RO for storing programs.
It is composed of an M502 and a RAM 503 for storing data. Then, when the switching request signal is supplied, the CPU of the CPU using the program of the ROM 502 or the like is used.
If it is a switching request signal related to the selection of the 1-system control unit 501, the 1-system control unit 5 is operable to set the switching command information (address and setting data for the switching circuit 2) for the 1-system bus. Output.

If the switching request signal does not relate to the selection of the 1-system control unit 5, the information (address and setting data for the switching circuit 2) for deactivating the 1-system control unit 5 is sent to the 1-system bus. Output.

In addition, when the CPU 501 of the 1-system control unit 5 recognizes an internal abnormality, a CPU abnormality signal (or failure signal) is generated.
HH is supplied to the 0-system control unit 3 and the switching circuit 2.

Then, the switching circuit 2 outputs the switching command information (address and setting data for the switching circuit 2) for operational setting, which is supplied from the 0 system control section 3 via the 0 system bus.
The non-operation information supplied from the system control unit 5 via the 1-system bus is taken in, the 0-system control unit 3 is made operable, and the selector (SEL) 8 of the memory unit 7 is selected to the 0-system. The selector (SEL) of the line interface 10 is selected to the 0 system, and the selection signal R (0 system operation: high level, logic 1) for switching the 1 system control unit 5 to the non-operation control is output,
Supply to each part.

Further, the switching circuit 2 is controlled by the 1-system control units 5 to 1
Switching command information (address and setting data for the switching circuit 2) for operational setting supplied via the system bus and information for non-operation supplied from the system 0 control unit 3 via the system 0 bus are taken in. 1 system controller 3 is made operational,
Select the selector (SEL) 8 of the memory unit 7 to the 1 system,
Outputs a selection signal R (1 system operation: low level, logic 0) for controlling the selector (SEL) of the line corresponding unit 10 to 1 system and switching control of the 0 system control unit 3 to non-operation, and supplies it to each unit. To do.

Further, when the failure signal (CPU abnormal signal) GG is supplied from the 0-system control section 3, the switching circuit 2 makes the 0-system inoperative and the 1-system operative control signal R.
(1 system operation: low level, logic 0) is output and supplied to each unit.

When the failure signal (CPU abnormality signal) HH is supplied from the 1-system control section 5, the switching circuit 2 makes the 1-system inoperative and the 0-system operable signal R.
(0 system operation: high level, logic 1) is output and supplied to each part.

In the functional block diagram of FIG. 1, the common memory 7 of the memory unit 7 manages the line status and the internal status of the device with a status table and a management table as in the conventional case. It is managed by the data from the bus or 1-system bus.

The control memory 12 also sets the line of the dedicated line accommodated in the conventional manner. This setting is performed from the 0 system controller 3 or the 1 system controller 5 via the 0 system bus or the 1 system bus.

FIG. 3 is a functional block diagram of the switching circuit 2 of this embodiment.

In the functional block diagram of FIG. 3, the switching circuit 2 mainly includes a 0-system bus interface section 21,
1-system bus interface section 22 and switching signal generating section 23
And a state holding unit 24 and a selection signal output unit 25.

In addition, the 0-system bus interface unit 2
1 is composed of D flip-flops 31 and 32 and an address decoder 33. With such a configuration, the 0-system CPU abnormal signal P * from the 0-system control unit 3 (where * represents a negative logic signal, active indicates a low level, and inactive indicates a high level) and the 0 system bus. 0 system data bus signals C and D (this signal C is bit 1
And the signal D is bit 0 data. )
And a 0-system address signal and a 0-system control (read / write control) bus signal A, and outputs 0 to the switching signal generator 23.
The system signals I and J are formed and supplied.

Further, the address decoder 33 determines whether or not the address supplied from the bus is the address for the switching circuit 2 and determines that the address is for the switching circuit 2 (this state is determined to be valid and valid). The chip select signal B (or 1 clock pulse)
It is supplied to the clock CK input of the flip-flops 31 and 32.

The 1-system bus interface section 22 is also provided.
Also comprises D flip-flops 34, 35 and an address decoder 36. With such a configuration,
1-system CPU abnormal signal Q * from the 1-system control unit 5 (this * represents a negative logic signal, active represents a low level, inactive represents a high level), and 1 from the 1-system bus
System data bus signals G and H (the signal G is data of bit 1 and the signal H is data of bit 0),
1-system address signal and 1-system control (read / write control)
The bus signal E is taken in, and the 1-system signals K and L are formed and supplied to the next switching signal generator 23.

Further, the address decoder 36 judges whether the address supplied from the bus is the address for the switching circuit 2 and judges that it is the address for this switching circuit 2 (this state is judged as Valid and valid). ), The chip select signal (or one clock pulse) is set to D
It is supplied to the clock CK input of the flip-flops 34 and 35.

Furthermore, the switching signal generator 23 is
Circuits 41 and 44, AND circuits 42 and 46, and NAND
It is composed of circuits 43 and 45. With such a configuration, the 0-system signal from the 0-system bus interface unit 21 and the 1-system signal from the 1-system bus interface unit 22 are taken in, and the 0-system switching signal and the 1-system switching signal to the next state holding unit 24 are acquired. Signals are generated and supplied.

Next, the state holding unit 24 operates the NAND circuit 5
It is composed of a set / reset (SR) flip-flop 54 composed of 1 and 42, and a NOT circuit 53. With such a configuration, the 0-system switching signal and the 1-system switching signal from the switching signal generating unit 23 are fetched and the selection signal R is formed and supplied to the final stage selection signal output unit 25.

The final stage selection signal output section 25
Is composed of, for example, buffer circuits 54a to 54n. With such a configuration, the selection signal from the state holding unit 24 is fetched and controlled by the selection signal R 0
System control unit 3, system 1 control unit 5, selector (SEL) 8 of memory unit 7, and selector (SEL) of line interface unit 10
11 and distribute and supply.

That is, the 0-system is selectively controlled by the selection signal R being logic 1 (high level, H level). Further, the 1 system is selectively controlled by the logic 0 (low level, L level).

Next, the operation of the functional block diagram of the switching circuit 2 shown in FIG. 3 will be described with reference to the operation timing chart of FIG.

FIG. 4 is an operation timing chart of the switching circuit. Then, after the power is turned on (0 system selection control at the time of operation) in this operation tine MIG chart, a 1 system selection request is externally supplied to the switching request generation unit 1 to perform 1 system selection control, and then switching is performed. The operation when the request for the 0-system selection is supplied to the request generation unit 1 will be described.

(1) Operation at power-on to this transmission device At power-on, when the power-on reset signal O * (this * represents negative logic) is supplied at a low level at the timing of O1 *, the NAND circuit is supplied. 43 and the AND circuit 46. Then, the NAND circuit 43 sets the 0-system switching signal M to a high level and supplies it to the set input of the set / reset flip-flop 54. At the same time, AND circuit 46
Supplies a low level output to the reset input of the set / reset flip-flop 54. With such a high level set input and a low level reset input,
The output of the set / reset flip-flop 54 is set to low level, and this low level is supplied to the inverter 53. The level of the signal is inverted by the inverter 53 and output as a high level selection signal R.

In this way, when the power is turned on (when the power is turned on), the 0-system control unit 3, the 0-system bus B, and the 0-system selector (SEL) control the selection by the high-level selection signal R. To be done.

In order to set the 0-system bus interface section 21 and the switching signal generating section 23 of the switching circuit 2 after the power-on reset to 0-system selection, the following operation is performed.

That is, when a valid address is supplied to the switching circuit 2 at a certain A1 timing after the 0 system is selected by the power-on reset, the 0 system data bus signal C1 (high level) and D1 (low level). And
The chip select signal B1 is latched at the rising timing of the chip select signal B1 to output the output I1 (high level) and J1 (low level).

This 0-system signal I1 (high level), J1
By (low level), the 0-system switching signal M1 becomes high level, and the 1-system switching signal also becomes high level, so that the 0-system selection control can be continued without affecting the set / reset flip-flop 54.

(2) When a switching request from the 0 system to the 1 system occurs
Operation An operation of the switching circuit 2 when a switching request from the 0-system to the 1-system is supplied from the switching request generation unit 1 following the operation of the above (1) will be described.

When a request for switching to the 1-system is generated at a certain timing A2, the address decoder 33 determines whether or not the address is a valid address (Valid), and if it is valid, outputs a chip select signal. At the rising timing B2 of the signal, the 0-system data bus signal C2 (low level) and D2 (low level) are latched by the D flip-flops 31 and 32, the latch output signal I2 is output at low level, and J2 is also at low level. To output.

Even in this state, the latch output signal I2
Since the 0-system switching signal M2 (high level) and the 1-system switching signal N2 (high level) depend on (low level) and J2 (low level), there is no change from the 0-system selection state.

However, next, at the timing of E1, 1
A switching request is issued from the system control unit 5 to the switching circuit 2,
Address decoder 36 validates the address (Valid)
Then, the chip select signal F is output.
This chip select signal rise timing F1
Then, the 1-system data bus signal G1 (low level) and H1
(High level) is latched and output by the D flip-flops 34 and 35, and the latch output signals K1 (low level) and L1 are output.
(High level) and are output.

The switching signal generator 23 outputs a 0-system switching signal M3 (low level) and a 1-system switching signal (high level) by the latch output signals K1 (low level) and L1 (high level).

This 0-system switching signal M3 (low level) and 1
The system reset signal (high level) changes the state of the set / reset flip-flop 54 to make the output level high level, and the inverter 53 outputs the low level selection signal R by this high level.

Therefore, the 1-system selection control is performed by the low-level selection signal R.

Further, after the selection and setting to the 1st system, 1
When the system data bus signals G2 (low level) and H2 (low level) are supplied to valid (Valid), latch output is performed at the rising timing F2 of the chip select signal F, and the latch output signal K2 (low level) and L2 are output.
(Low level) is output.

By the latch output signals K2 (low level) and L2 (low level), the switching signal generator 23 outputs a high level as the 0-system switching signal M4 and a high level as the 1-system switching signal N4.

In this way, even if the 0-system switching signal M4 (high level) and the 1-system switching signal N4 (high level) are output, the state of the set / reset flip-flop 54 does not change, and the low-level selection signal. By R, the 1-system selection control is continued.

When the 1-system data bus signals G3 (high level) and H3 (low level) are supplied during the 1-system selection control, latch output is performed at the rising timing F3 of the chip select signal F, Latch output signal K3
(High level) and L3 (Low level) are output.

This latch output signal K3 (high level)
And L3 (low level), the 0-system switching signal M is at high level and the 1-system switching signal N is also at high level. Therefore, the set / reset flip-flop 54
Does not change, and the low-level selection signal R
1-system selection control is performed.

When the 1-system data bus signals G4 (low level) and H3 (low level) are supplied during the 1-system selection control, latch output is performed at the rising timing F3 of the chip select signal F and the latch Output signal K4
(Low level) and L4 (low level) are output.

This latch output signal K4 (low level)
And L4 (low level), the 0-system switching signal M is at the high level and the 1-system switching signal N is also at the high level, so the set / reset flip-flop 54
Does not change, and the low-level selection signal R
1-system selection control is performed.

(3) When a switching request from the 1-system to the 0-system occurs
Operation An operation of the switching circuit 2 in the case where a switching request from the switching request generating unit 1 to the switching from the 1-system to the 0-system is supplied following the operation of the above (2) will be described.

When a switching request from the 1st system to the 0th system is generated at a certain timing of A3 and E3, the address decoder 33 judges whether or not the address is a valid address, and if it is valid, the address at that time is determined. 0-system data bus signal C
3 (low level) and D3 (high level) are latched and output by the D flip-flops 31 and 32 at the rising timing B3. Then, the latch output signals I3 (low level) and J3 (high level) are output.

By the latch output signals I3 (low level) and J3 (high level) and the latch output signals K4 (low level) and L4 (low level), the switching signal generator 23 outputs the 0 system switching signal M5 (high level). The 1-system switching signal N4 (low level) is output.

This 0-system switching signal M5 (high level) and 1
The system switching signal N4 (low level) is supplied to the set / reset flip-flop 54 and outputs a low level as an output signal.
The level is inverted and becomes high level by.

This high level signal is output as the selection signal R2. That is, 0-system selection control is performed by the high-level selection signal R.

The 0-system selection control operation of the switching circuit 2 at the time of turning on the power and the switching operation by the switching request generation unit 1 to the 1-system switching request or the 0-system switching request have been described above.

Next, the switching operation when the 0-system control section 3 or the 1-system control section 5 fails during operation will be described with reference to the operation timing chart of FIG.

(4) Switching to the 1st system due to the failure of the 0th system control unit 3
After the 0-system is selectively controlled by the switching operation power-on reset operation, the 0-system control unit 3 causes the failure signal GG at a certain timing.
Is output and supplied to the switching circuit 2 and the 1-system control unit 5.

The fault signal GG from the 0-system control unit 3 is supplied to the 0-system bus interface unit 21 of the switching circuit 2 as a 0-system CPU abnormal signal P * (low level) at timing P1 (low level). . This CPU abnormality signal P1 (low level) clears the D flip-flops 31 and 32, and the latch output signals I and J output low level.

Further, the 1-system control unit 5 also recognizes the failure of the 0-system control unit 3 at a certain timing E10. Then, the 1-system control unit 5 supplies an address and data to the switching circuit 2. Then, when it is determined that the supplied address is a valid address (Valid), the address decoder 36 of the switching circuit 2 outputs the chip select signal F. At the rising timing F10 of the chip select signal F, the 1-system data bus signal G10 (low level) and H10 (high level) are latched by the D flip-flops 34 and 35, and latch output signals K10 (low level) and L10 are latched.
(High level) and are output.

The 1-system latch output signals K10 (low level) and L10 (high level), and the 0-system latch output signal I
(Low level) and J (low level), the switching signal generator 23 sets the 0-system switching signal M10 (low level) and 1
The system switching signal N10 (high level) is output.

The 0-system switching signal M10 (low level) and the 1-system switching signal N10 (high level) change the state of the set / reset flip-flop 54 of the state holding section 24 to output a high level signal. The high level signal is level-inverted by the inverter 53 and the low level selection signal R5 is output.

Therefore, the failure signal (C
When the 1-system control unit 5 recognizes the failure of the 0-system control unit 3 by the PU abnormal signal) GG, the switching circuit 2 is caused to output the low-level selection signal R5, and the selection signal R5 controls the selection to the 1-system. Is done.

(5) Due to the failure of the 1-system control unit 5,
Switching operation Next, during operation using the 1-system control unit 5, a failure signal (CP
The switching operation when the U abnormality signal) HH is output and supplied to the 0-system control unit 3 will be described.

When the failure signal (CPU abnormality signal) HH of the 1-system control section 5 is output, it is supplied to the 1-system bus interface section 22 of the switching circuit 2 as the 1-system CPU abnormality signal Q. When this timing is Q1 (low level), the D flip-flops 34 and 35 are cleared by this Q1 (low level), and the 1-system latch output signal K1
1 and L12 are output at low level.

On the other hand, the 0-system control unit 3 which receives the failure signal (CPU abnormal signal) HH of the 1-system control unit 5 at a certain timing A10 starts the 0-system operation, so that the 0-system bus interface unit of the switching circuit 2 is started. Valid for 21 (Valid)
A 0-system address signal and 0-system data bus signals C5 (low level) and D5 (high level) are supplied.

The address decoder 3 of the switching circuit 2
3 recognizes the address from the 0-system control unit 3 and outputs a chip select signal B when judging that the address is valid. Then, the rising timing B10 of the chip select signal B
Then, the D flip-flops 31 and 32 latch and output the 0-system data bus signals C5 (low level) and D5 (high level), and the 0-system latch output signal I11 (low level) and J1.
0 (high level) is output.

The 0-system latch output signals I11 (low level) and J10 (high level), and the 1-system latch output signal K
A 0-system switching signal M12 (high level) and a 1-system switching signal (low level) are output depending on (low level) and L (low level).

The 0-system switching signal M12 (high level) and the 1-system switching signal N11 (low level) change the output of the set / reset flip-flop 54 of the state holding section 24 to the low level, and this level signal is output from the inverter 53. The level is inverted by and the high level selection signal R6 is output.

Therefore, the failure signal (C
When the 0-system control unit 3 recognizes the failure of the 1-system control unit 5 by the PU abnormal signal) HH, it causes the switching circuit 2 to output the high-level selection signal R6, and the selection signal R6 selects the 0-system. Control is performed.

From the above (1) to (5), the operation of the switching circuit 2 when the switching request occurs and when there is a failure can be explained.

According to the above-described embodiment, the external switching of 0 by the control of the single switching circuit 2 provided in the transmission device.
When a system operation switching request is supplied, the requested 0 system can be controlled to operate and the 1 system can be switched to non-operation. In addition, even if the 1 system operation request is supplied, it is inconsistent. It is possible to enable the operation in an alternative manner.

Moreover, when the 0-system control unit 3 is abnormal, the 0-system control unit 3 can be switched to non-operation and the 1-system control unit 5 can be switched to be operational. Further, when the 1-system control unit 5 is abnormal, the 1-system control unit 5 can be switched to non-operation and the 0-system control unit 3 can be switched to be operational. In addition, when power is supplied to this transmission device, the 0-system control unit 3 is operably switched and controlled to
The system control unit 5 can be controlled to switch to non-operation.

Therefore, even if a request is given from the outside or the control unit is broken, the alternative operation can be efficiently performed without contradiction and can be realized with a simple structure.

In the above embodiment, the case where the present invention is applied to the dedicated line transmission device has been described as an example, but the present invention is not limited to the transmission device having the configuration shown in FIG. Further, the functional block diagram of the switching circuit 2 in FIG. 3 is not limited to this configuration. For example, it can be realized by using another logic circuit or the like.

Further, for example, when the control unit has a triple or more configuration, it can be realized by changing the configuration of the switching circuit 2 in FIG. 3 so as to be compatible with the triple redundancy or more. In other words, an interface unit that fetches information (address and setting data) and an abnormal signal from each control unit from a bus of three or more and latches them out, and one normal control unit from the latch output signal of the 3 system It can also be realized by being configured by a switching signal generating unit that outputs a selection signal for switching control so that it can be operated and switching control other control units so that it is not operating.

[0098]

As described above, according to the present invention, the control means outputs the switching command information to the bus in response to the switching request information from the outside, and the switching means is provided, so that the configuration is simple and efficient. It is possible to realize a transmission device in which a plurality of control means can be selectively put into an operating state and which is highly reliable against failures.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a transmission device according to an embodiment of the present invention.

FIG. 2 is a functional block diagram of a transmission device according to a conventional example.

FIG. 3 is a functional block diagram of a switching circuit according to an embodiment.

FIG. 4 is an operation timing chart (No. 1) of the switching circuit according to the embodiment.

FIG. 5 is an operation timing chart (No. 2) of the switching circuit according to the embodiment.

[Explanation of symbols]

1 ... Switching request generating unit, 2 ... Switching circuit, 3, 5 ... Control unit,
10 ... Line corresponding part.

Claims (1)

[Claims] 1. A line accommodating means for accommodating a line to set a line, and a plurality of control means for controlling the line accommodating means via a bus and selectively operating. In the transmission device for controlling the line accommodation means by the control means, the control means outputs the switching command information to the bus according to the switching request information from the outside, and the switching command information from the bus or the control means in the operating state is used. When an abnormality occurs, the control means is switched to one of the normal control means, and when the switching command information is given, the corresponding control means is switched to be operable and the other control means are made inoperative. When the switching control is performed and an abnormal signal is given from the control means, the control means is controlled to switch to non-operation, and any other normal control means is switched to operability. Transmission devices.