JPH06164542A - Spread spectrum signal demodulation circuit - Google Patents

Abstract

PURPOSE:To obtain a spread spectrum signal demodulation circuit where malfunction due to noises is prevented when the synchronism of codes is established. CONSTITUTION:A code generator 33 and a switch 34 generate a first code, a second code whose phase is advanced compared to the first code, a third code whose phase is delayed compared to the first code and a fourth code whose phase is sequentially changed. The second code, the third code and an input signal are multiplied in a second multiplier 24. The phase state of the first code and a transmission side code is controlled based on the multiplied result, and it is judged whether the current phase of the first code is appropriate or not based on the multiplied result of the fourth code and the input signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum signal demodulation circuit.

[0002]

2. Description of the Related Art Conventionally, a carrier signal having a spectrum width sufficiently wider than that of an information signal and modulated by, for example, a binary pseudo noise code (PN code) is transmitted, and the receiving side uses it on the transmitting side. The so-called spread spectrum communication in which the original information signal is demodulated by multiplying the received signal by the same code as the PN code is well known (for example, Electronic Science 1).
See the November 1978 issue).

In this type of spread spectrum communication, since the information signal is modulated by the PN code having a wide spectrum width as described above, in order to accurately demodulate the information signal, the PN code to be multiplied on the receiving side is transmitted. It must first be synchronized with the code on the side and then kept synchronized. A method using a sliding correlator is known as a method for catching the synchronization, and a Taudiza method is known as a method for tracking the synchronization. This method will be described with reference to FIG.

In FIG. 7, 1 is an input terminal to which a received spread spectrum signal is supplied, 2 is a despreader, which receives a despread code from a code generator 3 and a received signal from an input terminal 1 The spread spectrum is used to despread the received signal spectrum. 4 is a bandpass filter for limiting the band of the output from the despreader 2, 5 is an output terminal, 6 is a first switch for selecting the output of the voltage controlled oscillator (VCO) 7 and the output of the phase modulator 8, and 9 is Oscillator for outputting low frequency signal, 10
Is a second switch for switching the output of the low-pass filter 11 and the DC power supply voltage, 12 is a multiplier for multiplying the output of the band-pass filter 4 by the output of the oscillator, and 14 is a synchronization detector for detecting the phase synchronization of the code.

Next, the operation will be described.

When the demodulation operation starts, the second switch 10
Switches to the DC power supply voltage 13 side, and the VCO 7 oscillates at a constant frequency. The DC power supply is set to a value in which the oscillation frequency of the VCO is slightly polygonal than the clock frequency of the transmitter code. The first switch 6 is VC
Connected to the O side, the code generator 3 generates a code by using the output of this VCO as a clock. This code is VCO7
Since the oscillation frequency of is higher than the clock frequency of the code on the transmission side, the phase shifts with respect to the code on the transmission side. By the way, in spread spectrum communication, it is known that a signal is generated at the output side of the despreader 2 when the receiving side code is synchronized with the transmitting side code. Therefore,
The output of the despreader 2 is band-limited by the bandpass filter 4 and then supplied to the synchronization detector 14, whereby the establishment of code synchronization can be detected.

When it is detected that the synchronization is established in this way, the control signal from the synchronization detector 14 causes the first switch 6 to be on the phase modulator 8 side and the second switch 10 to be the low-pass filter. It is switched to the 11 side. Bandpass filter 4
Is multiplied by the output of the oscillator 9 and passed through the low pass filter 11 to be converted into a DC voltage. This voltage is applied to the VCO through the second switch 10.
7, the VCO 7 changes the oscillation frequency according to the change in the voltage. Further, the phase of the output of the VCO 7 is modulated by the phase modulator 8 based on the output of the oscillator 9. For example, when the oscillator output is at H level, the phase is advanced, and when it is at L level, the phase is delayed. The output of the phase modulator 8 is supplied to the code generator 3 through the first switch 6, and the generated code shifts back and forth based on the output of the phase modulator 8. The signal multiplied by this code by the despreader 2 by the despreader 2 and passed through the bandpass filter 4 changes in accordance with the code phase shift. This output is multiplied by the output of the oscillator and converted into a DC voltage through the low-pass filter 11 to change in the same manner. Therefore, the oscillation frequency of the VCO is controlled by this change to track the synchronization state.

[0008]

In the above-mentioned method, since the output of the bandpass filter supplied to the synchronization detector exceeds the predetermined level, the synchronization signal is transferred to the synchronization maintaining state. When noise is superposed, the synchronization detector operates in response to the noise component.

[0009]

In view of the above points, the present invention is used in the transmitting side according to the output signal from the oscillating means capable of controlling the frequency or phase of the output signal. In the code generating means for outputting a despreading code which is the same as or has a large correlation with the spreading code,
A code, a second code having a certain amount of advanced phase with respect to the first code, and a third code having a certain amount of delayed phase with respect to the first code,
A despreading code generating means for deriving a fourth code whose phase sequentially changes with respect to the first code, a first multiplying means for multiplying the first code by an input signal, and an output terminal of the first multiplying means. First filter means connected to the second code means, second multiplying means for multiplying the second code, the third code, the fourth code and the input signal;
Second filter means connected to the output terminal of the second multiplying means, detecting means for detecting an output signal of the second filter means, the second code and the third code in the input signal and the second multiplying means. The output signal of the second filter means at the time of multiplication is detected by the detecting means, and the phase synchronization maintaining means for maintaining the synchronization state by changing the output signal of the oscillating means is multiplied by the fourth code and the input signal. The phase condition that maximizes the correlation value with the transmission side code is detected by the detection signal of the detecting means at that time, and it is determined whether the phase condition is the same as the current first code phase condition. And a phase setting unit for setting the detected phase to the detected phase state.

[0010]

According to the present invention, information is reproduced by despreading the input signal by multiplying the first code and the input signal, and at the same time, the second code, the third code, the fourth code and the input signal are combined. Multiplication is performed, and a control signal for phase control of the first code is obtained based on the multiplication result. Further, it is determined whether or not the current phase state of the first code is appropriate based on the multiplication result of the second code, the third code and the input signal.

[0011]

1 is a diagram showing an embodiment of a spread spectrum signal demodulation circuit according to the present invention. In FIG. 1, 2
0 is an input terminal to which a spread spectrum signal is input, 21
Is a first multiplier that multiplies the first code by the input signal from the input terminal 20, 22 is a first filter that band-limits the output signal of the first multiplier 21, and 23 is an output signal of the first filter 22. An output terminal for outputting as an information signal, a second code having a phase advanced by a certain amount with respect to the first code, a third code having a phase delayed by a certain amount, and a phase sequentially changing with respect to the first code. A second multiplier for multiplying by 4 codes, 25 a second filter for band limiting the output signal of the second multiplier, 26
Is a correlator that detects the correlation of the output signal of the second filter 25, 17 and 18 are first and second holding circuits that hold the correlation output of the correlators, and 29 is a correlator 26 and a first holding circuit 27 or A first comparator that compares the correlation values of the second holding circuit 28, 30 is a first switch that switches the output signal of the first comparator 29, 31 is a control circuit that controls the switching of various switches, and 32, 33, and 34 are A constant voltage source, 35 is a second switch for switching the outputs of the constant voltage sources 32, 33 and 34, 36 is a voltage controlled oscillator (VCO) whose output frequency changes according to the signal output from the second switch 35, and 37 is a VCO 36. A counter for counting the output signal of the counter for each cycle of the code, 38 is a third holding circuit for holding the count value of the counter 37, 39 and 40 are third counter circuits according to the control signal from the control circuit 31 Fourth and fifth holding circuit for holding a value lifting circuit 38 holds, the third holding circuit 3 is 41
8 is a second comparator for comparing the count values held by the fourth holding circuit 39, 42 is a third switch for switching the output signals of the counter 37, the fourth holding circuit 39, and the fifth holding circuit 40, and 43 is a This is a code generator that generates a code that is the same as or has a large correlation with the spreading code used on the transmission side by using the output signal of the VCO 36 as a clock, and includes one or more shift registers that shift the generated code in time. Reference numeral 44 is a switch for switching the extraction port of the generated code of the code generator 43. Reference numeral 45 is a delay circuit that delays the code output from the switch 44 by 1/2 chip, and 46 is a fourth switch that switches the code output from the switch 44 and the delay circuit 45.

Next, the operation will be described.

The despreading operation is divided into a period for first searching for phase synchronization of codes between transmission and reception and a period for thereafter maintaining synchronization. When the phase synchronization search is started, the connection of the first switch 30, the second switch 35, the third switch 42, and the fourth switch 46 is switched by the control signal of the control circuit 31, as shown in FIG. In addition, the first holding circuit 2
7 and the contents of the third holding circuit 38 are set to 0. The output voltage of the constant voltage source 32 causes the VCO 36 to start oscillating. The output voltage of the constant voltage source 32 is set so that the oscillation frequency of the VCO 36 is equal to the frequency of the oscillator used in the code generator on the transmission side. The code generator 43 generates a code by the output frequency of the VCO 36, and the counter 37 increments the count for each cycle of the code generated by the code generator. The switch 44 is connected according to the count output of the counter 37, and the output code of the code generator 43 is multiplied by the input signal in the second multiplier 24. The multiplied signal is band-limited by the filter 25, and the correlator 26 obtains the correlation between the transmission and reception codes. The correlation output of the correlator 26 is compared with the correlation value held by the first holding circuit 27 in the first comparator 29.
In this case, since the correlation value of the correlator 26 is larger, the correlation value of the correlator 26 is stored in the first holding circuit 27 and the count value of the counter 37 is stored in the third holding circuit 38 by the output signal of the first comparator 29. Retained. After this, counter 3
7 is incremented and the switch 44 is switched to change the code outlet. That is, the phase of the code is changed. Similarly, the correlation output of the correlator 26 is compared with the correlation value of the first holding circuit 27. If the correlation value of the correlator 26 is large, the correlation value of the correlator 26 is sent to the third holding circuit. The count value of the counter 37 is held. By repeating this operation for a predetermined period, the third holding circuit holds the phase state in which the code correlation between transmission and reception is maximized. Thereafter, as shown in FIG. 3, the control circuit 31 detects the end of the phase search period by the count output of the counter 37 and supplies a control signal to the fourth holding circuit 39 and the fifth holding circuit 40. In response to this control signal, the fourth holding circuit 39 holds the count value held in the third holding circuit 38, and the fifth holding circuit 40.
Holds the value obtained by incrementing the count value of the third holding circuit 38. The value held in the fourth holding circuit 39 is output to the switch 44, the switch 44 connects the switch corresponding to the value, and sends the code synchronized with the transmission side code to the first multiplier 21. The output of this first multiplier is the first filter 1
The band is limited by 2 and the original information signal is reproduced and output from the output terminal.

The synchronization maintaining operation is performed with the synchronization maintaining control and the optimum phase search control of the current phase as one cycle. First, as shown in FIG. 5, the synchronization maintaining control is performed by the control circuit 31.
The first switch 30 by the control signal from the first comparator 2
The output of 9 is switched to the side where it is input to the control circuit 31, and the second switch 35 and the third switch 42 are switched according to the output from the counter 37 to the control circuit 31.
Further, the fourth switch 46 is switched to the delay circuit 45 side. First, the third switch is connected to the fifth holding circuit 40 side, and the switch 44 changes the code generated by the code generator 43 to the first code.
The delay circuit 45 is advanced by advancing the phase by one chip as compared with the code.
Output to. Since the delay circuit 45 delays the code by 1/2 chip, as a result, the second multiplier 24 receives the first
A code with a 1/2 chip phase advanced from the code supplied to the multiplier is input. The second multiplier 24 multiplies the input signal from the input terminal 20 by this code, and the output of this multiplication is band-limited by the second filter 25, and then the correlation is obtained by the correlator 26. The second holding circuit 28 holds this correlation output by the control signal from the control circuit 31. The control circuit 31 switches the third switch 42 to the fourth holding circuit 39 side by the next count output of the counter 37. The output of the fourth holding circuit switches the switch 44 and outputs it to the delay circuit 45 with the generated code phase of the code generator 43 being the same code as the first code. As a result, the second multiplier 24
A code that is delayed by 1/2 chip compared to the phase of the first code is input to. Similarly, the correlation is obtained by the correlator 26 and compared with the correlation value held in the second holding circuit 28 by the first comparator. The comparison result is input to the control circuit 31 through the first switch 30. In response to this, the control circuit 31 switches the second switch to turn on the VCO3.
6 controls the oscillation frequency. When the correlation value when the 1/2 chip phase is advanced is large, the constant voltage source 33 is connected to increase the oscillation frequency of the VCO 36, and the code generated by the code generator 43 is advanced from the present. On the contrary, when the correlation value is large when the 1/2 chip phase is delayed, the low voltage source 34 is connected to lower the oscillation frequency of the VCO 36 to delay the phase of the code.

On the other hand, in the optimum phase search, as shown in FIG. 6, the first switch 3 is controlled by the control signal from the control circuit 21.
0 indicates that the output of the first comparator 29 is the first holding circuit 27 and the third holding circuit 27.
On the side of the holding circuit 38, the second switch is connected to the constant voltage source 33 or 34 by the above-mentioned synchronization maintaining control,
The third switch 42 is switched to the output side of the counter 37. The fourth switch 46 is connected to the switch 44 side. The operation is the same as the initial phase search operation. The switch 44 is switched by the count output of the counter 37, and the phase of the code extracted from the code generator 43 is sequentially changed. The correlation at each phase is obtained by the correlator 26 over a certain period, and the first holding circuit 27 and the first comparator 29 are used.
The code phase that maximizes the correlation value is detected by. The phase at the time of maximum correlation is held as a count value in the third holding circuit 38, and this value is the fourth phase which is the current phase state.
The count value held in the holding circuit and the second comparator 41
Compare by. As a result, the correctness of the current phase state is confirmed, and if it is correct, the above operation is continued, and if it is not correct, the count value held by the third holding circuit is set according to the control signal from the control circuit 31. Fourth holding circuit 3
9. The fifth holding circuit 40 is held again, and the above control is repeated.

[0016]

According to the present invention, phase synchronization between transmission and reception can be surely achieved, and it is also determined whether or not the current code phase is optimum, so that noise may be present on the transmission line during initial synchronization. Even if it occurs, the code phase can be accurately synchronized.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram for explaining a phase synchronization search.

FIG. 3 is a diagram showing a phase search end detection unit.

FIG. 4 is a diagram illustrating a procedure of a synchronization maintaining operation.

FIG. 5 is a diagram for explaining a phase synchronization maintaining operation.

FIG. 6 is a diagram for explaining an optimum phase search operation.

FIG. 7 is a diagram showing a conventional example.

[Explanation of symbols]

 21 1st multiplier 24 2nd multiplier 26 Correlator 27 1st holding circuit 28 2nd holding circuit 29 1st comparator 31 Control circuit 38 3rd holding circuit

Claims (2)

[Claims] 1. An oscillating means capable of controlling a frequency or a phase of an output signal and a despreading code which is the same as or has a large correlation with a spreading code used on a transmitting side according to an output signal from the oscillating means. In the code generating means for outputting a code, for the first code, the second code whose phase is advanced by a certain amount with respect to this first code, and the third code and the first code which are delayed by a certain amount of phase with respect to the first code Despreading code generating means for deriving a fourth code whose phase sequentially changes, first multiplying means for multiplying the first code by the input signal, and a first connecting means connected to the output terminal of the first multiplying means. Filter means, second multiplying means for multiplying the input signal by the second code, the third code, the fourth code, and a second connected to an output terminal of the second multiplying means.
Filter means, detecting means for detecting the output signal of the second filter means, and detecting means for detecting the output signal of the second filter means when the second code and the third code are multiplied by the input signal in the second multiplying means. Of the transmitting side code by the detection signal of the detecting means when the fourth code and the input signal are multiplied by each other. Phase setting means for detecting a phase state that maximizes the correlation value, determining a match with the current phase state of the first code, and setting the phase of the first code to the detected phase state when they do not match. A spread spectrum signal demodulation circuit characterized by being provided with. 2. The despreading code generating means, code generating means for generating a despreading code, at least one shift register for temporally shifting the output of the code generating means, and the output of the code generating means. 2. The spread spectrum signal demodulation circuit according to claim 1, further comprising selection means for selecting one of the outputs of the shift register and phase control means for controlling the selection means.