JPH06163725A - Production of semiconductor with multilayered wiring construction - Google Patents

Abstract

PURPOSE:To simplify a production process of semiconductor with multilayered wiring construction and improve its reliability. CONSTITUTION:After a conductive thin film 3 is formed on a base interlayer film 2 formed on a substrate 1, a resist 4 is placed thereon and it is etched to form a first wiring section 5. The substrate 1 is immersed in a supersaturated solution of SiO2, so that SiO2 precipitated in the solution 7 may be grown on a gapped section 8 that is the upper face of the film 2 exposing in the clearance between respective wirings in the section 5. When the thickness of an SiO2 film 9 reaches the film thickness of the section 5, the substrate 1 is taken out from a container 6 to remove the resist 4 and it is cleaned. The upper face of the section 5 and the film 9 between the wirings is made to be flat, and further a second wiring section 11 is formed on the upper face with an interlayer insulation film 10 interposed. Thus, a semiconductor with multilayered construction can be formed so as to have no uneven surface in respective wirings thereof and the reliability of the multilayered wiring can be also improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor having a multilayer wiring structure.

[0002]

2. Description of the Related Art A conventional manufacturing process of a semiconductor having a multilayer wiring structure is shown in FIGS. First, as shown in FIG. 2a, an aluminum thin film is formed on a base interlayer film 21 formed on a substrate by a sputtering method, and a desired shape is patterned by a photolithography method or an etching method. The conductive film 22 is formed. In addition,
The film thickness of the first aluminum conductive film 22 is 500 to 100.
It is about 0 nm.

Next, as shown in FIG. 2b, an interlayer insulating film 23 is formed by a plasma CVD method, and thereafter, as shown in FIG. 2c, an SOG 24 for flattening the uneven surface by pattern formation is formed. Apply to the front. That SOG
24 is etched back by an etching method to form an SOG pool 25 as shown in FIG. 2d. And
After forming the interlayer insulating film 26 by the plasma CVD method and subsequently forming the aluminum thin film by the sputtering method, the second aluminum conductive film 2 is patterned by the photolithography method and the etching method into a desired shape.
7 is formed to complete the semiconductor multilayer wiring structure.

In the conventional process described above, before the second aluminum conductive film 27 is formed, the step difference of the base due to the first aluminum conductive film 22 and the like is reduced.
A pool 25 is provided. However, since SOG must prevent corrosion on aluminum,
SOG with interlayer insulating films 23 and 26 formed by plasma CVD
The structure is such that the pool 25 is sandwiched between them. Therefore, there is a problem that a manufacturing process of a semiconductor having a multilayer wiring structure becomes complicated. Further, in the conventional manufacturing method, it is not possible to completely flatten the underlying step due to the first aluminum conductive film 22 or the like, and the second aluminum conductive film 27 formed in the upper layer has a disconnection in the wiring, Alternatively, wiring may be short-circuited due to etching residue, resulting in low reliability.

[0005]

SUMMARY OF THE INVENTION In view of the above problems of the prior art, a main object of the present invention is to provide a multilayer wiring structure which can simplify the manufacturing process of a semiconductor having a multilayer wiring structure and improve reliability. It is to provide a semiconductor manufacturing method.

[0006]

According to the present invention, such an object is to form a conductive film on a base interlayer film formed on a substrate, and to dispose a resist on the conductive film. Forming a first wiring portion by etching, immersing the substrate on which the first wiring portion is formed in a supersaturated solution of SiO ₂ , and a gap between each wiring of the first wiring portion. A step of growing SiO ₂ precipitated from the solution to form a SiO ₂ film having a thickness substantially equal to the film thickness of the first wiring portion, and the step of forming the SiO ₂ film after removing the resist.
Manufacturing a semiconductor having a multilayer wiring structure, which comprises a step of forming an interlayer insulating film on the wiring part and the upper surface of the SiO ₂ film, and a step of forming a second wiring part on the interlayer insulating film. This is accomplished by providing a method.

[0007]

According to this structure, the gap between the wirings of the first wiring portion can be evenly filled with the inter-wiring insulating film made of the SiO ₂ film, and the first wiring portion and the inter-wiring insulating film can be formed. It is possible to form a flat upper surface and to prevent the interlayer insulating film provided thereon from being unevenly formed.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic view showing a manufacturing process of a semiconductor having a multilayer wiring structure to which the present invention is applied. In FIG. 1a, a base interlayer film 2 is formed on a substrate 1, and a conductive thin film 3 is formed on the base interlayer film 2 by, for example, a sputtering method or a CVD method. The material of the conductive thin film 3 is Al-Si-Cu, Al-Si.
-Cu / TiN, Al, Cu, W, etc., and the film thickness thereof is about 100 to 1000 nm. And the resist 4
Is formed into a desired shape by photolithography,
As shown in FIG. 1b, a resist 4 is provided and etching is performed to form a first wiring portion 5.

Next, as shown in FIG. 1c, Si containing a H ₂ SiF ₆ solution in which SiO ₂ is supersaturated is contained in a container 6.
The O ₂ supersaturated solution 7 is filled, and the substrate 1 formed as shown in FIG.
Add H ₃ BO ₃ to. Then, the solution 7 is deposited on the stepped portion 8 which is the upper surface of the underlying interlayer film 2 exposed by the etching except the first wiring portion 5, that is, the gap between the wirings of the first wiring portion 5. The formed SiO ₂ begins to grow. In this case, SiO ₂ does not grow on the surface of the resist 4.

In this way, SiO ₂ is grown until the gaps between the wirings of the first wiring portion 5 are filled up, and then, as shown in FIG.
As shown in FIG. 3, SiO ₂ is grown until the film thickness of the first wiring portion 5 is reached, and Si as an inter-wiring insulating film is formed.
The O ₂ film 9 is formed. SiO in the gap of the first wiring portion 5
_The substrate 1 on which the ₂ film 9 is formed is taken out from the container 6, the resist 4 is removed and washed, and as shown in FIG. 1e, the upper surface of the SiO ₂ film 9 between the first wiring portion 5 and the wiring is removed. A sample formed on a continuous flat surface is formed.

Then, the first wiring portion 5 and the SiO ₂ film 9 are formed.
The interlayer insulating film 10 is formed on the flat upper surface of the substrate by, for example, the plasma CVD method. The interlayer insulating film 10 is made of SiO ₂ or the like. A conductive thin film is deposited on the interlayer insulating film 10 by a sputtering method or a CVD method, and patterned by a photolithography method and etching to form a second wiring portion 11 made of a conductive thin film as shown in FIG. 1g. To complete the formation of a semiconductor having a multilayer wiring structure. The material of the second wiring portion 11 is the same as that of the first wiring portion 5.
Similarly to Al-Si-Cu, Al-Si-Cu / Ti
N, Al, Cu, W and the like.

In the semiconductor thus formed, it is possible to eliminate a step due to the first wiring portion 5 which is a base of the interlayer insulating film 10 and the SiO ₂ film 9 between the wirings, and thus the step shown in FIG. As shown in FIG. 3, since the interlayer insulating film 10 formed between the first wiring portion 5 and the second wiring portion 11 is easily formed flat, the second insulating film 10 as shown in the conventional example is formed. It is possible to prevent disconnection of the wiring portion 11 and short circuit due to etching residue.

[0014]

As described above, according to the present invention, by depositing SiO ₂ from a solution, a SiO ₂ film is formed in the gap between each wiring of the first wiring portion, and each of the first wiring portion is formed. since filling the gap between the wires, without requiring the formation of an interlayer insulating film for preventing corrosion of in Al wiring in the case of the SOG coating, it is possible to simplify the process, SiO ₂ by the growth of the SiO ₂ Since the film is formed, the step on the upper surface of the first wiring portion can be easily flattened, and the second wiring portion formed on the interlayer insulating film can be prevented from being uneven, which is extremely preferable. A semiconductor having a multilayer wiring structure can be formed.

[Brief description of drawings]

1A to 1G are schematic explanatory views showing manufacturing steps of a semiconductor having a multilayer wiring structure to which the present invention is applied.

2A to 2E are schematic explanatory views showing a conventional manufacturing process of a semiconductor having a multilayer wiring structure.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Substrate 2 Underlayer interlayer film 3 Conductive thin film 4 Resist 5 First wiring part 6 Container 7 Solution 8 Step part 9 SiO ₂ film 10 Interlayer insulating film 11 Second wiring part 21 Underlayer interlayer film 22 First aluminum conductive film 23 interlayer insulating film 24 SOG 25 SOG pool 26 interlayer insulating film 27 second aluminum conductive film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H01L 21/31 9274-4M H01L 21/95

Claims (1)

[Claims] 1. A process of forming a conductive film on a base interlayer film formed on a substrate, a process of disposing a resist on the conductive film and forming a first wiring portion by etching, a step of immersing the substrate formed with the first wiring portion in a supersaturated solution of SiO _2, the first of the first and the SiO ₂ is grown to precipitate from the solution in the gap between the wires of the wiring portion A step of forming an SiO ₂ film having a thickness substantially equal to the film thickness of the wiring part, and a step of forming an interlayer insulating film on the upper surfaces of the first wiring part and the SiO ₂ film after removing the resist. And a step of forming a second wiring portion on the interlayer insulating film, the method of manufacturing a semiconductor having a multilayer wiring structure.