JPH06163652A - Wiring board - Google Patents

Wiring board

Info

Publication number
JPH06163652A
JPH06163652A JP4308498A JP30849892A JPH06163652A JP H06163652 A JPH06163652 A JP H06163652A JP 4308498 A JP4308498 A JP 4308498A JP 30849892 A JP30849892 A JP 30849892A JP H06163652 A JPH06163652 A JP H06163652A
Authority
JP
Japan
Prior art keywords
transmission line
wiring board
transmission lines
transmission
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4308498A
Other languages
Japanese (ja)
Inventor
Tetsuya Maruyama
徹也 丸山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4308498A priority Critical patent/JPH06163652A/en
Publication of JPH06163652A publication Critical patent/JPH06163652A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations

Landscapes

  • Structure Of Printed Boards (AREA)
  • Waveguides (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To keep property impedance constant even if at least one hand between the shape of a transmission line and the sectional area is changed optionally. CONSTITUTION:Wiring resistance is reduced by bringing the transmission lines 1 arranged in radial shape close to the shape of a fan with a large area as far as possible, and earth patterns 2a are arranged along both sides of the transmission lines 1, and the interval (d) between the earth pattern 2a and the transmission lines 1 decreases accompanying the reduction of width dimension of the transmission lines 1, thus the property impedance in overall length of the transmission lines 1 is stabilized, and the reduction of transmission loss by the reduction of wiring resistance and the security of the conformity and uniformity of property impedance are reconciled.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、配線基板に関し、特
に、半導体装置の試験技術に用いられるプローブの配線
拡大基板に適用して有効な技術に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board, and more particularly to a technology effectively applied to a wiring expansion board for a probe used in a semiconductor device testing technique.

【0002】[0002]

【従来の技術】たとえば、半導体装置の製造工程では、
ウエハ状あるいは単体の半導体素子の端子に外部から微
細なプローブ(探針)を押し当てて、電気的な導通をと
ることにより、所望の動作試験などが実施される場合が
ある。
2. Description of the Related Art For example, in a semiconductor device manufacturing process,
In some cases, a desired operation test or the like may be performed by pressing a fine probe (probe) from the outside against the terminals of a wafer-shaped or single semiconductor element to establish electrical continuity.

【0003】一方、高周波信号の伝送線などにおいて
は、特性インピーダンスの整合をとるために信号線幅は
一定にしている。この信号線幅は最も信号線密度の高い
微細部に合わせた細い線幅となるために、抵抗や損失が
大きくなりやすい。特に、前述のプローブの配線拡大基
板のように、放射状の信号パターンではこの影響は大き
い。
On the other hand, in a high-frequency signal transmission line or the like, the signal line width is made constant to match the characteristic impedance. Since this signal line width is a thin line width that matches the fine portion with the highest signal line density, resistance and loss are likely to increase. In particular, this effect is large in a radial signal pattern such as the above-described wiring expansion board of the probe.

【0004】なお、従来における半導体装置のプローブ
技術などについては、たとえば、株式会社工業調査会、
昭和58年11月18日発行、「電子材料」1983年
11月号P195〜P198、などの文献に記載されて
いる。
Regarding conventional semiconductor device probe technology and the like, for example, the Industrial Research Institute Co., Ltd.
It is described in documents such as "Electronic Materials", November 18, 1983 issue, P195 to P198, issued on November 18, 1983.

【0005】[0005]

【発明が解決しようとする課題】プローブの放射状の配
線拡大パターンなどのように、中心部と外周部などの伝
送線密度に粗密がある伝送線パタンでは、伝送線密度の
疎密に合わせて信号線幅をなるべく広くすれば、配線抵
抗を下げることができる。しかし、そのままでは特性イ
ンピーダンスを一定に保つことはできない、という問題
を生じる。
In a transmission line pattern having a dense and dense transmission line density such as a central portion and an outer peripheral portion such as a radial enlarged wiring pattern of a probe, the signal line is adjusted according to the density of the transmission line. The wiring resistance can be reduced by making the width as wide as possible. However, there is a problem that the characteristic impedance cannot be kept constant as it is.

【0006】そこで、本発明の目的は、伝送線の形状お
よび断面積の少なくとも一方を任意に変化させても、特
性インピーダンスを一定に保つことが可能な配線基板を
提供することにある。
Therefore, an object of the present invention is to provide a wiring board which can keep the characteristic impedance constant even if at least one of the shape and cross-sectional area of the transmission line is arbitrarily changed.

【0007】本発明の前記並びにその他の目的と新規な
特徴は、本明細書の記述及び添付図面から明らかになる
であろう。
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【0008】[0008]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。
Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

【0009】すなわち、本発明の配線基板は、伝送線
と、この伝送線の近傍に沿って配置され、当該伝送線の
形状および断面積の少なくとも一方の変化に応じた特性
インピーダンスの変化を補償する接地パターンとからな
るものである。
That is, the wiring board of the present invention is arranged along the transmission line and in the vicinity of the transmission line, and compensates the change in the characteristic impedance according to the change in at least one of the shape and the cross-sectional area of the transmission line. It consists of a ground pattern.

【0010】また、本発明は、請求項1記載の配線基板
において、伝送線の断面積が漸減する方向に当該伝送線
と接地パターンの間隔を漸減させる構造にしたものであ
る。
Further, according to the present invention, in the wiring board according to claim 1, the structure is such that the interval between the transmission line and the ground pattern is gradually reduced in the direction in which the cross-sectional area of the transmission line is gradually reduced.

【0011】また、本発明は、請求項1または2記載の
配線基板において、接地パターンを伝送線に沿って不連
続に配置し、隣接する接地パターンの間隔を変化させる
ようにしたものである。
Further, according to the present invention, in the wiring board according to the first or second aspect, the ground patterns are discontinuously arranged along the transmission line, and the interval between the adjacent ground patterns is changed.

【0012】また、本発明は、請求項1,2または3記
載の配線基板を、プローブ・カードを構成する配線拡大
基板として用い、放射状に配置される伝送線を可能な限
り大面積の略扇形状にしたものである。
Further, according to the present invention, the wiring board according to claim 1, 2 or 3 is used as a wiring expansion board which constitutes a probe card, and the transmission lines radially arranged have a fan having the largest possible area. It is shaped.

【0013】[0013]

【作用】上記した本発明の配線基板によれば、たとえ
ば、配線抵抗が下がるように、伝送線密度に合わせて、
伝送線幅をなるべく太くし、最大の伝送線幅と伝送路の
材質に合わせて、目的の特性インピーダンスとなるよう
に配線基板の厚みを厚めにする。そのままでは、伝送線
密度が高く伝送線幅が細くなる部分で、目的の特性イン
ピーダンスよりも高くなるので、接地パターンを適当に
隣接させることで特性インピーダンスの調整を行う。
According to the above-mentioned wiring board of the present invention, for example, the wiring resistance is lowered in accordance with the transmission line density,
The width of the transmission line is made as thick as possible, and the thickness of the wiring board is made thicker so that the target characteristic impedance is obtained, according to the maximum transmission line width and the material of the transmission line. As it is, the characteristic impedance is higher in the portion where the transmission line density is higher and the transmission line width is narrower. Therefore, the characteristic impedance is adjusted by appropriately adjoining the ground pattern.

【0014】これにより、特性インピーダンスの整合を
とったまま、伝送線密度が疎の場所の伝送線幅を広くし
抵抗を下げられるため伝送損失が少なくなり、高周波数
の信号を高精度で伝送することが可能になる。
As a result, the transmission line width can be widened and the resistance can be reduced in a place where the transmission line density is sparse while matching the characteristic impedance, so that the transmission loss is reduced and a high frequency signal is transmitted with high accuracy. It will be possible.

【0015】[0015]

【実施例1】以下、図面を参照しながら、本発明の一実
施例である配線基板について詳細に説明する。
First Embodiment A wiring board which is an embodiment of the present invention will be described in detail below with reference to the drawings.

【0016】図1は、本実施例の配線基板の一部を取り
出して示す平面図であり、図2は、図1において線II−
IIで示される部分の断面図、また図3は、その平面図で
ある。
FIG. 1 is a plan view showing a part of the wiring board of this embodiment taken out, and FIG. 2 is a line II-- in FIG.
A sectional view of a portion indicated by II and FIG. 3 are plan views thereof.

【0017】本実施例の配線基板は、たとえば、半導体
装置の試験技術に用いられるプローブの配線拡大基板と
して構成されている。
The wiring board according to the present embodiment is configured as, for example, a wiring expansion board for a probe used in a semiconductor device testing technique.

【0018】すなわち、放射状に配置された複数の伝送
線1の内端部には、それぞれ半導体素子10に設けられ
た図示しない外部接続端子に押し当てられるプローブ1
aが取り付けられている。伝送線1は、絶縁体3を介し
て上下に配置された導体からなる接地パターン2に挟ま
れた構成となっている。
That is, the inner ends of the plurality of radially arranged transmission lines 1 are pressed against the external connection terminals (not shown) provided on the semiconductor element 10, respectively.
a is attached. The transmission line 1 is sandwiched by grounding patterns 2 made of conductors arranged above and below via an insulator 3.

【0019】この場合、伝送線1は、プローブ1aが接
続される内端部から、図示しない引出し線などが接続さ
れる外端部側に向かって幅寸法が漸増する略扇形状に形
成されており、配置面積を可能な限り有効に利用して、
断面積を大きくすることにより配線抵抗の低減が図られ
ている。
In this case, the transmission line 1 is formed in a substantially fan shape whose width dimension gradually increases from the inner end portion to which the probe 1a is connected to the outer end portion side to which a lead wire (not shown) is connected. And using the layout area as effectively as possible,
Wiring resistance is reduced by increasing the cross-sectional area.

【0020】さらに、本実施例の場合、図2に例示され
るように、個々の伝送線1の両脇に沿って導体からなる
接地パターン2aが配置されている。この接地パターン
2aと伝送線1との間隔dは、当該伝送線1の幅寸法の
減少とともに漸減するように設定されており、伝送線1
の幅寸法の変化による特性インピーダンスの変化を打ち
消し、伝送線1の全長にわたって、特性インピーダンス
を目的の値に一定にする働きをしている。また、隣り合
う伝送線1の間に配置された接地パターン2aは、当該
伝送線1の間におけるクロストークの発生も防止する。
Further, in the case of this embodiment, as illustrated in FIG. 2, the ground pattern 2a made of a conductor is arranged along both sides of each transmission line 1. The distance d between the ground pattern 2a and the transmission line 1 is set so as to gradually decrease as the width dimension of the transmission line 1 decreases.
The function of canceling the change in the characteristic impedance due to the change in the width dimension of (1) and making the characteristic impedance constant over the entire length of the transmission line 1 is maintained. The ground pattern 2a arranged between the adjacent transmission lines 1 also prevents the occurrence of crosstalk between the transmission lines 1.

【0021】このような構成により、伝送線1における
配線抵抗を可能な限り低くして、伝送損失を減少させる
ことができるとともに、伝送線1とプローブ1aおよび
図示しない引出し線との間における特性インピーダンス
の不整合などに起因する信号の反射などの特性の劣化が
回避され、高周波数の信号を高精度に伝達することが可
能となり、半導体素子10の所望の試験を円滑に遂行す
ることができる。
With such a configuration, the wiring resistance of the transmission line 1 can be made as low as possible to reduce the transmission loss, and the characteristic impedance between the transmission line 1 and the probe 1a and the lead wire (not shown). It is possible to avoid deterioration of characteristics such as signal reflection due to mismatching of the signals, to transmit a high frequency signal with high accuracy, and to perform a desired test of the semiconductor element 10 smoothly.

【0022】また、半導体素子10における外部接続端
子数の増大や動作周波数の増大にも容易かつ的確に対応
できる。
Further, it is possible to easily and accurately cope with an increase in the number of external connection terminals in the semiconductor element 10 and an increase in operating frequency.

【0023】[0023]

【実施例2】図4は、本発明の他の実施例である配線基
板の一部を取り出して示す略平面図であり、図5は、図
4において線V −V で示される部分の略断面図である。
[Embodiment 2] FIG. 4 is a schematic plan view showing a part of a wiring board according to another embodiment of the present invention, and FIG. 5 is a schematic view of a portion indicated by line V-V in FIG. FIG.

【0024】この実施例2の場合には、絶縁体3を介し
て伝送線1とは異なる層に配置された接地パターン2b
の間隔d1を、伝送線1の幅寸法の変化に応じて変化さ
せることにより、幅寸法が変化する伝送線1の全長で、
特性インピーダンスが目的の値に一様になるようにした
ところが前記実施例1の場合と異なる。
In the case of the second embodiment, the ground pattern 2b arranged in a layer different from the transmission line 1 with the insulator 3 interposed therebetween.
By changing the distance d1 of the transmission line 1 according to the change of the width dimension of the transmission line 1, the total length of the transmission line 1 whose width dimension changes,
It is different from the case of the first embodiment in that the characteristic impedance is made uniform to a target value.

【0025】これにより、本実施例2の場合にも、伝送
線1における配線抵抗を可能な限り低くして、伝送損失
を減少させることができるとともに、伝送線1とプロー
ブ1aおよび図示しない引出し線との間における特性イ
ンピーダンスの不整合などに起因する信号の反射などの
特性の劣化が回避され、高周波数の信号を高精度に伝達
することが可能となり、半導体素子10の所望の試験を
円滑に遂行することができる。
As a result, also in the case of the second embodiment, the wiring resistance of the transmission line 1 can be made as low as possible to reduce the transmission loss, and at the same time, the transmission line 1, the probe 1a and a lead wire (not shown). It is possible to avoid deterioration of characteristics such as signal reflection due to mismatch of characteristic impedance between and, to transmit a high frequency signal with high accuracy, and to smoothly perform a desired test of the semiconductor element 10. Can be carried out.

【0026】また、半導体素子10における外部接続端
子数の増大や動作周波数の増大にも容易かつ的確に対応
できる。
Further, it is possible to easily and accurately cope with an increase in the number of external connection terminals in the semiconductor element 10 and an increase in operating frequency.

【0027】[0027]

【実施例3】図6は、本発明のさらに他の実施例である
配線基板の一部を取り出して示す略平面図であり、図7
は、図6において線VII −VII で示される部分の略断面
図である。
Third Embodiment FIG. 6 is a schematic plan view showing a part of a wiring board according to still another embodiment of the present invention.
FIG. 7 is a schematic sectional view of a portion indicated by line VII-VII in FIG. 6.

【0028】この実施例3の場合には、伝送線1の両脇
に配置された接地パターン2cを長さ方向に不連続に分
断し、隣り合う接地パターン2cの間隔d2を、その位
置における伝送線1の幅寸法の大小に応じて変化させる
ようにしたものである。
In the case of the third embodiment, the ground patterns 2c arranged on both sides of the transmission line 1 are discontinuously divided in the lengthwise direction, and the distance d2 between adjacent ground patterns 2c is transmitted at that position. The width of the line 1 is changed according to the size.

【0029】分断された接地パターン2cの各々は、絶
縁体3に穿設されたスルーホール3aに充填された導体
2dを介して、下または上側の接地パターン2に導通し
ている。
Each of the divided ground patterns 2c is electrically connected to the lower or upper ground pattern 2 through the conductor 2d filled in the through hole 3a formed in the insulator 3.

【0030】これにより、前記実施例1の場合と同様
に、伝送線1の幅寸法の変化による特性インピーダンス
の変化を、隣り合う接地パターン2cの間隔d2の大小
を調整することで打ち消し、伝送線1の全長にわたって
特性インピーダンスを目的の値に調整することができ
る。
Thus, as in the case of the first embodiment, the change in the characteristic impedance due to the change in the width dimension of the transmission line 1 is canceled by adjusting the size of the interval d2 between the adjacent ground patterns 2c, and the transmission line is changed. The characteristic impedance can be adjusted to a desired value over the entire length of 1.

【0031】この結果、本実施例3の場合にも、伝送線
1における配線抵抗を可能な限り低くして、伝送損失を
減少させることができるとともに、伝送線1とプローブ
1aおよび図示しない引出し線との間における特性イン
ピーダンスの不整合などに起因する信号の反射などの特
性の劣化が回避され、高周波数の信号を高精度に伝達す
ることが可能となり、半導体素子10の所望の試験を円
滑に遂行することができる。
As a result, also in the case of the third embodiment, the wiring resistance of the transmission line 1 can be made as low as possible to reduce the transmission loss, and at the same time, the transmission line 1, the probe 1a and a lead wire (not shown). It is possible to avoid deterioration of characteristics such as reflection of signals due to mismatch of characteristic impedance between them, to transmit high frequency signals with high accuracy, and to perform a desired test of the semiconductor element 10 smoothly. Can be carried out.

【0032】また、半導体素子10における外部接続端
子数の増大や動作周波数の増大にも容易かつ的確に対応
できる。
Further, it is possible to easily and accurately cope with an increase in the number of external connection terminals in the semiconductor element 10 and an increase in operating frequency.

【0033】以上本発明者によってなされた発明を実施
例に基づき具体的に説明したが、本発明は前記実施例に
限定されるものではなく、その要旨を逸脱しない範囲で
種々変更可能であることはいうまでもない。
Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

【0034】たとえば、配線基板の用途としては、プロ
ーブ用の配線拡大基板に限らず、半導体素子を搭載する
パッケージベースなどの配線基板にも広く適用できる。
For example, the application of the wiring board is not limited to the wiring expansion board for the probe, but can be widely applied to a wiring board such as a package base on which a semiconductor element is mounted.

【0035】[0035]

【発明の効果】本願において開示される発明の代表的な
ものによって得られる効果を簡単に説明すれば、下記の
通りである。
The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows.

【0036】すなわち、本発明の配線基板によれば、た
とえば、伝送線幅を微細部に合わせて一様に細くしなく
ても特性インピーダンスの整合がとれる。そのため伝送
線密度が低い所では伝送線幅を広くして配線抵抗を低減
でき高精度な信号伝送が可能となる。
That is, according to the wiring board of the present invention, the characteristic impedance can be matched without making the transmission line width uniformly thin in accordance with the fine portion. Therefore, in a place where the transmission line density is low, the transmission line width can be widened to reduce the wiring resistance and highly accurate signal transmission becomes possible.

【0037】また、局部的に伝送線密度を上げても、配
線抵抗の増加はその部分だけですみ全体への影響が少な
く、伝送線密度の局部的な増加が可能である。これによ
り、伝送線層数の増加を抑止できる。
Further, even if the transmission line density is locally increased, the wiring resistance is increased only in that portion, and the influence on the whole is small, and the transmission line density can be locally increased. This can suppress an increase in the number of transmission line layers.

【0038】また、隣り合う伝送線の間に存在する接地
パターンにより、隣接する伝送線や接地パターンとの間
のクロストークを減少させることができる。
Further, the ground pattern existing between the adjacent transmission lines can reduce the crosstalk between the adjacent transmission lines and the ground pattern.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例である配線基板の一部を取り
出して示す平面図である。
FIG. 1 is a plan view showing a part of a wiring board according to an embodiment of the present invention.

【図2】図1において線II−IIで示される部分の断面図
である。
FIG. 2 is a sectional view of a portion indicated by line II-II in FIG.

【図3】その平面図である。FIG. 3 is a plan view thereof.

【図4】本発明の他の実施例である配線基板の一部を取
り出して示す略平面図である。
FIG. 4 is a schematic plan view showing a part of a wiring board according to another embodiment of the present invention.

【図5】図4において線V −V で示される部分の略断面
図である。
5 is a schematic cross-sectional view of a portion indicated by line V-V in FIG.

【図6】本発明のさらに他の実施例である配線基板の一
部を取り出して示す略平面図である。
FIG. 6 is a schematic plan view showing a part of a wiring board according to still another embodiment of the present invention.

【図7】図6において線VII −VII で示される部分の略
断面図である。
7 is a schematic cross-sectional view of a portion indicated by line VII-VII in FIG.

【符号の説明】[Explanation of symbols]

1 伝送線 1a プローブ 2 接地パターン 2a 接地パターン 2b 接地パターン 2c 接地パターン 2d 導体 3 絶縁体 3a スルーホール 10 半導体素子 d 間隔 d1 間隔 d2 間隔 1 Transmission Line 1a Probe 2 Ground Pattern 2a Ground Pattern 2b Ground Pattern 2c Ground Pattern 2d Conductor 3 Insulator 3a Through Hole 10 Semiconductor Element d Interval d1 Interval d2 Interval

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 伝送線と、この伝送線の近傍に沿って配
置され、当該伝送線の形状および断面積の少なくとも一
方の変化に応じた特性インピーダンスの変動を補償する
接地パターンとからなることを特徴とする配線基板。
1. A transmission line and a ground pattern which is arranged along the vicinity of the transmission line and which compensates for fluctuations in characteristic impedance according to changes in at least one of the shape and cross-sectional area of the transmission line. Characteristic wiring board.
【請求項2】 前記伝送線の断面積が漸減する方向に当
該伝送線と前記接地パターンの間隔を漸減させてなるこ
とを特徴とする請求項1記載の配線基板。
2. The wiring board according to claim 1, wherein the distance between the transmission line and the ground pattern is gradually reduced in a direction in which the cross-sectional area of the transmission line is gradually reduced.
【請求項3】 前記接地パターンは前記伝送線に沿って
不連続に配置され、隣接する前記接地パターンの間隔を
変化させてなることを特徴とする請求項1または2記載
の配線基板。
3. The wiring board according to claim 1, wherein the ground pattern is discontinuously arranged along the transmission line, and the interval between the adjacent ground patterns is changed.
【請求項4】 プローブの配線拡大基板であり、放射状
に配置される前記伝送線を可能な限り大面積の略扇形状
にしてなることを特徴とする請求項1,2または3記載
の配線基板。
4. A wiring board according to claim 1, wherein the wiring board is a wiring expansion board for a probe, and the transmission lines arranged in a radial pattern are formed into a fan shape having a large area as much as possible. .
JP4308498A 1992-11-18 1992-11-18 Wiring board Pending JPH06163652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4308498A JPH06163652A (en) 1992-11-18 1992-11-18 Wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4308498A JPH06163652A (en) 1992-11-18 1992-11-18 Wiring board

Publications (1)

Publication Number Publication Date
JPH06163652A true JPH06163652A (en) 1994-06-10

Family

ID=17981743

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4308498A Pending JPH06163652A (en) 1992-11-18 1992-11-18 Wiring board

Country Status (1)

Country Link
JP (1) JPH06163652A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010050104A (en) * 2003-02-19 2010-03-04 Moog Inc Wider band high frequency slip ring system
JP2011035525A (en) * 2009-07-30 2011-02-17 Nec Corp Printed wiring board and method for printed wiring

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010050104A (en) * 2003-02-19 2010-03-04 Moog Inc Wider band high frequency slip ring system
JP2011035525A (en) * 2009-07-30 2011-02-17 Nec Corp Printed wiring board and method for printed wiring

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