JPH06163601A - Field effect transistor - Google Patents

Abstract

PURPOSE:To prevent performance degradation due to crystal transition fault caused when an In composition ratio is made larger. CONSTITUTION:On a semi-insulation InP substrate 1, an InAs/AlAs super lattice buffer layer 2, an InxGa1-xAs current channel layer 3, an InyAl1-yAs electron supply layer 4, and an InxGa1-xAs contact layer 5 are formed. Relating to the super lattice layer 2, the ratio t1/t2, between the thickness t1 of an InAs layer 10 and that t2 of an AlAs layer 11, gradually changes as they proceed to an upper layer, so that lattice conformity is obtained with the semi-insulation InP substrate 1 and the AlAs layer 11. Thanks to the super lattice layer 2, inter-lattice distortion between the semi-insulation InP substrate 1 and the InxGa1-xAs current channel layer 3 is relaxed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor using a compound semiconductor, and more particularly to a field effect transistor having a semiconductor heterojunction.

[0002]

2. Description of the Related Art In _0.53 Ga lattice-matched with an InP substrate
_0.47 As has a higher electron mobility and saturation velocity than GaAs, and as a semiconductor material suitable for a high frequency FET of 1 GHz or more, trial manufacture of an FET using In _0.53 Ga _0.47 As as a current channel is underway.

[0003] for example, undoped In _0.53 Ga _0.47 As lattice-matched (lattice constant match) and, when the heterojunction and a small electron affinity N-type In _0.52 Al _0.48 As, a heterojunction interface of the undoped In _0.53 Ga _0.47 As An electron accumulation layer called a two-dimensional electron gas having high mobility is formed on the surface. FET using this two-dimensional electron gas as a current channel
In, the cutoff frequency f _T = 250 GHz is obtained. This is superior to any other material system.

[0004] Increasing the In composition ratio of In _X Ga _1-X As, electron mobility and saturation velocity increases, the electron concentration of the two-dimensional electron gas has been demonstrated to increase. Therefore, attempts have been made to increase the In composition ratio of the In _0.53 Ga _0.47 As current channel layer to further improve f _T.

Next, a conventional FET will be described with reference to FIG. This is G. I. Ng and others are IEEE Tra
nsactions on Electron Dev
ices, vol. 36, no. 10, pp. 2249
˜2259, 1989.

Undoped In _0.52 Al _0.48 As buffer layer 2a lattice-matched to the semi-insulating InP substrate 1, undoped In _x Ga _1-X As (0.53 <X) having a large lattice constant.
<1) current channel layer 3, Si-doped N-type In _0.52 Al _0.48 As electron supply layer 4a and the Si-doped N-type In _0.53 Ga _0.47 As contact layer 5a of the InP substrate 1 and the lattice matching is grown.

Electrons move from the N-type In _0.52 Al _0.48 As electron supply layer 4a to the undoped In _x Ga _{1 -x} As current channel layer 3 to form a two-dimensional electron gas. The gate electrode 7 modulates the electron concentration of the two-dimensional electron gas between the source electrode 8 and the drain electrode 9 to control the current flowing between the source electrode 8 and the drain electrode 9.

[0008]

In the conventional FET, f _T
When the composition ratio of the undoped In _x Ga _1-X As current channel layer exceeds 0.7 in an attempt to improve the, an In _x Ga
_1-X As current channel layer and undoped In _0.52 Al _0.48
The difference in the lattice constant with the As buffer layer becomes large,
The interstitial strain in the crystal increases. Dislocation defects occur in the In _x Ga _1-x As current channel layer, and the performance of the FET deteriorates.

[0009]

A field effect transistor of the present invention comprises a superlattice buffer layer and a current channel layer in which two different types of semiconductor layers are alternately laminated on one main surface of a semiconductor substrate. The lattice buffer layer is lattice-matched at the junction surface with the semiconductor substrate and is also lattice-matched at the junction surface with the current channel layer.

[0010]

[Function] By the MBE (Molecular Beam Epitaxy) method,
A superlattice layer is formed by alternately laminating two kinds of compound semiconductor layers having different lattice constants and having a film thickness that does not cause crystal transition defects.

By limiting the thickness of each layer to 5 nm or less, InAs and AlA having a lattice constant difference of 7% can be obtained.
It is possible to alternately stack s and several hundred nm or more. Further, it is possible to form an InAs / AlAs superlattice layer corresponding to In _0.52 Al _0.47 As that lattice-matches with InP.

The ratio t ₁ / t ₂ between the thickness t _{1 of the} InAs layer and the thickness t ₂ of the AlAs layer is 0.52 / 0.48≈1.08.
Then, the superlattice layer in which the InAs layer and the AlAs layer are alternately laminated can be regarded as having the same lattice constant as the In _0.52 Al _0.48 As layer, and is lattice-matched with the InP substrate.

Further, the t ₁ / t ₂ of the superlattice layer is gradually increased so that the lattice constant is matched with that of the In _x Ga _1-x As current channel layer (0.7 <X <1) thereon. To

[0014]

EXAMPLE A first example of the present invention will be described with reference to FIGS. 1 (a) and 1 (b).

On the semi-insulating InP substrate 1 having a plane orientation (100) doped with Fe, undoped InA by the MBE method.
AlAs / InAs superlattice buffer layer 2 in which s layers 10 and undoped AlAs layers 11 are alternately stacked, undoped In _X Ga _1-X As current channel layer 3, Si-doped N type In _Y Al _1-Y As electron supply layer 4 and Si-doped N-type In _x Ga _1-x As contact layer 5 are sequentially epitaxially grown.

The undoped In _X Ga _1-X As current channel layer 3 had an In composition ratio X of 0.8 and a thickness of 15 nm. The In composition ratio Y of the N-type In _Y Al _1-Y As electron supply layer 4 is set to Y = 0.8 so that the In composition ratio Y of the N-type In _Y Al _1-Y As electron supply layer 4 becomes almost the same as that of the In _X Ga _1-X As current channel layer 3, and Si of The doping concentration was 2 × 10 ¹⁸ cm ⁻³ and the thickness was 40 nm. The N-type In _X Ga _1-X As contact layer 5 is also In _X G
a _1−X As current channel layer 3 and Y = 0.8 so as to match the lattice constant, and the doping concentration of Si is 1 × 10.
^The thickness was set to ¹⁹ cm ⁻³ and the thickness was set to 50 nm.

Next, the InAs / AlAs superlattice layer 2 will be described in detail with reference to FIG.

At the interface of the semi-insulating InP substrate 1, the ratio of the thickness t ₁ of the InAs layer 10 to the thickness t ₂ of the AlAs layer t ₁ / t.
₂ was close to 0.52 / 0.48, and t ₁ = t ₂ = 5 nm at which the lattice constant substantially matches that of InP. InAs / Al
As the upper layer of the As superlattice layer 2 increases, t ₁ + t ₂ = 10
The thickness of t ₁ / t ₂ is gradually increased while maintaining nm, and the undoped In _X Ga _1-X As current channel layer 3 (X =
0.8), so that the lattice constants are matched at the interface t ₁
= 8 nm and t ₂ = 2 nm, the total thickness of the InAs / AlAs superlattice layer 2 was set to 500 nm.

[0019] N-type In _X Ga _1-X As ohmic contact with the contact layer 5 Au-Ge / Ni (gold - germanium - nickel) source and drain electrodes 8 and 9 made of is formed. N in the recess region formed by etching the N-type In _X Ga _1-X As contact layer 5
A gate electrode 7 made of Al (aluminum) that forms a Schottky junction with the type In _Y Al _{1 -Y} As electron supply layer 4 is formed.

The undoped In _X between the source electrode 8 and the drain electrode 9 is controlled by the voltage applied to the gate electrode 7.
The current flowing through the Ga _1-X As current channel layer 3 is controlled.

When the In composition ratio X of the undoped In _X Ga _1-X As current channel layer 3 is 0.8, the conventional FET
In this case, the difference in lattice constant between the In _0.52 Al _0.48 As buffer layer and the InP substrate becomes large, and dislocation defects due to interstitial strain occur, resulting in performance deterioration. On the other hand, in this embodiment, I
NAS / AlAs superlattice layer 2, are substantially lattice matched any of the interface between the interface and the semi-insulating InP substrate 1 and In _X Ga _1-X As current channel layer 3.

Semi-insulating InP substrate 1 and In _X Ga _1-X A
The interstitial strain caused by the difference in lattice constant from the s-current channel layer 3 is relaxed by the InAs / AlAs superlattice layer 2 superlattice, and no dislocation defect occurs in the crystal. Therefore, in the FET of the present embodiment, the electron mobility and the saturation velocity are increased by the amount corresponding to the increase in the In composition ratio X of the In _x Ga ₁ -x As current channel layer from 0.53 which is lattice-matched with InP to 0.8. The electron concentration of the two-dimensional electron gas increases. When the In composition ratio X was increased to 0.8, the problem of performance deterioration that occurred in the conventional FET could be solved.

Next, a second embodiment of the present invention will be described.

Although the semi-insulating InP substrate was used in the first embodiment, a Cr-doped semi-insulating GaAs substrate was used in this embodiment instead of the InP substrate.

Since GaAs has almost the same lattice constant as AlAs, it is necessary to change the film thickness ratio of the InAs / AlAs superlattice. On the semi-insulating GaAs substrate side, the ratio of the thickness t ₁ of the InAs layer to the thickness t ₂ of the AlAs layer t ₁ / t ₂ =
0, that is, t ₁ = 0 and t ₂ = 10 nm, t ₁ + t
₂ = 10 nm is maintained and t ₁ / t ₂ is gradually increased toward the upper layer, and t ₁ / t ₂ = 0.0 on the In _x Ga ₁ -x As current channel layer (X = 0.8) side. 8 / 0.2
So that t ₁ = 8 nm and t ₂ = 2 nm.

In this embodiment, the difference in the lattice constant between the semiconductor substrate and the In _x Ga ₁ -x As current channel layer is larger than that in the first embodiment, and therefore InA is used to relax the interstitial strain.
The thickness of the s / AlAs superlattice layer is 10 times that of the first embodiment.
It was set to 00 nm.

Other than that, the same performance as that of the first embodiment could be obtained in the same manner as the first embodiment. No performance deterioration due to crystal transition defects was observed.

There is also an advantage that a GaAs substrate, which is cheaper than the InP substrate and is excellent in mechanical strength and handleability, can be used.

[0029]

[Effect of the Invention] InAs layer and the AlAs layer InAs / AlAs superlattice layers of alternately laminated and In _X Ga _1-X As current channel layer is formed on a semiconductor substrate, the superlattice layer is a semiconductor substrate and the current The InAs layer has a thickness t ₁ and the AlAs layer has a thickness t so that lattice matching is achieved on the channel layer side.
₂ and of the ratio t ₁ / t ₂ was gradually increased.

With this superlattice layer, the semiconductor substrate and the In _x
The interstitial strain caused by the difference in the lattice constant from the Ga _{1 -X} As current channel layer is relaxed, the occurrence of dislocation defects in the In _x Ga _1-X As current channel layer is suppressed, and the performance of the FET is degraded. Could be resolved.

[Brief description of drawings]

FIG. 1A is a sectional view showing a first embodiment of the present invention. (B) is an enlarged sectional view showing an InAs / AlAs superlattice layer.

FIG. 2 is a cross-sectional view showing a conventional FET.

[Explanation of symbols]

1 Semi-insulating InP substrate 2 InAs / AlAs superlattice buffer layer 2a In _0.52 Al _0.48 As buffer layer 3 In _X Ga _1-X As current channel layer 4 In _Y Al _1-Y As electron supply layer 4a In _0.53 Al _0.48 As Electron supply layer 5 In _X Ga _1-X As contact layer 5a In _0.53 Ga _0.47 As contact layer 6 Recess 7 Gate electrode 8 Source electrode 9 Drain electrode 10 InAs layer 11 AlAs layer

Claims (2)

[Claims] 1. A superlattice buffer layer and a current channel layer in which two different types of semiconductor layers are alternately laminated are formed on one main surface of a semiconductor substrate, and the superlattice buffer layer is formed on a junction surface with the semiconductor substrate. A field-effect transistor which is lattice-matched and lattice-matched at a junction surface with the current channel layer. 2. The field effect transistor according to claim 1, wherein the superlattice layer comprises an InAs layer and an AlAs layer, and the current channel layer comprises an InGaAs layer.