JPH06163560A - Semiconductor integrated circuit and fabrication thereof - Google Patents

Abstract

PURPOSE:To obtain a lateral bipolar transistor in which cut-off frequency is improved, noise factor is lowered, and chip cost is reduced by shortening base current path and decreasing base resistance and element size. CONSTITUTION:A semiconductor integrated circuit comprises an emitter region 18-collector region 19 formed oppositely on the surface layer part in base region 14, a guard electrode 16 for preventing surface inversion of base region formed through a first dielectric film 15 on the surface of substrate corresponding to an active base region between the emitter and collector regions. The integrated circuit further comprises a base electrode contact region 20 formed in the active base region, an emitter electrode 23 and a collector electrode 24, and a base electrode 22 formed to make contact with the guard electrode and the base electrode contact region through a contact hole made through a second dielectric film, the guard electrode, and the first dielectric film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a method of manufacturing the same, and more particularly to a structure of a lateral (horizontal) bipolar transistor and a method of forming the same.

[0002]

2. Description of the Related Art FIG. 3 shows a sectional structure of a conventional lateral PNP transistor.

Here, 30 is a P-type substrate and 31 is N ^+. A buried layer, 32 is a P type epitaxial layer, 33 is an N well for a base region, 34 is a field insulating film for element isolation, and 35 is a thin oxide film formed on a part of the substrate surface. In some cases, an N-type epitaxial layer is formed instead of the P-type epitaxial layer 32, and a deep P-type diffusion layer for element isolation is formed in this N-type epitaxial layer.

N ⁺ is formed on the oxide film 35 and is drawn out of the active region of the lateral PNP transistor. It is made of polysilicon and has a role of a guard electrode for preventing the inversion of the N well surface (base region surface) when the same potential as that of the N well 33 is applied.

Reference numeral 37 denotes the base region 33 from the surface of the base region.
Through the bottom part of the bottom N ⁺ Deep N ⁺ formed so as to be deeply diffused so as to be continuous with the buried layer 31. A base electrode contact region, and an emitter region (P ⁺ Area). Reference numeral 39 denotes a collector region (P ⁺ which is formed so as to face the emitter region 38 and is diffused in a part of the surface layer of the base region). Area),
It is formed so as to surround the emitter region 38 in order to enhance the injection efficiency of the emitter current. Reference numeral 40 is an interlayer insulating film. 41 is a base electrode, 42 is an emitter electrode, 43
Is a collector electrode, and for example, aluminum is used for each.

In the lateral PNP transistor, the field insulating film 34 is formed near the end of the surface of the base region.
A base electrode contact region 37 is formed in the base region 33 outside thereof, and a guard electrode (N ⁺ for preventing the base region surface inversion is formed above the base electrode contact region 37). The polysilicon) 36 and the base electrode 41 are in contact with each other.

In such a structure, the base current path becomes long and the base resistance becomes large, so that the cutoff frequency is lowered and the noise figure is increased. Moreover, the element size also increases, and the chip cost increases.

[0008]

As described above, the conventional lateral PNP transistor has a problem that the cut-off frequency is lowered and the noise figure is increased, and the chip cost is increased.

The present invention has been made to solve the above-mentioned problems, and the base current path becomes short, the base resistance becomes small and the element size becomes small, and the cutoff frequency is improved, the noise figure is lowered, and the chip cost is reduced. It is an object of the present invention to provide a semiconductor integrated circuit having a bipolar transistor having a lateral structure capable of reducing the power consumption and a manufacturing method thereof.

[0010]

A semiconductor integrated circuit of the present invention has a buried layer of the first conductivity type selectively inside and a second conductivity type opposite to the first conductivity type having an epitaxial layer on the surface. Type semiconductor substrate, a first conductivity type well region for the base region formed so as to be continuous with the buried layer on the surface of the semiconductor substrate, and selectively formed on a part of the surface of the epitaxial layer. Corresponding to a field oxide film for element isolation, an emitter region and a collector region of the second conductivity type formed in the surface region of the well region so as to face each other, and an active base region between the emitter region and the collector region. And a guard electrode for preventing surface reversal of the base region formed on the surface of the substrate via a first insulating film, and a position corresponding to the lower part of the guard electrode in the surface layer of the well region. The base electrode contact region of the first conductivity type formed between the emitter region and the collector region, the second insulating film formed on the guard electrode and the substrate, and the opening in the second insulating film. A contact formed in the second insulating film, the guard electrode and the first insulating film, and an emitter electrode and a collector electrode formed so as to correspond to the emitter region and the collector region through the formed contact hole. It is characterized by comprising a base electrode formed so as to contact the guard electrode and the base electrode contact region through a hole.

Further, according to the method for manufacturing a semiconductor integrated circuit of the present invention, the buried layer containing the impurity of the first conductivity type opposite to the second conductivity type at a high concentration is selectively provided inside the semiconductor substrate of the second conductivity type. And forming an epitaxial layer on the surface thereof, and then selectively forming a well region of the first conductivity type in the epitaxial layer so as to be continuous with the buried layer, and thereafter, the epitaxial layer A step of selectively forming a field oxide film for element isolation regions on the layer surface, a step of forming a first insulating film on the surface of the epitaxial layer, and a step of forming a first insulating film on the first insulating film thereafter. Forming a guard electrode for preventing surface reversal of the base region above a portion of the well region corresponding to the active base region, and thereafter, on both sides below the guard electrode in the surface layer portion of the well region Forming an emitter region and a collector region facing each other at corresponding positions, and forming a base electrode contact region between the emitter region and the collector region at a position corresponding to below the guard electrode in the surface layer portion of the well region. And a step of forming a second insulating film on the guard electrode and the substrate, forming an electrode contact hole, forming an electrode of a metal or a metal compound, and forming a surface protective film. It is characterized by including.

[0012]

The base electrode contact region of the lateral PNP transistor is formed between the emitter region and the collector region, and the base region surface inversion prevention guard electrode is formed in the region covering the base electrode contact region. The base electrode is formed so as to contact the guard electrode and the base electrode contact region through the contact hole opened in the guard electrode.

As a result, the base current path of the lateral PNP transistor becomes short, the base resistance becomes small, and the element size becomes small, so that the cutoff frequency can be improved, the noise figure can be lowered, and the chip cost can be reduced. .

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows an example of a plane pattern of a lateral PNP transistor according to an embodiment of the present invention.

A device forming region (lateral PNP transistor forming region) surrounded by a device isolation region 14 in the surface layer of the substrate.
, 13 is an N-type base region, 18 is an emitter region (P ⁺ Regions 19 and 19 are collector regions (P ⁺ Region), and the emitter region 18 is provided in order to increase the injection efficiency of the emitter current.
Is formed so as to surround the. An emitter electrode (not shown) and a collector electrode (not shown) are formed on the surface of the substrate via an insulating film (not shown) so as to contact the emitter region 18 and the collector region 19 respectively. There is. Reference numeral 16 is a guard electrode for preventing surface reversal of the base region, which is formed on the substrate surface corresponding to the active base region between the emitter region 18 and the collector region 19 via an insulating film (not shown). This guard electrode 1
A base electrode (not shown) is formed so as to contact 6 and the active base region. Reference numeral 20 denotes a base electrode contact region (N ⁺ Area).

2A to 2C are sectional views (sections taken along line BB in FIG. 1) of the semiconductor wafer in the main steps of the method for manufacturing the lateral PNP transistor according to the embodiment of the present invention. Is shown.

First, as shown in FIG. 2A, a P-type semiconductor substrate (for example, a silicon substrate) 10 is formed by a normal process.
Selectively inside N ⁺ The buried layer 11 is formed, and the P-type epitaxial layer 12 is grown on the surface. After that, a portion of the epitaxial layer 12 (element formation planned region) is provided with the N
⁺ An N well 13 for a base region is diffused and formed so as to be continuous with the buried layer 11. Next, the epitaxial layer 12 is formed by using PEP (photolithography process) and a usual selective oxidation method.
A field insulating film 14 is formed so as to surround the upper element formation region. Next, a thin first oxide film 15 is formed on the surface of the substrate.

Next, polysilicon is deposited on the first oxide film 16 and the polysilicon 1 is formed by ion implantation or the like.
6 is doped with N-type impurities such as phosphorus (for example, arsenic),
Convert to N ⁺ polysilicon.

Next, a photoresist 17 is applied on the N ₊ polysilicon 16 and patterned so that the photoresist 17 covers the active base region (base region between the emitter region and the collector region).

Next, using the photoresist 17 as an etching mask, anisotropic ion etching using RIE (reactive ion etching) is performed to obtain N ^+. Polysilicon 16
Is etched to leave a guard electrode 17 for preventing the surface inversion of the base region so as to cover the active base region. Next, using the photoresist 17 as a blocking mask, P
Ion implantation of a type impurity (for example, boron) is performed.

Next, the implanted ions are activated by annealing (heat treatment) so that the N well region 1 is formed.
3 into the emitter region (P ⁺ Region 18 and a collector region (P ⁺ Region 19) is formed.

Next, the photoresist 17 is peeled off,
As shown in FIG. 2B, by using PEP and RIE, N ⁺ at a position corresponding to the base electrode contact region is formed. A hole is opened in the polysilicon 16 and the first oxide film 15. Then, ion implantation of N-type impurities is performed.

Next, the implanted ions are activated by annealing (heat treatment) so that the N well region 1 is formed.
4 in the surface region of the base region, and the base electrode contact region (N
⁺ Region) 20 is formed.

Next, as shown in FIG. 2C, a CVD (vapor phase growth) oxide film 21 is deposited on the substrate. And P
An emitter contact hole, a collector contact hole, and a base contact hole are formed in the CVD oxide film 21 by using EP and RIE.

Next, in order to form electrodes (and wiring) made of a metal or a metal compound, for example, aluminum is sputtered and patterned on the substrate. As a result, a base electrode 22, an emitter electrode 23 and a collector electrode 24 are formed in contact with the base electrode contact region 20, the emitter region 18 and the collector region 19, respectively.

Next, a sintering process is performed to activate the electrodes, and finally, a surface protective film (not shown) is formed by the CVD method, and a PEP process for forming a bonding pad region is performed to complete the process.

An N-type epitaxial layer may be formed instead of the P-type epitaxial layer 12, and a deep P-type diffusion layer for element isolation may be formed in the N-type epitaxial layer in a later step. .

In the lateral PNP transistor formed as shown in FIG. 2C, the base electrode contact region 20 is formed between the emitter region 18 and the collector region 19, and the base electrode contact region 20 is formed above the base electrode contact region 20. A guard electrode 16 for preventing surface reversal of the base region is formed in a region to be covered, and a base electrode 22 is formed so as to contact the guard electrode 16 and the base electrode contact region 20 through a contact hole formed in the guard electrode 16. There is.

As a result, as compared with the conventional lateral PNP transistor, the base current path becomes shorter, the base resistance becomes smaller, and the element size becomes smaller, so that the cutoff frequency is improved, the noise figure is lowered, and the chip cost is reduced. It will be possible.

Further, according to the method of manufacturing the bipolar transistor as described above, the cutoff frequency and the noise figure are improved within the range of the miniaturization technology which can be usually achieved, and the bipolar transistor having a small element size can be realized. it can.

[0031]

As described above, according to the present invention, the base current path becomes shorter, the base resistance becomes smaller, and the element size becomes smaller, so that the cutoff frequency is improved, the noise figure is lowered, and the chip cost is reduced. It is possible to realize a semiconductor integrated circuit having a bipolar transistor having a lateral structure and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a plane pattern of a lateral PNP transistor according to an embodiment of the present invention.

FIG. 2 is a view showing a cross-sectional structure of a semiconductor wafer in a main step of the method for manufacturing the lateral PNP transistor of FIG.

FIG. 3 is a sectional view showing a part of a conventional lateral PNP transistor.

[Explanation of symbols]

10 ... Semiconductor substrate, 11 ... N ⁺ Buried layer, 12 ... P-type epitaxial layer, 13 ... N well, 14 ... Field insulating film, 15 ... First oxide film, 16 ... Base region surface inversion prevention guard electrode, 18 ... Emitter region, 19 ... Collector region , 20 ... Base electrode contact region, 21 ...
CVD oxide film, 22 ... Base electrode, 23 ... Emitter electrode, 24 ... Collector electrode.

Claims (2)

[Claims] 1. A semiconductor substrate of a second conductivity type opposite to the first conductivity type having a buried layer of the first conductivity type selectively inside and an epitaxial layer on the surface, and a surface of the semiconductor substrate. A first conductivity type well region for a base region formed so as to be continuous with the buried layer; a field oxide film for element isolation selectively formed on a part of the surface of the epitaxial layer; and the well region. A second conductive type emitter region and a collector region formed to face each other in the surface layer part of the substrate, and a first insulating film on the substrate surface corresponding to the active base region between the emitter region and the collector region. And a guard electrode for preventing surface reversal of the base region, and a phase difference between the emitter region and the collector region at a position corresponding to the lower side of the guard electrode in the surface layer portion of the well region. The first conductivity type base electrode contact region formed between the second insulating film and the second insulating film formed on the guard electrode and the substrate, and the emitter region through a contact hole formed in the second insulating film. And an emitter electrode and a collector electrode formed so as to correspond to the collector region, and the guard electrode and the base through contact holes formed in the second insulating film, the guard electrode and the first insulating film. A semiconductor integrated circuit, comprising: a base electrode formed so as to contact an electrode contact region. 2. A buried layer containing a high concentration of an impurity of a first conductivity type opposite to the second conductivity type is selectively formed inside a semiconductor substrate of a second conductivity type, and an epitaxial layer is formed on the surface. A step of selectively forming a well region of the first conductivity type in the epitaxial layer so as to be continuous with the buried layer, and thereafter, a field oxide film for an element isolation region on the surface of the epitaxial layer. And a step of forming a first insulating film on the surface of the epitaxial layer, and a step of forming a first insulating film on the surface of the first insulating film corresponding to the active base region of the well region. A step of forming a guard electrode for preventing surface reversal of the base region above, and thereafter, emitters facing each other at positions corresponding to both sides below the guard electrode in the surface layer part of the well region. Forming a region and a collector region, and thereafter forming a base electrode contact region between the emitter region and the collector region at a position corresponding to below the guard electrode in the surface layer portion of the well region, After that, a step of forming a second insulating film on the guard electrode and the substrate, opening an electrode contact hole, forming an electrode of a metal or a metal compound, and forming a surface protective film. A method of manufacturing a semiconductor integrated circuit having a feature.