JPH0616355B2 - Static memory - Google Patents

Description

The present invention relates to a static memory, and more particularly to a metal oxide semiconductor field effect transistor (hereinafter abbreviated as MOSFET).
For static memory using.

[Conventional technology]

Conventionally, as the memory cell of the static memory, the one of the circuit shown in FIG. 4 is often used. In Figure 4, R ₁ ,
R ₂ is a high-resistance polycrystalline silicon, Q _{1 to} Q ₄ are N-channel MOSFETs, DG and ▲ ▼ are a pair of digit lines, WD is a word line, and 40 is a data line selecting word line. And 41 is an inverter for driving the word line. Further, C ₁ and C ₂ are electrostatic capacitances equivalently attached to the nodes of the memory cell, and 42 is a power supply terminal.

[Problems to be solved by the invention]

In the static memory cell using the conventional memory cell described above, as the memory cell area is reduced due to high integration and large capacity, the electrostatic capacitances C ₁ and C ₂ of the memory cell node decrease, and the memory cell node Since the amount of electric charge accumulated in the memory cell is reduced, there is a drawback that the α-ray emitted from the package, the wiring material of the memory, or the like easily causes a malfunction such that the data written in the memory cell is lost. Hereinafter, description will be given with reference to FIG.

FIG. 5 is a waveform diagram of each circuit node when a write operation is performed in the circuit of FIG. In FIG. 5, 51 is a word line waveform, 52 is a memory cell node N ₁ waveform, 53 is a memory cell node N ₂ waveform, 54 is a digit line DG waveform,
Reference numeral 55 is a waveform of the digit line (5), and reference numeral 56 is a write control signal waveform applied from the outside. The address changes at time t ₀ , and the write control signal changes from read to write at t ₁ . Address is selected word line level at time t ₂ receives the changed rises to "H" to "L". Further, in response to the change to write at t ₁ , write data is transmitted to the digit line at t ₃ , DG goes to “L”, ▲ ▼ goes to “L”, and ▲.
▼ becomes “H”. Then, the memory cell nodes N ₁ , N
₂ changes following this, and N ₁ changes from “H” to “L”
Then, N ₂ changes from “L” to “H”. Next, at t ₄ , the write control signal changes from write to read, and the write operation is completed. It should be noted here that the "H" of the memory cell node N ₂ at the time of completion of writing reaches a level lower than the Vcc level by the threshold voltage V _T of the transfer gate MOSFET. Then, the node capacitance C is raised from this level to the Vcc level through the high resistance R ₂ of the memory cell load.
_This is because the high resistance R ₂ is very large and reaches about 3 × 10 ¹¹ ohms, so the time constant for charging is 6 when C ₂ is 2 × 10 ^-14 PF. It will be a large value of milliseconds. Normally, the operation speed of a static memory is about 100 + 1 seconds, and thus the time of 6 milliseconds is a length that enables access to a memory cell of 60,000 bits. Therefore, there is a great risk that the data in the memory cell will be lost when the α-ray hits during the period from the end of writing until the "H" level of the cell reaches the power supply level. Actually, when the "H" level is 3v and when it is 5v, the probability that data is lost is higher 1000 times to 10000 times in the case of 3v than in the case of 5v.

In recent years, static memory has been highly integrated and increased in capacity by about 3
It progresses at an astonishing speed of 4 times a year, and the memory cell node capacitance becomes smaller and smaller, and the high resistance of the memory cell load further increases due to the progress of low power consumption. In the direction. Therefore, in the conventional memory cell, there is a problem that the probability of malfunctioning due to α-rays increases. In order to deal with such a situation, after forming the gate electrode only in the memory cell part, an insulating film of about 500 Å to 200 Å is attached, and an electrode connected to a fixed potential is further formed on it to increase the memory cell node capacitance. That method has been devised. However, even if this method is used, the increase in capacitance is about 0.01 pF, which is not always sufficient.

[Means for solving problems]

The present invention greatly improves the malfunction of the conventional static memory due to the α ray as described above.

The static memory according to the present invention is used as a flip-flop memory cell in which a high resistance element is used as a load element, and a logic signal arranged in parallel with the word line for each word line. A line having one end connected to a cross connection point of flip-flops of a memory cell and the other end connected to a logic signal line, wherein the logic signal line has a word line at a high level and in a write state. It is characterized in that a logic signal is applied which changes to a low level and changes from a low level to a high level after completion of writing.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. 1 is different from FIG. 4 shown in the conventional example in that capacitors C ₃ and C ₄ are added to the memory cell node, and a NAND logic of a word line signal and a write control signal is taken at the opposite electrode of the capacitor. Is being applied. FIG. 2 shows the circuit of FIG. 1 in an actual layout. In FIG. 2, numeral 20 corresponds to the word line WD in FIG.
2 corresponds to the gate portions of the transfer gate MOSFETs Q ₁ and Q ₂ , and 23 and 24 are transfer gates M.
Corresponding to the diffusion layers on the memory cell node side of the OSFETs Q ₁ and Q ₂ , 25 and 26 are transfer gate MOSFETs Q.
₁ and Q ₂ digit line side diffusion layers and digit lines DG and D
27 and 28 correspond to the gate portions of the flip-flop MOSFETs Q ₃ and Q ₄ , 29 corresponds to the drain side diffusion layer of the flip-flop MOSFET Q ₄ , and 200, 201 and 202 correspond to the contact holes connecting to G. A direct contact hole 203 connects the first polysilicon and the diffusion layer, and 203 is a flip-flop MOSFET Q ₃ , Q _4.
Is a ground side diffusion layer, and 204 is a second-layer polysilicon electrode that forms a capacitor between itself and a memory cell node, and corresponds to 13 in FIG. In FIG. 2, high resistance elements R ₁ and R ₂ are formed for the sake of clarity. The third layer of polysilicon is omitted. In the layout shown in FIG. 2, the capacitor C ₁ is formed between the polysilicon 204 of the second layer, the diffusion layer 23, and the first polysilicon forming the gate of the MOSFET Q ₄ , and the second layer is formed. Polysilicon 204 and diffusion layers 29 and M
The capacitor C ₂ will be formed between the OSFET Q ₃ and the first polysilicon 28 forming the gate of the OSFET Q ₃ .

Next, the operation of the circuit shown in FIG. 1 will be described with reference to FIG.

In FIG. 3, 31 is the waveform of the word line WD of FIG.
2 is a waveform of the logic signal line 13 connected to the capacitors C ₃ and C ₄ , 33 is a waveform of the memory cell node N ₁ , 34
Is a waveform of the memory cell node N ₂ , 35 is a waveform of the digit line DG, 36 is a waveform of the digit line ▴, and 37 is a write control signal waveform supplied from the outside. In FIG. 3, the address input changes at time t ₀ , and the word line selected at time t ₂ correspondingly changes to “H”. Further, at time t ₁ , the write control signal changes from “H” to “L”, and at the time t ₃ , the logic signal changes from “H” to “L” in response to the change from the read state to the write state. Further, at time t ₄ , write data appears on the digit line DG, ▲ ▼. Here, when the logic signal changes from “H” to “L” at time t ₃ , the level of the memory cell node N ₁ is the power supply.
The decrease from the (Vcc) level to Vcc-V _T is due to the coupling of the capacitor C ₃ . At the level of Vcc-V _T , the transfer gate MOSFET Q ₁ is turned on and the charge flows from the digit line, so that the level does not drop any more. Further, the level of the memory cell node N ₂ is also lowered by the coupling of the capacitor C ₄ , but
Since MOSFETs Q ₂ and Q ₄ are on, the amount of decrease is small. When data appears on the digit line at time t ₄ , the memory cell node N ₁ changes from “H” to “L” and N ₂ changes from “L” to “H”, and data is written in the memory cell. . At this time, the "H" level of N ₂ is V
only increased to cc-V _T. Next, when the write control signal changes from “L” to “H” at time t ₅ , time t ₆
Then, the logic signal changes from "L" to "H". When the logic signal changes from "L" to "H", the capacitor C4
Of the memory cell node N ₂ is quickly
Increase to cc level or higher. At this time, how much the level of N ₂ rises is determined by the capacitance of the capacitor C ₄ and the size of C ₁ . For example, now C ₁ = C ₄ =
If the power supply voltage is 5v at 0.01pF, the rise of the node N ₂ Is. Thus after the value of Vcc-V _T becomes "H" from the logic signal is "L" if 3.5 V is 3.5 V + 2.5v
= 6v and rises above the power supply voltage. But this 6
The voltage v is discharged through the resistor R ₂ and the power supply voltage 5v
Finally settles down.

〔The invention's effect〕

As described above, according to the present invention, one end is connected to the memory cell node and the other end is provided with the capacitor connected to the logic signal line to which the signal obtained by the logic of the write control signal and the word line signal is supplied. After the writing is completed, the "H" level of the memory cell quickly reaches the power supply level. Therefore, even if the memory cell area is made small, the malfunction due to the α ray can be suppressed to a large effect.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a static memory according to the present invention, FIG. 2 is a layout diagram of a memory cell portion of the circuit of FIG.
FIG. 3 is a waveform diagram showing the operation of the circuit of FIG. 1, FIG. 4 is a circuit diagram of a conventional static memory, and FIG.
It is an operation | movement waveform diagram of the circuit of the figure. Q ₁ ~Q _4: transistor

Claims (2)

[Claims] 1. In a static memory using a flip-flop having a high resistance element as a load element as a memory cell, one end is connected to a cross connection point of the flip-flops, and the other end is changed from a low level to a high level after a write operation is completed. A static memory having a capacitor to which a varying logic signal is applied. 2. A signal line to which the logic signal is supplied is arranged in parallel with the word line for each word line corresponding to each word line, and the logic signal is written at a high level in the word line and is written. The static memory according to claim (1), which is at a low level when in a state.