JPH06161875A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To accelerate the processing speed of an image processor. CONSTITUTION:This device is provided with a register circuit 9 for holding logical arithmetic information supplied from a CPU 200, a latch circuit 10 for latching first data from the CPU 200, an arithmetic logic circuit 11 for executing an arithmetic operation by the logical arithmetic information from the register circuit 9 for data from a memory cell array 1, a latch circuit 10 and a CPU 200, a switching circuit 12 for controlling the flow of data among the memory cell array 1, the CPU 200, the latch circuit 10, the register circuit 9 and arithmetic logic circuit 11, and an arithmetic control circuit 13 for controlling the respective parts by executing the arithmetic operation during one write cycle so as to store the data in the memory cell array 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to a RAM type semiconductor memory device used in an image processing apparatus.

[0002]

2. Description of the Related Art In an image processing apparatus, various image processing is performed on two figures each having a predetermined shape within one frame. For example, FIG.
As shown in (C), when clipping, that is, when the internal area of one graphic is limited to the internal area of another graphic, 2
An AND operation is performed on the data of one figure (see FIG. 7).
(A)) When showing all the internal areas of two figures,
An AND operation is performed on the data of these figures (FIG. 7B), and when the areas other than the areas shared by these figures are shown, the EX-
An OR operation is performed ((C) of FIG. 7).

As the image processing apparatus having such an arithmetic processing function, a RAM type semiconductor memory device for storing the data of each figure in frame units is used.

FIG. 8 shows a first example of a conventional semiconductor memory device used in such an image processing apparatus.

This semiconductor memory device 100a includes a memory cell array 1 in which dynamic memory cells are arranged in rows and columns to write data to and read data from a selected memory cell, and a row from a CPU 200a at a predetermined timing. An address buffer circuit 2 that takes in and outputs an address signal ADr and a column address signal ADc, a row selection circuit 3 that selects a row of the memory cell array 1 according to a row address signal ADr from this address buffer circuit 2, and an address buffer circuit 2 A column selection circuit 4 for selecting a column of the memory cell array 1 according to the column address signal ADc.
A sense amplifier circuit 5 for amplifying data read from each column of the memory cell array 1, and data from the memory cells of the memory cell array 1 selected by the row selection circuit 3 and the column selection circuit 4 to the CPU 200a. The data input / output circuit 6 for supplying the data from the memory cell to the selected memory cell and the dynamic memory cell of the memory cell array 1 are refreshed at a predetermined timing, and the operation of each part is controlled according to various control signals from the CPU 200a. The refresh address control circuit 7 and the control circuit 8 are provided.

Next, the operation of this semiconductor chrysanthemum device will be described. FIG. 9 is a timing chart of signals of respective parts for explaining the operation of the semiconductor memory device.

At the fall of the row address strobe signal RASb (hereinafter simply referred to as the RASb signal. B of RASb indicates that the low level is active. The same applies to other signals). Read as ADr. Then, after a predetermined time, the data of the address signal AD is switched to the column address ADc. After the address signal switches and stabilizes, C
The column address ADc is read at the fall of the ASb signal. After a lapse of a predetermined time after the fall of the CASb signal, the data of the memory cell at the selected address of the memory cell array 1 appears at the output terminal, and the data DT is changed to CP.
The U200a reads and performs a logical operation process with the operation data held by the CPU 200a. Then, the result of the logical operation processing is stored in the memory cell array 1 at the write cycle timing of the semiconductor memory device 100a.

Next, an example in which a static type memory cell is used will be described. FIG. 10 is a block diagram showing an example of a conventional static RAM type semiconductor memory device, and FIG. 11 is a timing diagram of signals of respective parts for explaining the operation.

This semiconductor memory device 100B is different from the above-mentioned dynamic type example in that it has a memory cell array 1a.
The memory cell is of a static type, the row address ADr and the column address ADc are separately input as the address signals, and the control signal from the CPU 200B is different.

Next, the operation of this semiconductor memory device will be described. When the CE1b signal and the CE2 signal are active, the OEb signal is activated to enable the buffer for the output data of the data input / output circuit 6a, and the data read from the memory cell array 1a is output from the output terminal through this buffer. The output data DT is read by the CPU 200B, and logical operation processing is performed with the operation data held in the CPU 200B. Then, the result of the logical operation is stored in the memory cell array 1a at the write cycle timing of the semiconductor memory device 100B. In this way, the semiconductor memory device 100
When a drawing process such as clipping of an arbitrary shape is performed using a, 100B, CPUs 200a, 200B
And the arbitrary data in the memory cell arrays 1 and 1a are logically operated, and the processing time is 2
It is the total time of the bus state and the logical operation processing time. For example, in the case of the read-modify-write mode, the read cycle + calculation time (CPU) + write cycle time is required, and when high speed is pursued,
It is necessary to speed up CPU processing performance and memory access time. However, it is difficult to extremely increase the access speed of the semiconductor memory device.
Now, when V20HL (μPD70108H) is used for the CPU, one clock is 62.5ns (16M
Hz), the data 0FH in the addressed memory is only bits 2 and 3, the operation data 08H and AN
When executing D, first load the data in memory to the accumulator with the MOV instruction, and then F3H in the register.
And OR of the operation data 08H are executed, and the result is ANDed with 0FH in the accumulator. And MO
The V instruction stores the result in the memory cell array. The operation speed is 10 clocks for MOV instruction, 9 clocks, O
Since R has 4 clocks and AND has 2 clocks, 25
It becomes a clock (1562.5 ns). As described above, it takes 33 clocks (2
062.5 ns) is required.

[0011]

In the conventional semiconductor memory device described above, the data read from the memory cell array is transmitted to the CPU, and the data processed by the CPU is stored in the memory cell array. Since a read cycle, a write cycle, and an arithmetic processing time are required for the CPU, there is a problem that the drawing processing time becomes long.

An object of the present invention is to provide a semiconductor memory device capable of shortening the drawing processing time.

[0013]

In a semiconductor memory device of the present invention, a plurality of memory cells are arranged, stored data is read from the selected memory cell and transmitted to a CPU, and the selected memory cell is supplied from the CPU. A memory cell array for storing the selected data, an address selection circuit for selecting a predetermined memory cell of the memory cell array according to an address signal from the CPU, and the memory cell array and an address selection circuit according to various control signals from the CPU. RA having a control circuit for controlling the operation of each unit
In an M-type semiconductor memory device, a register circuit for holding and outputting logical operation information of data supplied from the CPU, and a latch for latching and outputting first data of the data supplied from the CPU A circuit, a logical operation circuit for executing and outputting an operation between data read from the memory cell array, data from the CPU and data from the latch circuit in accordance with logical operation information from the register circuit, and the CPU Supply of data from the memory cell array to the memory cell array and supply to the logic operation circuit, register circuit, latch circuit, transfer of data from the memory cell array to the CPU and transfer to the logic operation circuit, And a switching circuit for controlling transmission of data from the logical operation circuit to the memory cell array, An operation control circuit for controlling operations of the register circuit, the latch circuit, the logical operation circuit and the switching circuit so that the operation is executed and stored in the memory cell array during one write cycle according to various control signals from the CPU; Is provided and configured.

[0014]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

This embodiment differs from the conventional semiconductor memory device shown in FIG. 8 in that the register circuit 9 for holding and outputting the logical operation information of the data DT supplied from the CPU 200 and the CPU 200 for supplying. Data DT
Circuit 1 for latching and outputting the first data of the
0, data read from the memory cell array 1 and CP
A logical operation circuit 11 that executes and outputs an operation of the data from the U200 and the data from the latch circuit 10 according to the logical operation information from the register circuit 9, and the supply of the data from the CPU 200 to the memory cell array 1 and the logical operation circuit 11 , Supply to the register circuit 9 and the latch circuit 10, transfer of data from the memory cell array 1 to the CPU 200 and transfer to the logical operation circuit 11, and transfer of data from the logical operation circuit 11 to the memory cell array 1. A switching circuit 12 for controlling transmission, a register circuit 9, a latch circuit 10, a logical operation circuit 11, and a logical operation circuit 11 so that the above operation is executed and stored in the memory cell array 1 during one write cycle in accordance with various control signals from the CPU 200. An arithmetic control circuit 13 for controlling the operation of the switching circuit 12 is provided. 2 shows a specific circuit example of the register circuit 9, and FIG. 3 shows a specific circuit example of the logical operation circuit 11.

Next, the operation of this embodiment will be described.
FIG. 4 is a timing chart of signals of respective parts for explaining the operation of this embodiment.

First, the address signal AD from the CPU 200
Is input and an address in the memory cell array 1 is designated. When the WEb signal 7 is set to the low level at the fall of the RASb signal, the data (D
TL) is held in the latch circuit 10. The data is further sent to logical operation circuit 11 to instruct the masking of a specific bit of the addressed and read data from memory cell array 1. Subsequently, the write data is read at the rising edge of the WEb signal and sent to the logical operation circuit 11. Then, the operation is executed in accordance with the logical operation information of these data selected by the register circuit 9,
The calculation result is stored in the designated address of the memory cell array 1. The above processing is executed in one write cycle.

FIG. 5 is a block diagram showing a second embodiment of the present invention. In this embodiment, the present invention is applied to the static RAM type semiconductor memory device 100B shown in FIG. 10, and a register circuit 9a, a latch circuit 10a, and a logical operation circuit having the same functions as those of the first embodiment. 11a, a switching circuit 12a, and an arithmetic control circuit 13a are provided.

Next, the operation of this embodiment will be described.
FIG. 6 is a timing chart of signals of respective parts for explaining the operation of this embodiment.

First, when the CE1b signal is at the low level and the CE2 signal is at the high level, the writable state is set. CPU20
Address signals (ADr, ADc) are input from 0A to specify an address in the memory cell array 1a. CE1
When the WEb signal is set to the low level at the fall of the b signal, the data input from the input / output terminal is latched by the latch circuit 10.
held in a. The data is further processed by the logical operation circuit 11
The mask of the specific bit of the data sent to the a and addressed and read from the memory cell array 1a is designated. Subsequently, the write data is read at the falling edge of the WEb signal and sent to the logical operation circuit 11a. Then, an operation is performed on both data by the logical operation information selected by the register circuit, and the operation result is stored in the specified address of the memory cell array 1a. The above processing is executed in one write cycle.

Here, the CPU is V20HL (μPD70
108H) and one clock is 62.5ns (16MH
z), the data 0FH in the addressed memory cell array is ANDed with 08H only in bits 2 and 3.
In the case of the present invention, processing can be performed in one write cycle (1 bus state), that is, 4 clocks (250 ns), and the processing time is significantly longer than that of the conventional example. Is shortened to.

[0023]

As described above, according to the present invention, a logical operation can be executed by itself at one write timing of the memory, so that the drawing processing speed such as clipping is increased in the image processing apparatus. There is an effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific circuit example of a register circuit of the embodiment shown in FIG.

FIG. 3 is a circuit diagram showing a specific circuit example of a logical operation circuit of the embodiment shown in FIG.

FIG. 4 is a timing chart of signals of respective parts for explaining the operation of the embodiment shown in FIG.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a timing chart of signals of respective parts for explaining the operation of the embodiment shown in FIG.

FIG. 7 is an image diagram for explaining the operation of an image processing apparatus in which a conventional semiconductor memory device is used.

FIG. 8 is a block diagram showing a first example of a conventional semiconductor memory device.

FIG. 9 is a timing chart of signals of respective parts for explaining the operation of the semiconductor memory device shown in FIG.

FIG. 10 is a block diagram showing a second example of a conventional semiconductor memory device.

FIG. 11 is a timing chart of signals of respective parts for explaining the operation of the semiconductor memory device shown in FIG.

[Explanation of symbols]

1, 1a Memory cell array 2 Address buffer circuit 3, 3a Row selection circuit 4, 4a Column selection circuit 5, 5a Sense amplification circuit 6, 6a Data input / output circuit 7 Refresh address control circuit 8, 8a Control circuit 9, 9a Register circuit 10 , 10a Latch circuit 11, 11a Logical operation circuit 12, 12a Switching circuit 13, 13a Operation control circuit 100, 100a, 100A, 100B Semiconductor memory device 200, 200a, 200A, 200B CPU

Claims (1)

[Claims] 1. A memory cell array in which a plurality of memory cells are arranged, stored data is read from the selected memory cell, transmitted to a CPU, and data supplied from the CPU is stored in the selected memory cell, and the CPU. RAM having an address selection circuit for selecting a predetermined memory cell of the memory cell array in accordance with an address signal from the memory cell array, and a control circuit for controlling the operation of each part including the memory cell array and the address selection circuit according to various control signals from the CPU. In a semiconductor memory device of the type
A register circuit for holding and outputting logical operation information of the data supplied from the CPU, a latch circuit for latching and outputting the first data of the data supplied from the CPU, and a read circuit from the memory cell array. A logical operation circuit that executes and outputs an operation between data, data from the CPU, and data from the latch circuit according to logical operation information from the register circuit, and supply of data from the CPU to the memory cell array And switching of supply to the logical operation circuit, register circuit, and latch circuit, transfer of data from the memory cell array to the CPU and switching to the logical operation circuit, and transfer of data from the logical operation circuit. A switching circuit for controlling the transmission to the memory cell array, and one-time operation according to various control signals from the CPU. A semiconductor memory including an arithmetic control circuit for controlling the operations of the register circuit, the latch circuit, the logical arithmetic circuit and the switching circuit so that the arithmetic operation is executed and stored in the memory cell array during a write cycle. apparatus.