JPH06161614A - Memory board device - Google Patents

Abstract

PURPOSE:To obtain a memory keyboard capable of selecting plural memory capacity and battery backup time with a kind of main printed board by constituting that the combinations of memory capacity and battery capacity can be changed according to the applications of a memory board. CONSTITUTION:The parts other than the memory control circuit/external bus interface circuit 103 and the power source switching circuit 104 on a main printed board 201 are divided into plural blocks S, S..., and are used for mounting a memory unit 101 or a battery unit 102. When they are used, arbitrary units 101, 102 are mounted on each block S according to preliminarily desired memory capacity and battery backup time. Then, when the information on the mounting states of the necessary units 101, 102 is set by a switching means, a memory control circuit (in 103) controls for decoding an address from a back board based on the setting information and making access to only the mounting part of the memory unit 101.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory board device, and more particularly to a memory board device having a function of backing up the contents stored in a storage means such as a volatile memory by an external battery power source when the main power source is cut off.

[0002]

2. Description of the Related Art Conventionally, as a memory board device for backing up, for example, a volatile memory by an external battery power source, JP-A-63-150716 and JP-A-3-3000.
As shown in Japanese Patent Laid-Open No. 1, a storage means such as a volatile memory is used by being fixed to a printed circuit board by soldering. FIG. 13 is a block diagram showing a conventional battery backup memory board. In the figure, 701 is a volatile memory for storing data, 102 is a battery unit for supplying power at the time of backing up the volatile memory, 103 is a control circuit and CPU for reading / writing the volatile memory. A control circuit such as an external bus interface circuit, 104 is a power supply switching circuit for switching the power supply of the volatile memory from the backboard during normal operation, and the power supply from the battery during backup, and 106b is the battery unit 102, A connection connector for connecting a main printed circuit board (not shown), 107 is a connected connector on the main printed circuit board side for connecting the battery unit 102 and the main printed circuit board, and 108 is a memory board and a main power source, etc. Connector for connecting the mounted backboard, 109 A diode for preventing backflow of power, 110 is a memory access bus including an address line, a data line and a control line for accessing the volatile memory, 111 is a memory power supply line for supplying power to the volatile memory, and 112 is A battery power supply line for supplying battery power at the time of backup, 113
Indicates a normal power supply line that normally supplies power from the backboard. The dotted line indicates the current path.

Next, the operation will be described. During normal times other than backup, power is supplied from the normal power supply line 113 to the volatile memory 701 and the memory power supply line 111 in the power supply switching circuit 104. When performing the backup operation, the battery connector 106b
The power supply switching circuit 104 switches the power supply to the volatile memory 701 and the memory power supply line 111 to the power supply from the battery unit 102 via the battery power supply line 112. As a result, even if the power supply from the backboard is cut off, the power is continuously supplied from the battery unit 102, and the backup operation of the volatile memory becomes possible.

[0004]

However, in the conventional memory board device, the volatile memory 701 is soldered on the printed circuit board in advance, and the capacity may be small but the backupable time is desired to be long. However, since it is impossible to attach and detach the memory, it was necessary to increase the capacity of the battery in order to extend the backup time. In this case, the unnecessary memory is backed up, and the battery charge is wasted. Further, if there is an unnecessary memory or an extra battery, there is a problem that the area occupied on the printed circuit board and the cost are increased.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to arbitrarily change the combination of the memory capacity and the battery capacity according to the application of the memory board so that one type of memory board can be used. An object of the present invention is to obtain a memory board device capable of selecting a plurality of memory capacities and battery backup times on a main printed circuit board.

[0006]

A memo board device according to claim 1 of the present invention comprises a normal power supply line 113 to which a main power is supplied from the outside, an external interface circuit provided on a main printed circuit board 201, Memory access bus 11 connected to a control circuit 103 such as a memory control circuit
0, a memory power supply line 111, a battery power supply line 112, a plurality of connected connectors 107 connected to the memory access bus, the memory power supply line, and the battery power supply line, and the plurality of connected connectors, respectively. Any one of the battery power supply line and the normal power supply line, and a memory unit 101 and a battery unit 102, one of which is connected to the connected connector via the connection connector. A power supply switching circuit 104 for switching and connecting one to a memory power supply line.

The memory board device according to claim 2 of the present invention further comprises an identification means (unit mounting state recognition circuit 301) for identifying which of the memory unit and the battery unit is connected to the connected connector. It is added to the configuration of 1.

[0008]

The memory unit and the battery unit are attached to the main printed circuit board according to the desired memory and battery capacity. The power supply switching circuit supplies the power supply of the battery unit to the memory unit when the main power supply is cut off.

The identifying means sends to the control circuit a signal indicating which of the memory unit and the battery unit is connected to the connected connector.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings. Example 1. FIG. 1 is a block diagram showing the configuration of the memory board device of this embodiment, and FIG. 2 is an external view. In each figure, 101 is a memory unit in which a volatile memory 101a is mounted on a printed circuit board 101b as a storage unit for storing data, and 102 is a battery 102a for supplying power when the volatile memory 101a is backed up.
A printed circuit board 1 having the same form as the memory unit 101
A battery unit mounted on the battery 02b; 103, a control circuit for reading / writing the volatile memory 101a; and a control circuit, such as an external bus interface circuit with the CPU, 104. A power supply from the board, a power supply switching circuit for switching to the power supply from the battery at the time of backup, 105 is a switch means for setting which of the memory unit 101 and the battery unit 102 is connected to each block S, S, 106a, Reference numerals 106b respectively denote connection connectors for connecting the memory unit 101, the battery unit 102 and the main printed circuit board 201, and have the same shape. 107 is also the memory unit 1
01 or battery unit 102 and main printed circuit board 2
01, the connected connector on the main printed circuit board side,
Reference numeral 108 denotes a connector for connecting a memory board device 210 to a backboard (not shown) equipped with a main power source and the like, 109 a diode for preventing backflow of the power source, and 110, an address line and a data line for accessing the volatile memory. , A memory access bus including a control line, 111 is a memory power supply line for supplying power to the volatile memory, 11
Reference numeral 2 indicates a battery power supply line that supplies battery power during backup, and 113 indicates a normal power supply line that supplies power from the backboard during normal operation. The dotted line indicates the current path.

Next, the operation of the first embodiment will be described. As shown in FIG. 2, the present memory board device includes a plurality of blocks S, S, ... On the main printed circuit board 201 except for the memory control circuit / external bus interface circuit (control circuit 103) and the power supply switching circuit 104. .., and is used for mounting the memory unit 101 or the battery unit 102. When using, the memory unit 101 or the battery unit 102 is optionally mounted in each block S in accordance with a desired memory capacity and battery backup time in advance. At that time, if a large amount of memory capacity is required and only a short backup time is required, one battery unit may be used for all the remaining memory units. Conversely, if the memory capacity is not required so much and a long backup time is desired, the memory unit 1 All the remaining battery units may be used. Next, the memory unit 1 required in the memory control circuit (in 103)
01 and the mounting state information of the battery unit 102 is set by the switch means 105 shown in FIG. The memory control circuit decodes the address from the backboard based on the setting information and controls so as to access only the mounted portion of the memory unit 101. As the switch means 105, assuming that there are eight blocks S, for example, a DIP type switch (8bi) as shown in FIG.
t) 105a and, for example, as shown in FIG.
Set 5b. In this case, the bit of the switch 105a
0 to 7 correspond to each block, and only the bits corresponding to the blocks in which the unit is mounted are set to “ON”. By entering the setting information from the switch 105a into the memory address decoding condition, control is performed so that only the portion where the unit is mounted is accessed. By providing the switch 105a for the memory unit and the switch for the battery unit, it is possible to set the mounting type and state information of each unit.

The power supplied to the memory unit 101 is normally supplied from the normal power supply line 110 supplied from the backboard through the backflow prevention diode 109 and the power supply switching circuit 104. When the main power supply is cut off and battery backup is performed, the power supply switching circuit 104 is switched so that the power supplied to the memory unit is supplied from the battery unit 102 to the backflow prevention diode 109 and the power supply switching circuit 104.
Supplied through. At that time, when a plurality of battery units 102 are connected, the charge is supplied from each, so that the battery backup time can be lengthened. In other words, if you need a large amount of memory but not a lot of backup time, or if you do not need a large amount of memory but want to take a lot of backup time, you can freely use the memory and battery according to your application. The mounting configuration of can be changed.

Example 2. In the configuration of the first embodiment, the switch means 105 must be reset every time the combination of the memory unit 101 and the battery unit 102 is changed. In such a case, as shown in FIG. 4, a configuration in which a means for automatically recognizing the mounted states of the memory unit 101 and the battery unit 102 is provided can be considered. FIG. 4 is a block diagram of the memory board device according to the second embodiment, in which 301 is a unit mounting state recognition circuit as an identifying means, and 302 is a unit mounting state information line for transmitting the information. Other 101-104, 106a, 1
06b and 107 to 113 are the same as those in FIG. 1 described in the first embodiment.

FIG. 5 shows the memory unit 101, the battery unit 102 and the main printed circuit board 2 of this embodiment.
It is the figure which showed the detail of the connector which connects 01 and. Among the pins of the connectors 106a, 106b and 107 are a memory access bus 110 and a memory power supply line 11
1, a battery power supply line 112, a common ground line 403 on the board, a memory unit selection signal line 401 that becomes significant when a memory unit is connected, and a battery unit selection signal that becomes significant when a battery unit is connected Line 402 is connected. Here, 1a to 6a,
Reference numerals 1b to 6b denote pins in a connector for connecting the memory unit 101 or the battery unit 102 to the main printed circuit board 201, and 1a and 1b, 2a and 2b, ...
Contact each other. A plurality of signal lines are connected except the memory unit selection signal line 401 and the battery unit selection signal line 402. Selection signal lines 401 and 402
Becomes the above-mentioned information line 302.

Next, the operation of this embodiment will be described. When this memory board device is used, as in the first embodiment,
The memory unit 101 or the battery unit 102 is mounted on the main printed board 201 according to the application. At that time, by the circuit shown in FIG. 5 (in this case, from the power source P via the pull-up resistors 404a and 404b, the signal line 40 is
The circuit 301a connected to 1, 402 serves as a unit mounting state recognition circuit for one block. ), If the memory unit 101 is connected to the connector 107, the pull-up resistor 4
04a makes the memory unit selection line 401 significant (L level), and when the battery unit 102 is connected to the connector 107, the pull-up resistor 404b makes the battery unit selection line 402 significant (L level).
These pieces of information are sent to the respective signal lines 401 or 402.
Through the memory control circuit. Then, the information is used for address decoding at the time of memory access.

Next, a specific example of using the signals on the signal lines 401 and 402 for address decoding and the like will be described. For example, the maximum installed memory capacity of this memory board device is 32
Assuming that MB (4 MB × 8), by the memory-mounted information line 8 bit (00 _{H to} FF _H ) of the memory board (here,
This information line is logically inverted and, if connected, H (=
1), which is represented by two hexadecimal digits (= A). ), The memory space is mapped by the CPU connected to the external bus as follows. When one memory unit is connected (A = 01 _H , 02 _H ,
04 _H , 08 _H , 10 _H , 20 _H , 40 _H , 80 _H ),
The memory space M1 shown in FIG. 6 is mapped on the memory space M. If the memory unit 2 connected _{(A = 03 H, 06 H} ,
For _{0C H, 30 H, 60 H} , C0 H), in the memory space M, the memory space M2 shown in FIG. 7 is mapped. Similarly, when three to eight memory units are connected, the address X is determined by the information A (the final address determined by the number of previous connections, for example, in the case of two connections (BASE + 3
FFFFF)) is continuously mapped.

Next, in the present memory board device, the signal group (= A) of 401 is used as follows (here, the memory element uses a 4 Mbit (1 Mword × 4 bit) DRAM, and eight (8) per unit ( Data 32 bits) shall be used). As shown in FIG. 8, the lower 22 bit address (000000 _{H to} 3FFFFF _H ) goes to the connector of all units as it is, but the upper 10 bit is RAS /
Used for CAS generation conditions (only RAS may be controlled). For example, if eight RAS signals are set to RAS0 to RAS7 and correspond to the unit connectors 1 to 8, respectively, the condition of RAS0 and RAS is: RAS0 = (address <31 ... 22> = BASE)
& (A1 = [X, X, X, X, X, X, X, 1]) (where “X” = arbitrary) → This memory board device is selected and the memory unit is connected to the connector 1. When RAS1 = (address <31 ... 22> = BASE)
& (A1 = [X, X, X, X, X, X, 1, X]) → This memory board device is selected, and the memory unit is connected to the connector 2. Also CAS
The same is true for.

Example 3. As described above, when the main printed circuit board is mounted on the backboard on which the plurality of boards are mounted, it may not be possible to confirm the mounting state of the memory unit and the battery unit from the outside. In such a case, as shown in FIGS. 9 to 11, the mounted state of the memory unit 101 and the battery unit 102 is set to LE.
Use display means such as D so that it can be confirmed from the outside. FIG. 9 shows a block diagram of this embodiment, FIG. 10 shows an example of the unit mounting state display means, and FIG. 11 shows an example of the display means drive circuit. In FIG. 9, reference numeral 501 indicates a memory unit mounting state display means, and 502 indicates a battery unit mounting state display means. Other 101-105, 106a,
Reference numerals 106b and 107 to 113 are the same as those in FIG. 1 described in the first embodiment.

FIG. 10 shows an example of the memory unit display means 501 and the battery unit display means 502 of this embodiment. In this example, it is assumed that the block S in which the memory unit 101 or the battery unit 102 is mounted is divided into eight, and the capacity of one memory unit is 4 MByte. Therefore, as shown in FIG.
By using the LEDs 501a and 502a and installing them on the front surface of the main printed board 201, it is possible to display the total memory capacity and the number of connected battery units of the present memory board. For example, of the 8 blocks,
When four memory units and two battery units are mounted, the memory unit mounting state display unit 501 is
The LED at 6 MB and the battery unit mounting state display means 502 turn on the LED at 2. If the display means is composed of a simple LED as shown in FIG. 10, an output signal 8bi from the switch is generated by a circuit as shown in FIG.
It is sufficient to decode t (= A). That is, in each of the LEDs 1, LED 2, ..., One of the signals of A is "H", two of which are "H", ..., 7 of which are "H", and all of them are "H". LED1-8 when
It suffices to construct a combination circuit so that any of the above lights up and decode it. Further, a circuit for displaying the number of connected battery units can be similarly configured. According to the present embodiment, even if the present memory board device is mounted on the same backboard as a plurality of other boards, the mounted states of the memory unit and the battery unit can be confirmed from the outside.

Example 4. The power supply switching circuit 104
In order to perform the automatic switching of the power source, the voltage of the main power source appearing on the normal power supply line 113 is detected by the main power source detecting means 40, and the power source switching circuit is switched by the switching control means 41 based on the detection result. You may comprise so that 104 may be switched. With such a configuration, when the power supply from the power supply means is stopped, the connector 108 is pulled out from the external device, or the like, the voltage appearing on the normal power supply line 113 drops, and the power supply is reduced based on this voltage drop. Since the switching circuit 104 switches the switching contact 104a from the normal power supply line 113 side to the battery power supply line 112 side, the backup voltage from the battery power supply line 112 side is automatically supplied to the memory power supply line 111. According to this embodiment, the power supply switching circuit 104 can be automatically switched.

Although a volatile memory is used as an example of the storage means in the above embodiment, a storage means such as a register circuit using a flip-flop for battery backup may be mounted as a memory unit.

[0022]

According to the memory board device of the first aspect of the present invention, the normal power supply line to which the main power is externally supplied, the external interface circuit and the memory control circuit provided on the main printed circuit board, etc. are provided. A memory access bus connected to the control circuit, a memory power supply line, a battery power supply line, a plurality of connected connectors connected to the memory access bus, the memory power supply line, and the battery power supply line, respectively. A memory unit and a battery unit which have a connection connector connectable to a plurality of connected connectors, and one of which is connected to the connected connector via the connection connector, the battery power supply line and the normal power supply line And a power supply switching circuit for switching and connecting one of the two to a memory power supply line, and a memory for storing data. The unit and the battery unit for supplying backup power are mounted on a different printed circuit board from the main printed circuit board on which the memory control circuit etc. are mounted, and the main printed circuit board is connected via a connector for connecting to each main printed circuit board. Since the attachment / detachment to / from the substrate is made possible arbitrarily, there is an effect that the memory capacity and the battery backup time can be selected by freely changing the mounting configuration of the memory unit and the battery unit according to the application.

According to a second aspect of the memory board device of the present invention, in addition to the configuration of the first aspect, identification means for identifying which of the memory unit and the battery unit is connected to the connected connector is provided. Since it is provided, it is possible to reliably set the mounting states of the memory unit and the battery unit without using the switch means or the like. Further, by decoding the signal from the identification means and displaying the mounting state on the display means separately, there is an effect that the type of the unit and the mounting state can be confirmed from the outside.

[Brief description of drawings]

FIG. 1 is a block diagram showing a memory board device according to a first embodiment of the present invention.

FIG. 2 is an external view showing a memory board device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing an example of a switch unit according to the first exemplary embodiment of the present invention.

FIG. 4 is a block diagram showing a memory board device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing details of a connector for connecting a memory unit and a battery unit of a memory board device according to a second embodiment of the present invention to a main printed circuit board.

FIG. 6 is a diagram showing an example of a memory space mapped by a signal of a selection signal line.

FIG. 7 is a diagram showing an example of a memory space mapped by a signal of a selection signal line.

FIG. 8 is a diagram illustrating a usage example of a signal of a selection signal line in a memory board device.

FIG. 9 is a block diagram showing a memory board device according to a third embodiment of the present invention.

FIG. 10 is a diagram showing an example of display means for displaying the mounted states of a memory unit and a battery unit of a memory board device according to a third embodiment of the present invention.

FIG. 11 is a diagram showing an example of a display unit drive circuit.

FIG. 12 is a principal block diagram showing a memory board device according to a fourth embodiment of the present invention.

FIG. 13 is a block diagram showing a conventional memory board device.

[Explanation of symbols]

 101 memory unit 102 battery unit 103 control circuit 104 power supply switching circuit 105 switch means 106a memory unit connection connector 106b battery unit connection connector 107 main printed circuit board side unit connected connector 108 backboard connection connector 109 power supply backflow prevention diode 110 memory access Bus 111 Memory power supply line 112 Battery power supply line 113 Normal power supply line 201 Main printed circuit board 301 Unit mounting state recognition circuit (identifying means) 302 Unit mounting state information line 401 Memory unit selection signal line 402 Battery unit selection signal line

Claims (2)

[Claims] 1. A normal power supply line to which main power is externally supplied, a memory access bus connected to a control circuit such as an external interface circuit or a memory control circuit provided on a main printed circuit board, and a memory power supply. A line, a battery power supply line, a plurality of connected connectors connected to the memory access bus, the memory power supply line, and the battery power supply line, and connection connectors connectable to the plurality of connected connectors, respectively. , A power supply for switching and connecting one of the battery power supply line and the normal power supply line to a memory power supply line, and a memory unit and a battery unit, one of which is connected to the connected connector via this connection connector A memory board device comprising a switching circuit. 2. The memory board device according to claim 1, wherein the connected connector is provided with identification means for identifying which of the memory unit and the battery unit is connected.