JPH06161379A - Driving circuit of display device - Google Patents

Abstract

PURPOSE:To reduce the operation speed of shift registers by using plural shift registers and to make a display of high resolution without deforming the waveform of a video signal. CONSTITUTION:The shift registers 11-14 output such signals that successive periods of a high level overlap with each other and also deviate. Consequently, the shift registers 11-14 can be placed in low-speed operation. Further, control signals generating means 51, 52... output active control signals in a period wherein one of the signals SR1, SR2... from the shift registers 11-14 and another signal having a high level in a period overlapping with a high-level period of the signal have the high level at the same time. Switch means 21, 22... are turned ON and OFF according to the control signals. Periods of conduction are shortened and loads of sampling capacitors 41, 42... on a video signal electric conductor 30 is reducible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device driving circuit for outputting a video signal to a data signal line in a display device such as an active matrix liquid crystal display device.

[0002]

2. Description of the Related Art The above active matrix type liquid crystal display device performs display by driving pixels formed in a matrix by switching elements such as thin film transistors. As a conventional active matrix type liquid crystal display device, a display section in which pixels are formed, and a data signal line drive circuit for driving the pixels (hereinafter referred to as “source driver”).
Called. A driver monolithic display device in which (1) and (2) are formed on the same substrate is known. In this driver monolithic display device, the switching element of the pixel and the source driver are manufactured in the same process in the manufacturing process. Therefore, it is desirable that the switching element of the pixel and the element forming the source driver have the same structure. In the transmissive display device, the switching element has to be formed on a transparent substrate such as quartz glass by a thin film process, while the element constituting the source driver must have a required operation speed. For these reasons, a polycrystalline silicon thin film transistor (hereinafter, referred to as “polysilicon TFT”) is usually used as an element forming a pixel switching element and a source driver.

The mobility of this polysilicon TFT is approximately 10 to 100 cm ² / V · s, and the operating speed at the limit of stable operation in a shift register formed using the polysilicon TFT is currently The maximum is about several MHz. However, a display device having a large number of pixels, for example, an NTSC-T having 720 horizontal pixels.
V (National Television System Committee televisio
n) In the display, the shift register constituting the source driver is required to have an operating speed of 14.4 MHz. Therefore, a source driver in which the operating speed of the shift register is slowed is used.

FIG. 7 shows a configuration diagram of a source driver in which the operating speed of the shift register is reduced. This source driver is, as shown in the figure, a four-system shift register 1
1 to 14 and sampling analog switches 21, 22 ... Controlled by the shift registers 11 to 14 for opening and closing,
It is composed of a video signal wiring 30 to which the video signal Video is sent and sampling capacitors 41, 42, ... Connected to the video signal wiring 30 via the switches 21, 22 ,. The data signal lines S1, S2, ... Connected to pixels (not shown) are branched and connected between the switches 21, 22, ... And the sampling capacitors 41, 42 ,. The data signal lines S1, S2, ... Are set to four continuous lines, for example, S1, S2, S3 and S4,
Connected to switches 21, 22, ... Controlled by different shift registers 11 to 14, respectively. In detail, every three shift registers 11 have data signal lines S1, S5,
, And the shift register 12 is connected to the data signal lines S2, S6 ,. Similarly, the shift registers 13 and 14 are connected to the data signal lines S3, S4, ... Every three lines.

In the above structure, the switches 21, 22,
Is a video signal Vid applied to the video signal line 30.
It is for sampling eo. The sampling capacitors 41, 42, ... Hold the sampled video signal Video.

The operation of the source driver will be described with reference to the time chart shown in FIG. The activation of the shift registers 11 to 14 of the four systems is performed by each shift register 11 to 1
4 is controlled by a shift start pulse SP common to the four. The shift registers 11, 12, 13, and 14 have a shift clock φ1 and an inverted signal φ1 bar thereof having different phases,
It is controlled by φ2 and its inverted signal φ2 bar, φ3 and its inverted signal φ3 bar, φ4 and its inverted signal φ4 bar. Adjacent sampling analog switches 21 and 2
The shift clocks .phi.1 to .phi.4 and .phi.1 to .phi.4 bar corresponding to 2, ... Are out of phase with each other by a time width of 1/8 of the shift pulse width .tau.0. As a result, the sampling switch control signals SR1, SR2, ...
The waveform has a phase shift of 1/8 of the time width. The switches 21, 22, ... Are sampling switch control signals S.
R1 and SR2 ... Conduct during the high level period. The video signal Video is sampled by the sampling capacitors 41, 42, ... During the period .tau.0 during which the switches 21, 22 ,. However, what is actually held in the sampling capacitors 41, 42, ... Is the switch 21,
22 ... are the voltages of the video signal Video held at the time of switching from ON to OFF.

Since it operates as described above, even if the time difference between the control signals SR1, SR2 ... In the source driver is made the same as in the case of the source driver having only one system of shift register, The shift pulse width τ0 in the source driver can be set to four times the shift pulse width of the source driver having a shift register of only one system, and the shift registers 11 to 14 of each system are provided.
Can be operated at low speed.

[0008]

By the way, as described above, the sampling switch control signals SR which are arranged one behind the other are provided.
The high level periods of 1, SR2, ... Are overlapping with each other. Therefore, for example, eight control signals S
R1 to SR8 are simultaneously active, and the eight sampling switches 21 to 28 are simultaneously turned on. That is, the video signal Video is eight switches 21.
8 to 8 sampling capacitors 41 to 4
8 is supplied. This is the eight control signals SR2-S.
The same applies to R9, and as a result, the video signal wiring 30,
Alternatively, for the circuit section that outputs the video signal Video, eight sampling capacitors 41, 42,
The capacity becomes the load. Furthermore, since the wiring resistance of the video signal wiring 30 exists, the RC integrating circuit is configured. Therefore, the sampling capacitors 41, 4
In case of 2, ..., the response to the video signal Video deteriorates due to the action of the RC integration circuit, and the original video signal Video
The waveform is distorted compared to. Since the band information originally possessed by the video signal Video is lost at the input section of the liquid crystal display device, the signal having such a distorted waveform is lost in the video display based on the signal having the distorted waveform.
There is a problem that the horizontal resolution becomes low.

The present invention has been made to solve the above-mentioned problems of the prior art. The operation speed of the shift register is reduced by using a plurality of systems of shift registers, and
High horizontal resolution without breaking the waveform of the video signal,
An object of the present invention is to provide a driver circuit for a display device capable of performing display using a driver monolithic liquid crystal display device.

[0010]

According to a drive circuit of a display device of the present invention, in a drive circuit of a display device which outputs a video signal to a data line, a part of a period in which signals which are in succession are at a high level is overlapped with each other. , A plurality of systems of shift registers that shift and output the periods, one of the signals from the shift register, and another signal having a high-level period that overlaps the high-level period of the one signal Control signal generating means for outputting a control signal that activates a period in which the one signal and the other signal are simultaneously at a high level, and a switch means for controlling ON / OFF based on the control signal. And a sampling capacitor for sampling the video signal via the switch means, thereby achieving the above object.

[0011]

In the drive circuit of the display device of the present invention, a plurality of systems of shift registers cause signals of which high periods are overlapped and which are shifted from each other. Therefore, the shift register can be operated at a low speed similar to the conventional one.

Further, between one signal of the signals from the shift register and another signal having a high level period which overlaps with the high level period of the one signal, the one signal and the other signal. The control signal generating means outputs a control signal that activates during a period when and are simultaneously at the high level. The switch means is turned on based on the control signal.
/ OFF control, the period of conduction becomes shorter than before,
Therefore, the number of switch means which are simultaneously turned on is reduced, and the load of the sampling capacitor on the wiring for transmitting the video signal is reduced.

[0013]

EXAMPLES The present invention will be described below with reference to examples.

FIG. 1 shows a block diagram of a source driver to which the present invention is applied. The same components as those of the conventional source driver shown in FIG. 7 are designated by the same reference numerals.

As shown in the figure, the source driver of this embodiment includes four systems of shift registers 11-14, sampling analog switches 21, 22 ... Which are controlled to open / close by the shift registers 11-14, and the shift register 11. ~
14 provided between the switch 14 and the switches 21, 22, ..., The video signal wiring 30 to which the video signal Video is sent, and the video signal wiring 30 via the switches 21, 22 ,. , And sampling capacitors 41, 42, ... The data signal lines S1, S2, ... Connected to pixels not shown are
The switches 21, 22, ... And the sampling capacitor 4
1, 42, ... Are branched and connected. The data signal lines S1, S2, ... Have four continuous lines, for example, S1,
One set of S2, S3, and S4 is connected to switches 21, 22, ... Controlled by different shift registers 11-14. In detail, every three shift registers 11 are connected to the data signal lines S1, S5, S9, ...
In addition, the shift register 12 has data signal lines S2 every three lines.
It is connected to S6, .... Shift registers 13 and 14
Similarly, every three data signal lines S3, S
4 ...

In the above structure, the switches 21, 22,
… Is an NMOS (N-channel metal oxide semiconducto)
r) for sampling the video signal Video applied to the video signal line 30. The sampling capacitors 41, 42, ... Hold the sampled video signal Video. The control signal generating means 51, 52, ... Is composed of NAND gates 51a, 52a, .. and inverters 51b, 52b ,. NA
The ND gates 51a, 52a, ...
Two output signals 1 to 14 are input, and the output signals of the inverters 51b, 52b, ...
2, ... is controlled.

2 and 3 are circuit diagrams of the shift registers 11 to 14 used in the source driver. In the clocked inverters in the figure, the types of signals for controlling the clocked inverters are added. The four systems of shift registers 11 to 14 have the same circuit configuration, and are circuits in which an inverter and a clocked inverter are combined as shown in FIG. The circuit configuration of the shift registers 11 to 14 may be a circuit configuration compatible with bidirectional shift, as shown in FIG.

FIG. 4 shows a time chart in the shift registers 11-14. Shift registers 11 to 1
4 is controlled by the shift start pulse SP, the shift clock φi and its inverted signal φi, as shown in the figure. As a result, the shift registers 11 to 14 sequentially output shift pulses having a pulse width τ0, as indicated by the signals O1, O2, ....

In the bidirectional shift registers 11 to 14 shown in FIG. 3, the shift direction setting signal R,
The shift direction is controlled based on L. When the signal R is at a high level and the signal L is at a low level, the clocked inverter controlled by the signal R always outputs an inverted signal, and the clocked inverter controlled by the signal L always outputs. It becomes a high impedance and becomes a shift register that shifts from left to right in the drawing. When the signal R is at the low level and the signal L is at the high level, on the contrary, the shift register shifts from the right direction to the left direction in the drawing. However, the operation for the shift clocks φi, φi bar may be considered in the same manner as the case of the shift registers 11 to 14 shown in FIG. 2, and in the time chart shown in FIG. This is applicable when the signal L is at low level.

FIG. 5 shows a time chart when the source driver of this embodiment is driven. The operation of the source driver will be described with reference to FIG.

The activation of the four shift registers 11 to 14 is controlled by the shift start pulse SP, as described above. The shift start pulse SP may be a signal common to each shift register 11-14. The shift registers 11, 12, 13, 14 are controlled by shift clocks φ1 and their inverted signals φ1 bar, φ2 and their inverted signals φ2 bar, φ3 and their inverted signals φ3 bar, φ4 and their inverted signals φ4 bar, which have different phases. It
The shift clocks φ1 to φ4 and φ1 bar to φ4 bar corresponding to the adjacent sampling analog switches 21, 22, ... Are respectively phase-shifted by a time width of ⅛ of the shift pulse width τ0. As a result, the shift registers 11 to 11
In the 14 output signals SR1, SR2, ..., The signals output to the adjacent control signal generating means 51, 52 ,.
For example, as seen in SR1 and SR2 shown in FIG. 5, the waveforms are out of phase by the time width of 1/8 of the shift pulse width τ0. The output signals O1, O2, ... Of the shift registers 11-14 shown in FIG. 4 are the output signals SR1, SR2 of the shift registers 11-14 shown in FIG.
..., every third signal, for example, SR1, SR5,
It corresponds to SR9, ....

In the source driver of this embodiment, the output signals SR1, SR2, ... Of the shift registers 11-14 are ...
Output signal SRj (j is an integer of 1 or more)
, And the signal SRj + 7, which is seven signals after the output signal SRj, are input to the NAND gates 51a, 52a, ... And the inverted signal Saj of the logical product of them is obtained. This NAND gate 51
Output signals Sa1 bar, Sa2 bar, ...
Is input to the inverters 51b, 52b, ...
The signal Sa as the output of the inverters 51b, 52b, ...
, 1, Sa2, ... The output signals Sa1, Sa2,
, Are input to sampling analog switches 21, 22, ... Formed by NMOS to control ON / OFF.
When turned on, the switches 21, 22, ... Are made conductive, and the sampling capacitors 41, 42, ... Connected to the switches 21, 22, ... Are charged to the voltage of the video signal Video. After that, the sampling capacitors 41, 42, ...
, The corresponding switches 21, 22, ... From ON to OFF
The voltage level of the video signal Video at the time of switching to is held as it is. This held voltage becomes an input signal to the data signal lines S1, S2, ... Of the liquid crystal display device.

In the source driver which operates as described above, the sampling analog switches 21, 22, ...
The signals Sa1, Sa2, ... That control the signals are signals having a pulse width of ⅛τ0 as shown in the time chart of FIG. 5 by the control signal generating means 51, 52 ,. Therefore, two or more sampling analog switches 21, 22, ... Do not conduct at the same time, and the load on the video signal wiring 30 is always the capacitance of only one sampling capacitor 41, 42 ,.

In the above-mentioned conventional example, the output signals SR1, SR2, ... Of the shift registers 11-14 turn ON / OFF the sampling analog switches 21, 22 ,.
It controls F. As a result, the capacity of the eight sampling capacitors 41, 42, ...
Has become a load against. On the other hand, in the source driver of this embodiment, the load on the video signal wiring 30 is one sampling capacitor 4 as described above.
Since they are 1, 42, ..., The RC time constant is also 1/8 of the conventional value. Therefore, the video signal V generated by the action of the RC integrating circuit
Waveform distortion (waveform rounding) of video can be suppressed smaller than before, and display with high horizontal resolution can be performed.

In the above embodiment, the control signal generating means 5
, And NAND gates 51a, 52a, ... And inverters 51b, 52 instead of AND gates
b, ... are used for the NAND gates 51a, 52
If a ..., CMOS (Complementary metal oxide)
This is because it can be easily configured by a semiconductor) structure. The control signal generating means 51, 52, ... Are not limited to the above-described embodiment, and other methods such as a method of taking the NOR of the inverted signal may be used as long as they can obtain a logical product.

Sampling analog switches 21, 2
Regarding the configurations of 2, ..., In addition to the above-mentioned embodiment, the configuration shown in FIG. 6 may be adopted. The switch 21 shown in FIG.
22, ... Are composed of CMOS, and the inverter 5
.. and NA of the output signals Sa1, Sa2 ,.
The output signal Sa1 bar of the ND gates 51a, 52a, ...
Sa2 bar is used together. Of course, the switches 21, 22, ... Are connected to PMOS (P-channel metal oxide se
miconductor).

In the above embodiment, the shift register 1
Although four systems of 1 to 14 are provided, the present invention can be applied to any source driver having shift registers of two or more systems. Further, in the control signal generating means 51, 52, ... Of the above embodiment, a certain output signal S of the output signals SR1, SR2 ,.
The signal to be ANDed with Rj may be any signal that has a period in which it is active at the same time as its output signal SRj, and may be, for example, the output signal SRj + 6 after six lines. Thus, the signals SRj and SRj + 6
, The two sampling analog switches 21, 22, ... Are always turned on at the same time. However, the number is smaller than that of the conventional example, and the effect of improving the horizontal resolution can be expected.

[0028]

As is apparent from the above description, according to the drive circuit of the display device of the present invention, the operation speed of the shift register is reduced by the shift registers of a plurality of systems, and the waveform of the video signal is not destroyed. Display using a driver monolithic liquid crystal display device with high horizontal resolution can be performed.

[Brief description of drawings]

FIG. 1 is a structural diagram of a source driver that is an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an internal configuration of a shift register used in the source driver shown in FIG.

FIG. 3 is a circuit diagram showing an internal configuration of a bidirectional shift-compatible shift register used in the source driver shown in FIG.

FIG. 4 is a time chart showing the operation of the shift register shown in FIG.

5 is a time chart showing the operation of the source driver shown in FIG. 1. FIG.

6 is a circuit diagram in the case where a sampling analog switch used in the source driver shown in FIG. 1 is configured by CMOS.

FIG. 7 is a configuration diagram of a conventional source driver.

FIG. 8 is a time chart showing the operation of the conventional source driver shown in FIG.

[Explanation of symbols]

 11-14 Shift register 21, 22, ... Sampling analog switch 30 Video signal wiring 41, 42, ... Sampling capacitor 51, 52, ... Control signal generating means 51a, 52a, ... NAND gate 51b, 52b, ... Inverter

Claims (1)

[Claims] 1. A drive circuit of a display device for outputting a video signal to a data line, comprising: a plurality of systems of shift registers for overlapping a part of a high-level period of successive signals and outputting the shifted period of the signals. Between the one signal of the signals from the shift register and another signal having a high-level period overlapping with the high-level period of the one signal, the one signal and the other signal are At the same time, a control signal generating means that outputs a control signal that activates a high-level period, a switch means whose ON / OFF is controlled based on the control signal, and a sampling of the video signal via the switch means And a driving circuit of a display device including a sampling capacitor.