JPH06160480A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form a scan bus having no problem of a clock skew merely by continuously laying out input/output circuit cells in input/output circuit regions at a periphery of a chip by incorporating a boundary scan register and a data ring in the respective cells. CONSTITUTION:A boundary scan register 42 and a boundary scan data ring 44 are contained in input/output circuit cells 40, and a scan bus is formed merely by continuously disposing the cells 40 on input/output circuit regions 20 at a periphery of a chip. Accordingly, it is not necessary to assemble the register 42 in a user circuit region 10, and a system design of a user circuit can be performed without being conscious of a presence of the register 42. Further, the registers 42 can be regularly laid out without special layout.wiring, and a scan bus having no problem of a clock skew can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit incorporating a boundary scan register for forming a scan path near an input / output pin during a test,
In particular, the present invention relates to a semiconductor integrated circuit in which a scan path can be formed by simply arranging input / output circuit cells continuously in an input / output circuit area around a chip without being aware of clock skew.

[0002]

2. Description of the Related Art A semiconductor integrated circuit is provided with a scan path in the vicinity of an input / output pin at the time of testing in order to compensate for testability and allow the use of an inspection tool for automatically generating a test pattern. There is a built-in boundary scan register for this purpose.

A semiconductor integrated circuit incorporating such a boundary scan register has been conventionally
A dedicated gate cell (boundary scan cell) having a built-in scan register is designed, and the same layout / wiring method is used in the same user circuit area 10 as the system circuit 12 as in the chip layouts shown in FIGS. 1 and 2. Was built in. In FIG. 1 and FIG. 2, 14 is a boundary scan register, and 16 is a boundary scan register.
A data line, 20 is an input / output circuit area in which an input buffer circuit 22 and an output buffer circuit 24 are arranged, and 30 is
A power supply ring 32 arranged in the input / output circuit area 20;
A power ring region including 34.

On the other hand, conventionally, the maximum operating speed of a circuit incorporated in a semiconductor integrated circuit has been estimated by a circuit simulation or the like based on data in a standard process. or,
At the stage where the semiconductor integrated circuit is manufactured, while measuring the actual operating speed while actually operating the incorporated circuit, by estimating the maximum operating speed and comparing the measured actual operating speed, The degree of variation in operating speed due to the manufacturing process was evaluated.

When estimating the maximum operating speed and measuring the actual operating speed, attention is paid not to the entire circuit incorporated in the semiconductor integrated circuit but to a part of the circuit, and the measurement work is performed. The efficiency is being improved. Further, by incorporating a dedicated circuit suitable for such estimation and measurement into the semiconductor integrated circuit to be measured, the efficiency of such measurement work is improved.

[0006]

However, in the conventional method of arranging the boundary scan register 14 in the user circuit area 10, the boundary scan register exists when the system circuit 12 is designed. The design is complicated because it must be consciously designed. Further, since the arrangement position of the boundary scan register 14 is not always constant, the arrangement and wiring must be performed in consideration of the clock skew, and there is a problem that the design is more complicated.

On the other hand, the estimation of the maximum operating speed by the circuit simulation as described above has a problem in measurement accuracy. This is because the accuracy of estimating the wiring length of the circuit under test incorporated in the semiconductor integrated circuit is not sufficient.

In addition, in estimating the maximum operating speed by the circuit simulation as described above, or by measuring the actual operating speed of the manufactured semiconductor integrated circuit as described above, the incorporated circuit is simulated or actually operated. Therefore, it is difficult to compare the above-described estimation of the maximum operating speed with each other and the above-described mutual comparison of the actual operating speeds between semiconductor integrated circuits in which different circuits are incorporated. On the other hand, when a dedicated circuit suitable for such estimation and measurement is incorporated in the semiconductor integrated circuit as described above, there is a problem that the degree of integration is reduced by the incorporated dedicated circuit. .

The present invention has been made in order to solve the above-mentioned conventional problems and includes the problem of clock skew only by arranging the input / output circuit cells continuously in the input / output circuit area around the chip. A first object of the present invention is to provide a semiconductor integrated circuit capable of forming a non-existent scan path.

Further, the actual operating speed of the semiconductor integrated circuit at the stage of manufacture can be estimated more easily and more accurately, and the actual operating speed can be controlled even between semiconductor integrated circuits in which different circuits are incorporated. A second object is to provide a semiconductor integrated circuit that can be easily compared with each other.

[0011]

SUMMARY OF THE INVENTION According to the present invention, in a semiconductor integrated circuit having a boundary scan register for forming a scan path near an input / output pin at the time of a test, a boundary scan·
The first object is achieved by forming a scan path by incorporating a register and a data ring and arranging the input / output circuit cells continuously in the input / output circuit area around the chip. .

Further, the boundary scan register is laminated at the same position as the power ring.

In addition, when the input / output circuit cell having the boundary scan register built-in, scan data is fetched from the input / output circuit cell which is adjacent to the input / output circuit cell when the boundary scan chain is formed. A clock buffer used for a transmission path of a clock signal used for timing is built in, and the input and output directions of the clock signal are opposite to the input and output directions of the scan data for each of the two adjacent ones. As described above, the clock buffer is provided and connected to achieve the first object and the second object.

[0014]

In the present invention, since the boundary scan register and the data ring are incorporated in each input / output circuit cell, the I / O circuit cells can be arranged continuously in the input / output circuit area around the chip. The campus is formed. Therefore, it is not necessary to incorporate the boundary scan register into the user circuit area as in the conventional case, and the system design of the user circuit can be performed without being aware of the existence of the boundary scan register. Further, the boundary scan registers can be regularly arranged without special placement and wiring for the boundary scan registers, and a scan path free from the problem of clock skew can be obtained.

In particular, when the boundary scan register is laminated at the same position as the power supply ring, the boundary scan register can be incorporated in the empty area of the input / output circuit, and the space can be saved. .

Although the present invention is not limited to this, in the present invention, the actual operating speed of the semiconductor integrated circuit at the stage of manufacture can be estimated more easily and more accurately. I also found what I did. this is,
The input / output circuit cell included in the semiconductor integrated circuit of the present invention is provided with a predetermined clock buffer in a predetermined form. Further, the actual operating speed of the incorporated circuit is estimated from the measurement of the delay time of the clock buffer. A device in which the actual operating speed can be estimated in this way will be described later in more detail as a second embodiment.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings.

First, the first embodiment of the present application will be described with reference to FIGS.
As shown in FIG. 3, in a semiconductor integrated circuit having a built-in boundary scan register for forming a scan path near the input / output pins at the time of testing, as shown in FIGS. The scan path is formed by incorporating the scan register 42 and the boundary scan data ring 44, and only by arranging the input / output circuit cells 40 continuously in the input / output circuit area 20 around the chip. It is a thing.

The boundary scan register 42
Are stacked in the power supply ring region 30 of the input / output circuit cell 40 with respect to the power supply rings 32 and 34, as shown in FIG. Therefore, it is possible to prevent an increase in space due to the inclusion of the boundary scan register 42 in the input / output circuit cell 40, and to increase the number of system circuits 12 by the amount of the boundary scan cells conventionally arranged in the user circuit area 10. It becomes possible to arrange the circuit area 10.

The location of the boundary scan register is not limited to the power ring area.

FIG. 5 is a circuit diagram of an input / output circuit cell portion used in the second embodiment of the present invention.

In FIG. 5, each input / output circuit cell 40a
Includes a boundary scan register 42 and a clock buffer 52. Also, the input / output circuit cell 40a
Of the input buffer circuit 22 or the output buffer circuit 24, which are not shown, respectively.
At least one is provided. Each input / output circuit cell 40a is provided with the power supply rings 32 and 34 and the boundary scan data ring 44 similar to those in the first embodiment.

In FIG. 5, the input / output circuit cell 40a is shown.
Are shown in total n. These behave like shift registers as a whole when a boundary scan chain is formed. Further, when the boundary scan chain is formed in this way, the respective scan data D1 to D (n + 1) are transferred from the left to the right in FIG. 5 according to the clock signals C1 to C (n + 1). It is sequentially shifted. The clock signals C1 to C (n + 1)
Is input from the right side in FIG. Further, the clock signal C2 and the clock signal C3 are sequentially transmitted through the clock buffers 52 included in the input / output circuit cells 40a, and the clock signal C (n + 1) is output from the input / output circuit cell 40a at the left end of FIG. Is output.

Thus, the features of this embodiment are as follows.
When the boundary scan chain is formed as described above, the clock buffer 52 used for the transmission path of the clock signal used for the timing of capturing the scan data with each of the I / O circuit cells 40a which are adjacent to the I / O circuit cell 40a, The point is that each of the input / output circuit cells 40a is provided. The feature of the present embodiment is that the scan data D1
The clock buffer 52 is provided so that the input and output directions of the clock signals C1 to C (n + 1) are opposite to the input and output directions of ~ D (n + 1).
It is the point of connection.

That is, in FIG. 5, the scan data D1 to D (n + 1) are shifted from left to right. On the other hand, in the opposite direction, the clock signal C
The clock buffers 52 of the input / output circuit cells 42 are provided and connected so that 1 to C (n + 1) are transmitted from the right side to the left side in FIG.

Therefore, the scan data D1 input from the left side in FIG. 5 is input, and the input / output circuit cell 40a at the leftmost end in FIG. 5 has any of the other input / output circuit cells 40a. The clock signal Cn which is delayed is input. Further, in the boundary scan register 42 of the input / output circuit cell 40a at the left end, the clock signal C (n +) output from the clock buffer 52 which inputs the clock signal Cn.
1) is used. The clock signal C (n + 1) is the clock signal C input from the right side in FIG.
1, the signal is delayed by a total of n clock buffers 52.

That is, the degree of signal delay of the clock signal C (n + 1) with respect to the clock signal C1 is accumulated by the series connection of the plurality of clock buffers 52.
Further, variations in the signal delay of these clock buffers 52 due to, for example, variations in the manufacturing process of the semiconductor integrated circuit are also accumulated by such series connection.

The clock buffer 5 as described above is used.
The signal delay of 2 and the fluctuation of the signal delay, that is, the operating speed of these clock buffers 52 and the fluctuation of the operating speed affect the delay time and the operating speed due to the manufacturing process of the semiconductor integrated circuit in which they are incorporated. It is useful information for evaluation.

FIG. 6 is a time chart showing the principle of estimating the actual operating speed of the semiconductor integrated circuit in the second embodiment.

In the time chart of FIG. 6, the time chart of FIG.
The clock signal C1 input from the right side, that is, the clock signal CI is shown in FIG. Further, in the time chart, the clock signal C (n + 1) output from the left side in FIG. 5, that is, the clock signal CO is shown. In the time chart, the scan data D1, that is, the scan data DI input from the left side in FIG. 5 is shown. Further, the following description using FIG. 6 is for the input / output cell 40a at the left end of FIG.

First, the boundary scan register 42 in the input / output circuit cell 40a at the left end of FIG.
6 captures the scan data DI at the rising edge of the clock signal CO, as shown in FIG. On the other hand, the scan data DI is input from the left side of FIG. 5, that is, the clock signal CI of the clock signal CI externally input to the entire boundary scan chain when it operates as a shift register. The scan data DI is input from the outside of such a shift register based on the timing.

First, in FIG. 6, the scan data DI is input with reference to the time t ₁ when the clock signal CI input from the outside of the shift register rises. The scan data DI is at time t ₃
Up to that logical state is guaranteed. That is, when the rising time t ₂ of the clock signal CO is later than the time t ₃ at which the scan data DI is guaranteed, the shift register malfunctions. Therefore,
The scan data DI must be fetched in the boundary scan register 42 at the left end in the period from time t ₁ to time t ₃ .

That is, the delay of the clock signal CO with respect to the clock signal CI is allowed until the rising time of the clock signal CO is just before the time t ₃ . Further, considering that the delay of the clock signal CO is according to the accumulation of the delays of the n clock buffers 52 in total, the following equation is established.

(T ₂ −t ₁ ) = (delay per stage of the clock buffer 52) × (total number of stages of the clock buffer 52, that is, n stages) (1)

As described above, if the rising time t ₂ of the clock signal CO is later than the time t ₃ , the shift register malfunctions. In particular, as shown in FIG. 6, the scan data DI is (0),
(1), (0), (1) and so ..., "0" when a "1" and are alternately input, the malfunction due to the rise delay time t ₂ of the clock signal CO Can be detected more reliably from the outside of the shift register by observing the scan data D (n + 1) output from the right side of FIG. 5, for example.

On the other hand, the time t ₃ when the logical state of the scan data DI is guaranteed with reference to the rising time t ₁ of the clock signal CI is when the scan data DI is input from the outside of the shift register. , Timing can be controlled. That is, the time t ₃ when referenced to time t ₁ can be controlled from the outside of the shift register. Therefore, as described above, when the scan data DI is input relative to the time t ₂ peculiar to the semiconductor integrated circuit, which depends on the accumulation of the delay times of the n clock buffers 52 in total. The timing control allows the time t ₃ to be gradually advanced.

Further, in the process in which the time t ₃ is gradually advanced in this way, if a malfunction of the shift register is confirmed from the observation of the scan data D (n + 1) or the like, then the time t ₃ is It can be determined that it is almost the same as t ₂ . In this way time t ₂ and the same time t ₃
The time between and the time t ₁ can be measured outside the shift register.

Therefore, such time t₁And time t₃When
From the time between t₁And time t ₂Set the time between
Can be calculated according to the following formula, which is a modification of the formula (1).
Therefore, the delay time per stage of the clock buffer 52
Can be asked.

(Delay per stage of clock buffer 52) = (t ₂ −t ₁ ) / (total number of stages of clock buffer 52, that is, n stages) (2)

In the present embodiment, the clock signals C1 to C are arranged so as to be in the opposite direction to the input and output directions of the scan data D1 to D (n + 1) (shift direction of the shift register). Since the input and output directions (signal transmission direction) of (n +1) are used, the time t ₁ and the time t ₂ used in the equations (1) and (2) are used.
The time between and can be set with higher accuracy. That is, even if the delay time of each clock buffer 52 is short, by connecting a large number of stages in series in this way, it is possible to accumulate up to a time length that can be measured with higher accuracy.
Further, by accumulating the delay times of the clock buffers 52 in a large number of stages in this way, it is possible to average the delay time variations among the respective clock buffers 52, and also in this respect, it is possible to achieve high accuracy. Is possible.

The operating speed of a circuit incorporated in the semiconductor integrated circuit, for example, the circuit whose actual operating speed is estimated in this embodiment, and the degree of delay of the operating speed of the clock buffer 52 are determined by the semiconductor integrated circuit. Fluctuates due to variations in the manufacturing process. This is due to manufacturing variations in the width of patterns such as wiring when a semiconductor integrated circuit is manufactured using a predetermined mask. Alternatively, it may be due to variations in the thickness of the metal wiring layer, insulating layer, etc. during the manufacturing process. Further, it is due to variations in the diffusion amount and diffusion range at the time of diffusion to a desired portion in the semiconductor integrated circuit.

FIG. 7 is a layout diagram of the integrated circuit of the second embodiment.

FIG. 7 shows some of the plurality of input / output circuit cells 40a shown in FIG. 5, that is, a total of four adjacent input / output circuit cells 40a. In the second embodiment of FIG. 7 as well, similar to the first embodiment of FIG. 4, the input / output circuit cells 40a are continuously arranged in the input / output circuit area around the semiconductor integrated circuit chip. Has been done.
Therefore, according to the present embodiment, the boundary and
It is not necessary to incorporate the scan register in the user circuit area, and the user circuit system can be designed without being aware of the existence of the boundary scan register.
Further, the boundary scan registers can be regularly arranged without any special arrangement or wiring for the boundary scan registers, and a scan path free from the problem of clock skew can be obtained.

Although the present invention is not limited to this, the second embodiment can also be laminated at the same position as the power supply ring, as in the first embodiment. . That is, the boundary scan register 4
2, or the clock buffer 52 is laminated at the same position as, for example, a ring-shaped power ring provided in the input / output circuit area around the semiconductor integrated circuit chip as in the first embodiment. By arranging the stacked layers on the power supply ring of the input / output circuit in this manner, the empty area of the input / output circuit can be effectively utilized, and the degree of integration can be further improved.

In the second embodiment, the time between time t ₁ and time t ₂ , that is, the clock signal C (n
+1) the degree of delay with respect to the clock signal C1
It is also possible to measure by externally observing the clock signal C (n + 1) from the left end of FIG. For example, the clock signal C1 and the clock signal C (n +
It is also possible to measure the delay time between these signals while displaying both 1) and 2) on the oscilloscope. However, when the output drive capability of the clock buffer 52 is small, the error in such measurement increases. For example, the increase in the load of the clock buffer 52 due to the connection of the probe of the oscilloscope increases the error in the delay time measurement.

[0046]

As described above, according to the present invention, the scan path is formed only by continuously arranging the input / output circuit cells in the input / output circuit area around the chip. Therefore, the boundary scan register is formed. You can design a system without being aware that Moreover, even if the special placement and wiring for the boundary scan register are not performed, the boundary scan register is regularly arranged, and a scan path that does not include the problem of clock skew can be easily obtained. Has excellent effect.

[Brief description of drawings]

FIG. 1 is a plan view showing an example of a chip layout of a semiconductor integrated circuit incorporating a conventional boundary scan register.

FIG. 2 is an enlarged view of a main part of FIG.

FIG. 3 is a plan view showing the overall configuration of a first embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 4 is an enlarged view of a main part of FIG.

FIG. 5 is a circuit diagram of an input / output circuit cell portion of a second embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 6 is a time chart showing the principle of operation speed estimation in the second embodiment.

FIG. 7 is an integrated circuit layout diagram of the second embodiment.

[Explanation of symbols]

 20 ... Input / output circuit area 30 ... Power supply ring area 32, 34 ... Power supply ring 40, 40a ... Input / output circuit cell 42 ... Boundary scan register 44 ... Boundary scan data ring 52 ... Clock buffers D1 to D (n + 1) ) ... Scan data C1 to C (n + 1) ... Clock signal

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location // H01L 21/66 F 7377-4M 7377-4M H01L 21/82 T

Claims (3)

[Claims] 1. A semiconductor integrated circuit having a built-in boundary scan register for forming a scan path near an input / output pin during a test, wherein each input / output circuit cell has a boundary scan register and a data ring. The semiconductor integrated circuit is characterized in that the scan path is formed only by arranging the input / output circuit cells continuously in the input / output circuit area around the chip. 2. The semiconductor integrated circuit according to claim 1, wherein the boundary scan register is laminated at the same position as the power ring. 3. The I / O circuit cell containing the boundary scan register according to claim 1, wherein the I / O circuit cell is adjacent to the I / O circuit cell when a boundary scan chain is formed. A clock buffer used for a transmission path of a clock signal used for timing of capturing scan data, and inputting the clock signal in a direction opposite to the input and output directions of the scan data with respect to each of the two adjacent ones. A semiconductor integrated circuit, wherein the clock buffer is provided and connected so as to be in the direction of the output.