JPH06160478A - Logic testing device - Google Patents

Abstract

PURPOSE:To improve the processing efficiency of a logic testing device by controlling a pattern memory which stores test vectors and an execution control circuit by using microinstructions. CONSTITUTION:The title testing device is provided with a vector memory 11 which stores data to be impressed in parallel with each other, observation memory 14 which stores observed data, and a shifting system data memory 5 which stores the data of a shifting system, all of which can independently operate. In order to control the memories with microinstructions, an execution control circuit 4 analyzes instruction codes in data and generate the microinstructions. In addition, a data bus 8 and the data bus 7 of the shifting system function to transfer data at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic tester device, and more particularly to a logic tester device using a scan.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional logic test apparatus transfers a test vector to a data memory 22 via a system bus 20 and an execution control circuit 21, and the test vector is directly input from the pattern memory 22. Output circuit 23
Are output in parallel with each other, and only a few specific channels have meaning in the case of test data using scan, the others need to be fixed, and other than specific channels of the pattern memory 22. It was necessary to maintain a constant state in the column.

[0003]

In this conventional logic test apparatus, since the data stored in the pattern memory 22 to be applied to the circuit under test is configured to be executed in parallel at the same time, the scan is used. In the case of the existing data, only the column of the specific pattern memory 22 is used, and the other columns have no meaning during the series of scanning operations and their capacity is wasted. Therefore, when the contents of the memory are transferred, there is a problem that the transfer time is greatly increased because the entire memory space including waste is processed.

[0004]

A logic test apparatus of the present invention includes a data memory for storing test data, a shift system data memory for storing shift system data read from the data memory, and a read data memory. Control memory for storing microinstructions generated from the data, vector memory for storing parallel output data read from the data memory, and stored in the shift system data memory according to the microinstructions stored in the control memory. And a control circuit for applying the shift system data or the parallel output data stored in the vector memory to the circuit under test via the input / output circuit.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

Test data is stored in the data memory 3 under the control of the memory control circuit 2 via the system bus 1 directly controlled by the host computer. Next, the execution control circuit 4 sequentially reads the data from the data memory 3, analyzes the instruction code described in the data, and transfers the shift system data to the shift system data memory 5. Further, the parallel output data and the microinstruction defining the execution of the channel 17 are generated, and the microinstruction is transferred to the control memory 10 and the normal parallel output data to the vector memory 11 via the data bus 8. The series of transfers is controlled by the channel bus control circuit 9.

At the start of the test, the microinstruction stored in the control memory 10 is executed by the control circuit 12 and the data in the vector memory 11 is applied to the circuit under test by the input / output circuit 15 via the output control circuit 13. . I / O circuit 1
The data observed by 5 is sequentially stored in the observation memory 14.

On the other hand, for shift system data, the execution of microinstructions stored in the control memory 10 progresses,
When it is necessary to apply shift system data, the control circuit 12
Causes the output control circuit 13 to be switched to the shift system, and the channel shift system control circuit 16 is activated to read the necessary data from the shift system data memory 5 via the shift system data bus 7 to set the output control circuit 13 It is applied from the input / output circuit 15 to the circuit under test via the circuit. Similarly, the shift system data observed by the input / output circuit 15 is stored in the shift system data memory 5 via the shift system data bus 7 under the control of the channel shift system control circuit 16. The clock required for executing the above series of operations is generated by the clock generation circuit 6 and supplied to each unit.
In this case as well, the execution control circuit 4 controls the clock generation circuit 6.

When the shift system data application is completed, the control returns to the control circuit 12, and the parallel input / output processing is continuously executed. When the execution progresses and the application of all the data stored in the vector memory 11 of the channel 17 ends, under the control of the channel bus control circuit 9 and the memory control circuit 2, all the contents of the observation memory 14 are transferred to the data bus 8 And the data memory 3 via a part of the execution control circuit 4.
Stored in. When the data to be executed next is stored in another area of the data memory 3, a series of operations such as analysis of instruction code, generation of microinstruction, transfer of parallel output data, transfer of shift system data, etc. are performed again. To be executed.

When the data application and observation of all the contents described in the data memory 3 are completed by repeating the above process as necessary, and when the following data is present, the external data is transmitted via the system bus 1. Under the control of the memory control circuit 2, the storage device stores the test data to be executed next in the data memory 3, and the series of operations of the test device described above is repeated.

Although the basic operation has been described above, by changing the structure of the microinstruction generated by the processing of the execution control circuit 4, for example, the vector memory 11 and the control memory 10 can be operated during the shift processing. In addition to being able to execute simultaneous processing such as rewriting contents, the channel information processing algorithm can be changed depending on the situation to perform various data processing that was performed by the host processor and software within the channel. Is partially executed as the process of.

[0013]

As described above, according to the present invention, the tester has a control circuit which operates by micro-instruction, a parallel output and a scan-system data storage circuit are separately provided, and the instruction code of the data is analyzed. However, since the micro instruction is generated and the micro instruction itself can be changed,
The memory space can be used efficiently, and the maximum transfer speed of the device can be used.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional logic test apparatus.

[Explanation of symbols]

 1 System Bus 2 Memory Control Circuit 3 Data Memory 4 Execution Control Circuit 5 Shift Data Memory 6 Clock Generation Circuit 7 Shift Data Bus 8 Data Bus 9 Channel Bus Control Circuit 10 Control Memory 11 Vector Memory 12 Control Circuit 13 Output Control Circuit 14 Observation memory 15 I / O circuit 16 channels Shift system control circuit 17 channels

Claims (2)

[Claims] 1. A data memory for storing test data,
A shift system data memory for storing the shift system data read from the data memory, a control memory for storing microinstructions generated from the data read from the data memory, and a parallel output data read from the data memory Vector memory, and the shift system data stored in the shift system data memory or the parallel output data stored in the vector memory according to the microinstruction stored in the control memory via the input / output circuit to be tested. And a control circuit for applying to the logic test apparatus. 2. The logic test apparatus according to claim 1, wherein the vector memory, the input / output circuit, the control memory and the control circuit are provided in a channel for applying a signal to the circuit under test.