JPH06153184A - Inter-frame prediction coding and decoding device - Google Patents

Abstract

PURPOSE:To decode a picture signal without error by avoiding generation of overflow and underflow of a reception buffer memory when a processing frequency of a coder differs from a processing frequency of a decoder in the inter- frame prediction coding and decoding device. CONSTITUTION:The prediction coding decoding device is provided with an in-frame prediction coder 100 having a means inserting periodically an in-frame code by one frame and a means measuring a delay time in a transmission buffer memory and sending the result to an in-frame prediction decoder, and with an in-frame prediction decoder having a means measuring a delay time in a reception buffer memory, interleaving decoded frame just before a frame subject to in-frame coding when an overall delay time in the transmission reception buffer memory exceeds a predetermined value, and stopping the decoding processing by one frame time when the overall delay time in the transmission reception buffer memory is less than a predetermined value by one frame time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to interframe prediction for highly efficient coding of a moving picture signal by an interframe predictive coding method when a clock for coding the moving picture signal and a clock for decoding the moving picture signal are asynchronous. The present invention relates to an encoding / decoding device.

2. Description of the Related Art In the case of performing interframe predictive coding, when adaptive quantization or entropy coding is used, the frequency of occurrence of coded data is not constant and changes with time according to the nature of the input signal. To do. In an encoding / decoding device using such an encoding method, a transmission side encoding device is provided with a transmission buffer memory and a reception side decoding device is provided with a reception buffer memory, and an encoding unit, a transmission line, and a transmission line are provided. The speed is smoothed and the clock is changed between the decoding unit and the decoding unit. In this case, it is necessary to perform speed conversion without loss or duplication of encoded data in the transmission and reception buffer memories. If the encoded data is lost or duplicated, a decoding error will occur,
In the interframe predictive coding method, this decoding error continues until the interframe predicted value is refreshed by some method. Therefore, for example, "Japanese Patent Laid-Open No. 58-5
As disclosed in Japanese Patent Publication No. 9641), the data delay time in the transmission buffer memory is measured and transmitted to the decoding device so as to prevent the encoded data from being lost or duplicated in the reception buffer memory. Also, in the above, the data delay time in the reception buffer memory is measured, and the data read from the reception buffer memory is controlled so that the total delay time in both the transmission and reception buffer memories becomes constant.

In this conventional interframe coding / decoding apparatus, the control method of the buffer memory is based on the premise that the coding clock and the decoding clock of the image signal are synchronized. If this premise does not hold, for example, if the frequency of the decoding clock is lower than the encoding clock, the decoding process will not be in time and the encoded data stored in the receive buffer memory will gradually increase. Overflow occurs, data loss occurs, and a decoding error occurs.

The interframe coding / decoding apparatus of the present invention is a high-efficiency coding apparatus for moving image signals, and has an interframe predictive coding method and an intraframe coding method. In an interframe predictive coding apparatus having a transmission buffer memory for smoothing a highly efficient coded signal generated at random and changing to a clock of a transmission line, a frame is obtained by detecting a delay time in the transmission buffer memory. Means for transmitting every frame, means for encoding one frame by an intra-frame encoding method within a predetermined cycle, means for adding a flag indicating the beginning of each frame of the high efficiency encoded signal, and said frame Information indicating that the intra-coded frames are consecutive before the beginning of the frame one frame before the intra-coded frame. Comprising inter-frame prediction encoding device and means for entering.

Further, the interframe coding / decoding apparatus of the present invention receives the transmission coded signal from the interframe predictive coding apparatus according to claim 1 and decodes it from the clock of the transmission path into the moving picture signal. A high-efficiency decoding apparatus for decoding the high-efficiency-encoded signal with a clock asynchronous with the interframe predictive coding apparatus, which has a reception buffer memory for changing to the clock Means for detecting the time and adding it to the delay time in the transmission buffer memory to detect the total delay time; and the total delay when the information indicating the intra-coded frame is detected from the received signal and detected. When the time exceeds a predetermined value, the received signal of the frame immediately preceding the intra-coded frame is written to the receive buffer memory. And means for prohibiting the write, the inter-frame prediction decoding device and a means for stopping one frame time decoding when the total delay time has not reached the predetermined value.

Further, an interframe coding / decoding apparatus of the present invention comprises the interframe predictive coding apparatus according to claim 1 and the interframe predictive decoding apparatus according to claim 2, and the interframe A predictive coding apparatus codes and transmits a moving image signal, receives the transmission coded signal from the interframe predictive coding apparatus, and decodes the moving image signal.

The present invention will be described below with reference to the drawings. Referring to FIG. 1, which shows an embodiment of an interframe predictive coding apparatus of the present invention, a digital image signal M of a moving image input through an input terminal 1 is supplied to a subtracter 5 and a selector 6. The subtractor 5 subtracts the inter-frame prediction value signal h from the frame memory (FM) 10 from the digital image signal M of the moving image to output the prediction error signal k and supplies it to the selector 6. The selector 6 selects either the digital image signal M of the moving image or the prediction error signal k according to the control signal m from the control circuit 11 and outputs it as a selected output signal θ to the quantizer (QNT) 8. Supply. Quantizer (QN
T) 8 quantizes the selection output signal θ from the selector 6 and performs equal-length coding, and supplies it to the variable-length coding circuit (VLC) 13 and the adder 12 as the equal-length coded signal j. Adder 1
Reference numeral 2 denotes a frame memory in which a digital image signal M of a moving image is decoded by adding a selection output signal φ from a selector 9 to a quantized signal j from a quantizer (QNT) 8 and outputting it as a decoded image signal i. (FM) 10 is supplied. The frame memory (FM) 10 writes the decoded image signal i from the adder 12 and delays it by one frame as a prediction signal for the next frame, and supplies it to the subtractor 5 and the selector 9 as an inter-frame prediction value signal h. To do. The selector 9 is the control circuit 11
Either the inter-frame predicted value signal h or the "0" value is selected in accordance with the control signal m from 1) and is supplied to the adder 12 as the selected output signal φ. The frame pulse Q synchronized with the digital image signal M of the moving image input through the input terminal 2 is supplied to the control circuit 11. The control circuit 11 controls the selector 6 to select the digital image signal M of the moving image and the selector 9 to select the "0" value for one frame time by counting the frame pulse Q every predetermined period. The intra-frame coding selection signal "S" ε is generated to control the selectors 6 and 9, and the intra-frame coding selection signal "S" ε is multiplexed by the multiplex circuit (MUX).
The signal 15 is supplied one frame before the control signal m supplied to the selector 6. Variable length coding circuit (VLC) 13
Converts the equal-length coded signal j from the quantizer (QNT) 8 into a variable-length code, outputs it as a variable-length coded signal p, and supplies it to the multiplexing circuit (MUX) 15. Multiplex circuit (MUX)
Reference numeral 15 denotes a variable length coded signal p from the variable length coding circuit (VLC) 13, an intra-frame coding selection signal "S" ε from the control circuit 11 and a transmission buffer memory data storage amount "BOC S from the subtracter 16". “Α” is multiplexed, a frame flag “F” indicating the beginning of the frame is added and output as multiplexed data r, and the transmission buffer memory (BM
S) 17 is supplied. The multiplexing circuit (MUX) 15 sends the write pulse n to the write address generating circuit (WA
GEN) 14. Write address generation circuit 1
4 generates a write address e by the write pulse n from the multiplexing circuit (MUX) 15 and supplies it to the subtracter 16 and the transmission buffer memory (BMS) 17. The read address generation circuit (RA GEN) 18 has an input terminal 3
A transmission line clock R is input via the input line to generate a read address f, and the read address f is supplied to the subtracter 16 and the transmission buffer memory (BMS) 17. Transmission buffer memory (B
MS) 17 is multiplexed circuit (MUX) 15 by write address e from address generation circuit (WA GEN) 14.
From the written multiplexed data r at the read address f from the read address generation circuit (RA GEN) 18, and the output terminal 4 as the transmission encoded data N. Output to. The subtractor 16 uses the write address e from the write address generation circuit (WA GEN) 14 to the read address generation circuit (RA GEN) 18
The read address f from is subtracted from the transmission buffer memory data storage amount of the buffer memory (BMS) 17 ″
BOCS ″ α is calculated and supplied to the multiplexing circuit (MUX) 15 and the control circuit 7. The control circuit 7 outputs the control signal μ according to the transmission buffer memory data storage amount “BOC S” α from the subtractor 16. , And controls the quantizer (QNT) 8. The quantizer (QNT) 8 responds to a control signal from the control circuit 7 to write address generation circuit (WAGEN).
The quantization characteristic is switched so as to control the generated information amount of the write address e output from 14 and control the information amount of the encoded data r written in the transmission buffer memory (BMS) 17. FIG. 2 shows a data string of transmission coded data in the interframe predictive coding apparatus shown in FIG.
This transmission encoded data string is composed of a frame flag "F", an intra-frame encoding selection signal "S" ε, a transmission buffer memory data storage amount "BOC S" α and encoded data x. With this frame structure, a frame flag "S" = 1 indicating that the intraframe coding is selected is multiplexed in the i-th frame, and the coded data x of the (i + 1) th frame is intraframe-coded and transmitted. To be done. Next, referring to FIG. 3 showing an embodiment of the inter-frame predictive decoding apparatus of the present invention, the received encoded data X inputted via the input terminal 22 is the control circuit 24 and the receiving buffer memory (BMR). Is supplied to 27. The reception buffer memory (BMR) 27 writes the reception coded data X input via the input terminal 22 by the write address g from the write address generation circuit (WA GEN) 26, and also writes the received reception coded data Z. Is read by the read address q from the read address generation circuit (RAGEN) 30 and is supplied to the separation circuit (D MUX) 31 as received encoded data w. The separation circuit (D MUX) 31 is a reception buffer memory (BM
R) The frame flag "F", the intra-frame coding selection signal "S" ε, the transmission buffer memory data storage amount "BOC S" α, and the coded data x are separated from the received coded data w from the frame 27, respectively. The inner coding selection signal "S" ε is supplied to the selector 35, the transmission buffer memory data storage amount "BOC S" α is supplied to the adder 29, and the coded data x is supplied to the variable length decoding circuit (VLD) 33. To do. The variable length decoding circuit (VLD) 33 converts the encoded data x from the separation circuit (DMUX) 31 into an equal length code, outputs it as an equal length coded signal y, and supplies it to the adder 34. The adder 34 is a variable length decoding circuit (VLD) 3
The predicted value t from the selector 35 is added to the equal-length encoded signal y from 3
Is added to decode the coded signal x, output as a decoded signal z and supplied to the frame memory (FM) 36 and the selector 37. The frame memory (FM) 36 writes the decoded signal z from the adder 34, delays the written decoded signal z by one frame, and supplies it as a decoded signal u to the selectors 35 and 37. The selector 37 is controlled by the control signal b from the control circuit 32, and the adder 34
Signal z or frame memory (FM) 36 from
Of the decoded image signal Y
Is output to the output terminal 23. The selector 35 is an intra-frame coding selection signal ″ from the separation circuit (D MUX) 31.
Controlled by S ″ ε, the decoded signal u from the frame memory (FM) 36 or “0” value is selected and output. Intra-frame coding selection signal “output from the separation circuit (DMUX) 31” S ″ ε is a separation circuit (D M
(UX) 31 is time-delayed, synchronized with the coded data x, and supplied to the selector 35. The intraframe-coded coded data x is decoded by the adder 34 as the equal-length coded signal y. The selector 35 is controlled so that the "0" value is selected and supplied to the adder 34. When the selector 35 selects the decoded signal u from the frame memory (FM) 36, the decoded signal u is supplied from the selector 35 to the adder 34 as the predicted value signal t of the next frame. The control circuit 24 receives the transmission path clock Z via the input terminal 21, monitors the received encoded data X input via the input terminal 22, and detects the frame flag "F" indicating the beginning of the frame. To monitor the intra-frame coding selection signal "S" ε. Further, when the intra-frame coding selection signal "S" ε is detected as "1" and the control signal a from the control circuit 32 is "1", the control circuit 24 determines that the received coded data X of the frame is A control signal v is output and supplied to the AND circuit 25 in order to prohibit writing to the reception buffer memory (BMR) 27, and the transmission path clock Z from the AND circuit 25 from the input terminal 21 is transferred to the address generation circuit ( The output to the WA GEN) 26 is prohibited so that the write address generation circuit (WA GE)
The output of the write address g from N) 26 is stopped to prohibit the reception encoded data X from being written in the reception buffer memory (BMR) 27. However, the frame flag "F" and the intra-frame coding selection signal "S"
Writing of ε is not prohibited. Separation circuit (D MUX) 3
1 indicates that the data string of the reception encoded data w read from the reception buffer memory 27 is a frame flag "F", an intra-frame encoding selection signal "S", a frame flag ".
When it continues with F ″, it is determined that the coded data x has been thinned out, and immediately the decoding process of the coded data x of the next frame is started to accelerate the decoding operation of one frame. The read address generating circuit (RA GE) from the write address g from the address generating circuit 26
N) The read address c from 30 is subtracted to obtain the reception buffer memory data accumulation amount “BOC R” β of the reception buffer memory (BMR) 27, and the result is supplied to the adder 29. The adder 29 stores the transmission buffer memory data storage amount "BOCS" α from the separation circuit (D MUX) 31 and the reception buffer memory data storage amount "BOC from the subtractor 28.
R ″ β is added to obtain the total storage amount “BOC” δ of the transmission / reception buffer memory data accumulated in the reception buffer memory 17 and the transmission buffer memory 17 in FIG. 1 and supplied to the control circuit 32. The control circuit 32 adds The control signal a and the control signal b are output for each decoded frame according to the value of the total product volume "BOC" δ of the transmission / reception buffer memory data from the device 29. Here, the transmission / reception buffer memory input to the control circuit 32. When the value of the total data storage amount "BOC" δ exceeds the value of the predetermined transmission / reception buffer memory total storage amount "BOC" δ, the control circuit 32 outputs "1" as the control signal a, and the transmission / reception buffer memory Total amount of data ″
When the value of BOC ″ δ is lower than the value of the total amount of accumulated transmission / reception buffer memory data “BOC ″ δ,“ 1 ”is output as the control signal b. Further, when the value of the total transmission / reception buffer memory data storage amount “BOC” δ is within the range of the value of the predetermined transmission / reception buffer memory data total storage amount “BOC” δ, both the control signal a and the control signal b are “ 1 ”is output. When “1” is output as the control signal b from the control circuit 32, the read address generation circuit (RA GEN) 30 stops the output of the read address c and receives the reception code from the reception buffer memory (BMR) 27. The reading of the encoded data w is stopped, and the selector 37
Selects and outputs the decoded signal u from the frame memory (FM) 36 to delay the decoding operation by one frame. In the embodiment of the inter-frame predictive coding apparatus of FIG. 1 and the inter-frame predictive decoding apparatus of FIG. 3, the example in which the intra-frame coding selection signal “S” ε is transmitted as the intra-frame coding selection signal has been described. If it is prohibited to transmit all the data of the i-th frame shown in FIG. 2 to the buffer memory by transmitting it as a signal indicating an intra-coded frame, the intra-frame coding selection signal ″ as a selection control signal to the selector 35 S ″ ε is an intra-frame coding selection signal “S” ε as a signal indicating an intra-frame coding frame.
Can be a selection control signal. The total transmission / reception buffer memory data storage amount “BOC” δ corresponds to the total delay time in the transmission buffer memory (BMS) 17 and the reception buffer memory (BMR) 27 when the transmission rate is constant. Therefore, by monitoring the total storage amount "BOC" δ of the transmission / reception buffer memory data and controlling the total storage amount "BOC" of the transmission / reception buffer memory within a certain range, data loss in the reception buffer memory (BMR) 27 or You can avoid duplication.

Referring to FIG. 4, when the total storage amount "BOC" δ of the transmission / reception buffer memory data exceeds the total delay time "d3", the writing of the reception encoded data X into the reception buffer memory (BMR) 27 is prohibited. , Total delay time "d
2 ”, the reception buffer memory (BMR) 27
Control is possible by prohibiting the reading of the reception encoded data w from. In FIG. 4, A is the case where the frequency of the decoding clock in the interframe predictive decoding device is higher than the frequency of the encoding clock in the interframe predictive coding device, and B is the frequency of the encoding clock is the frequency of the decoding clock. The change in the total storage amount "BOC" δ of the transmission / reception buffer memory data when it is higher than the above is represented by the total delay time, and the section from "d2" to "d3" is 1
It corresponds to the frame time. Further, even if the writing to the reception buffer memory (BMR) 27 is prohibited and the data is lost, an error occurs in the decoded image signal Y because the intraframe-coded coded data X continues in the next frame. do not do. If the maximum frequency difference between the encoding clock and the decoding clock is 100 ppm and the maximum delay difference is 1 frame time (33 ms), it is sufficient to perform intraframe encoding at intervals of about 2.7 minutes at maximum. The inter-frame predictive coding unit 100 of the inter-frame predictive coding device and the inter-frame predictive decoding unit 200 of the inter-frame predictive decoding device according to the above-described embodiments include orthogonal transform coding and motion-compensated inter-frame predictive coding. It can also be applied to a hybrid coding combined with the above coding.

In the above, one embodiment of the inter-frame predictive coding apparatus and the inter-frame predictive decoding apparatus has been described, but the inter-frame predictive coding apparatus and the inter-frame predictive decoding apparatus are connected via a transmission line. Connected and transmitted encoded data N from the output terminal 4 of the interframe predictive encoding device
Is input as the reception coded data X via the input terminal 22 of the interframe predictive decoding apparatus, so that the digital image signal M of the moving image encoded by the interframe predictive encoding apparatus is interframe predictive decoding apparatus. And functions as an interframe predictive coding / decoding device that decodes the decoded image signal Y.

[0006]

As described above, according to the present invention, the coded data for intraframe coding is periodically inserted into the interframe predictive coding apparatus, and the total delay amount in the transmission buffer memory and the reception buffer memory is increased. When the value exceeds a certain value, the decoding process of the frame immediately preceding the intra-frame predictive-coded frame is skipped to avoid the overflow of the reception buffer memory and control the delay time. Even if the clocks of the interframe predictive decoding device are asynchronous, no error occurs in the decoded image signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an interframe predictive coding apparatus of the present invention.

FIG. 2 is a diagram showing an example of a transmission encoded data string.

FIG. 3 is a block diagram showing an embodiment of an interframe predictive decoding device of the present invention.

FIG. 4 is a diagram showing a change in total delay time in a transmission / reception buffer memory.

[Explanation of symbols]

 100 interframe predictive coding unit 200 interframe predictive decoding unit 1,2,3 input terminal 4 output terminal 5 subtractor 6 selector 7 control circuit 8 quantizer (QNT) 9 selector 10 frame memory (FM) 11 Control circuit 12 Adder 13 Variable length coding circuit (VLC) 14 Write address generation circuit (WA GEN) 15 Multiplexer circuit (MUX) 16 Subtractor 17 Transmission buffer memory (BM S) 18 Read address generation circuit (RA GEN) 21 , 22 input terminal 23 output terminal 24 control circuit 25 AND circuit 26 write address generation circuit (WA GEN) 27 reception buffer memory (BM R) 28 subtractor 29 adder 30 read address generation circuit (RA GEN) 31 separation circuit (D MUX) 32 Control Circuit 33 Variable Length Decoding Circuit (VLD) 34 adder 35 selector 36 frame memory (FM) 37 selector M image signal N transmission coded data Q frame pulse R transmission line clock X reception coded data Y decoded image signal Z transmission line clock a, b control signal c reading Address e write address f read address g write address h inter-frame prediction value signal i coded image signal j equal length coded signal k prediction error signal m control signal n write pulse p variable length coded signal q read address r multiplexed data t predicted value signal u decoded signal v control signal w received coded data x coded data y equal length coded signal z decoded signal α transmission buffer memory data storage amount “BOC S” β reception buffer memory data storage amount “BOC R” δ Transmission / reception buffer memory data total accumulated amount “BOC” ε Over arm in coding selection signal "S" theta selection output signal μ control signal φ selection output signal

Claims (3)

[Claims] 1. A high-efficiency coding apparatus for moving picture signals, comprising an inter-frame predictive coding method and an intra-frame coding method, smoothing a high-efficiency coded signal generated randomly. In an interframe predictive coding apparatus having a transmission buffer memory for changing to a clock of a transmission path, means for detecting a delay time in the transmission buffer memory and transmitting for each frame, an intraframe code within a predetermined cycle Before the head of the frame one frame before the intra-coded frame, means for coding one frame by the coding method, means for adding a flag indicating the head of each frame of the high-efficiency coded signal, Means for inserting information indicating that the intra-coded frames are continuous, and Measuring the encoding device. 2. A reception buffer memory for receiving a transmission coded signal from the interframe predictive coding apparatus according to claim 1 and changing to a clock for decoding a transmission path clock into a moving picture signal. In a high-efficiency decoding device that decodes the high-efficiency coded signal with a clock that is asynchronous with the interframe predictive coding device, a delay time in the reception buffer memory is detected and a delay time in the transmission buffer memory is detected. And a means for detecting the total delay time by adding and the information indicating the intra-coded frame from the received signal is detected and the total delay time exceeds the predetermined value when detected, the frame Means for inhibiting writing of a reception signal of a frame immediately preceding the inner coded frame to the reception buffer memory, and the total delay time An inter-frame predictive decoding apparatus comprising: a unit for stopping the one-frame time decoding process when the predetermined value is not reached. 3. The interframe predictive coding apparatus according to claim 1 and the interframe predictive decoding apparatus according to claim 2, wherein the interframe predictive coding apparatus encodes a moving image signal. An interframe predictive coding / decoding apparatus which transmits and receives the transmission coded signal from the interframe predictive coding apparatus to decode the moving image signal.