JPH06153091A - Solid state image pickup device - Google Patents

Abstract

PURPOSE:To continuously vary an exposure time over a whole vertical synchronization area and also to enable stable automatic exposure adjustment with high precision by providing two control means for step-controlling and for continuously controlling the electric load store time of a solid state image pickup device. CONSTITUTION:The device is constituted so as to convert a storage electric load obtained by photoelectrically converting light incident from an object into an image pickup signal and so as to sweep out the storage electric charge by reset potential supply as the solid state image pickup device 1. A timing generating circuit 2 generates reading pulses SG1 and SG2 based on a horizontal synchronizing signal HD from a synchronizing signal generating circuit 5. A shutter pulse generating circuit 7 generates a reset signal P and stepwise controls the exposure time of the image pickup device 1 during a period based on the level of a first control signal. A pseudo signal generating circuit 6 continuously varies the phases of the reading pulses SG1 and SG2 by the portion of one horizontal cycle, at least, based on the level of the second control signal and continuously controls the exposure time of the image pickup device 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device using a solid-state image pickup device such as a CCD imager applied to a video camera, and more particularly, to controlling shutter timing of a solid-state image pickup device having a so-called electronic shutter function. .

[0002]

2. Description of the Related Art Conventionally, for example, in a video camera, a photoelectric conversion element and a charge coupled device (CCD: Ch
a so-called C, which is composed of a large coupled device)
As a mechanism for automatically adjusting the amount of light received by the CD imager (hereinafter, simply referred to as an automatic exposure adjusting mechanism), a mechanism for automatically adjusting a so-called iris (aperture) built in the lens (hereinafter, simply An automatic iris mechanism is known) (see Japanese Patent Laid-Open No. 63-82067).

Specifically, as shown in FIG. 8, the video camera is composed of a lens section 100 and a video camera body 101. The lens unit 100 includes a lens 102,
Iris 103 and detection circuit 104 for detecting the output level of the imaging signal sent from the video camera body 101
And a comparison circuit 105 that compares the output of the detection circuit 104 with a reference voltage, and an iris drive circuit 106 that controls the mechanical opening and closing of the iris 103 based on the output of the comparison circuit 105.

Further, the video camera body 101 is a CCD imager (hereinafter simply referred to as CCD) 107 which is a solid-state image pickup device, an amplifier circuit 108 for amplifying an image pickup signal from the CCD 107, and an amplifier circuit 108 for amplifying the image pickup signal. The so-called AGC (Automatic Gain Contr
ol) applied AGC circuit 109 and this AGC circuit 10
A video signal processing circuit 1 for converting the image pickup signal from 9 into a video signal conforming to the so-called NTSC system or PAL system.
10, and the video signal is taken out from the output terminal φout of the video signal processing circuit 110.

The auto iris mechanism is achieved by feeding back the output level of the image pickup signal from the CCD 107 built in the video camera body 101 to the iris 103 built in the lens unit 100.

That is, the output level of the image pickup signal obtained from the CCD 107 through the amplification circuit 108 and the detection circuit 104 becomes the reference voltage, and in this case, for example, the output of the comparison circuit 105 becomes zero, so that the iris 103 outputs. Mechanical opening and closing is adjusted automatically.

On the other hand, as an automatic exposure adjustment mechanism that does not use the mechanical iris 103, for example, a mechanism for controlling the charge accumulation time of a so-called field accumulation type CCD image sensor (hereinafter, simply referred to as an electronic shutter or an electronic shutter function). ) Was previously proposed by the present applicant (Japanese Patent Application No. 2-238930).

Specifically, in a field storage type CCD image sensor having an electronic shutter function, as shown in FIG. 9, a vertical blanking period (vertical blanking period) in the vertical synchronizing signal VD shown in FIG. When the low level signal indicating VBLK is supplied, the charge read pulse SG (high level) shown in FIG. 9B is supplied. Then, the charge accumulated from the charge read pulse SG in an arbitrary field to the charge read pulse SG in the next field is read out based on the charge read pulse SG in the next field. .

The electronic shutter function is, for example, CC
When the D image sensor is of the vertical overflow type, as shown in FIG. 9C, after the charge read pulse SG of an arbitrary field is supplied, the reset pulse Ps of a level higher than the substrate potential is applied to, for example, the N substrate of the CCD image sensor. Is supplied during the horizontal blanking period (horizontal blanking period), the charges accumulated up to that time are swept away to the substrate side, and the next reset field Ps is supplied after the last reset pulse Ps is supplied. The charge accumulation time (that is, exposure time) T is controlled by controlling the time until the charge read pulse SG is supplied.

For example, in the NTSC system, the maximum exposure time T is 16.7 ms determined by the field frequency, and in the PAL system, the maximum exposure time T is 20 ms determined by the field frequency.

[0011]

By the way, for example, in an industrial video camera, many interchangeable lenses of the so-called C mount system are used, and the lenses of the video camera body can be freely combined and used. .

However, in the auto iris lens adopting the mechanical auto iris mechanism as described above, in the connection (interface) with the video camera main body,
There were various problems. For example, the compatibility problem of the connector for connecting the auto iris lens and the video camera body, the compatibility problem of the standard such as the power supply voltage, the current capacity and the output level of the feedback signal that the video camera body supplies to the auto iris lens. was there.

Further, as shown in FIG.
The comparison circuit 105 and the like are built in the lens unit 100, and each time the lens unit 100 is replaced,
It is necessary to adjust the reference voltage and the like in the lens unit 100 so that optimum exposure can be obtained. Further, in general, the auto iris lens is more expensive than the manual iris lens in which the iris 103 is manually adjusted, and
There is a problem that the connection by the cable is complicated.

Next, adjusting the exposure time T using the electronic shutter function causes the following problems. That is, when the time (1 horizontal cycle) corresponding to 1 cycle of the horizontal sync pulse in the horizontal sync signal HD is 1H, when the exposure time T becomes 10H to 20H (1H≈64 μs) or more,
The start timing of the exposure time T deviates from the vertical blanking period VBLK on the video signal and enters the effective video output period.

In this case, the reset pulse Ps for sweeping away the accumulated charges needs to be output during the horizontal blanking period so as not to affect the image pickup signal currently being read. Therefore, as described above, when the exposure time T is relatively long, the exposure time T has to be controlled (step control) only in units of one horizontal period 1H, that is, 64 μs, as shown in FIG. 9E.

In the low-speed shutter region where the subject is dark and the shutter speed is slow (that is, the exposure time T is long), stepwise step control of the exposure time T is not a problem, but the subject is bright and the shutter speed is fast (that is, In the high-speed shutter region, the amount of change in charge accumulation due to 1H becomes extremely large with respect to the total exposure time T, so that convergence tends to be unstable and it is not suitable for practical use. There is.

Therefore, in order to solve the above problem, the present applicant has previously proposed a solid-state image pickup device capable of finely controlling the shutter speed in the high-speed shutter region (Japanese Patent Application No. Hei 2).
-327850).

However, in the case of the above solid-state image pickup device, if a high-speed shutter of 1/1000 second or more is simply realized, the image signal which is picked up and output becomes unstable and flicker may occur. there were.

That is, in the high-speed shutter area, the shutter speed may be several times as fast as one step, and the exposure time may be twice or more as small as the control signal. For example, 1/10000 seconds from the high speed side, 1
Assuming that the shutter speed changes, such as / 4000 seconds, 1/2000 seconds, etc., the shutter speed may slightly change due to temperature changes and the like when capturing images with good iris adjustment performed at the fastest 1/10000 second. The control signal fluctuates and the image is temporarily taken in 1/4000 seconds.

At this time, since the exposure time becomes twice or more, the output level of the image pickup signal temporarily increases. In this way, when the level fluctuations in which the exposure time is temporarily doubled or more occur constantly, when the output video signal is displayed on the monitor receiver, the fluctuation of the screen brightness occurs in a short cycle, so-called flicker. It becomes a very unsightly image.

Therefore, in the above solid-state image pickup device, it is necessary to stabilize the control signal for determining the shutter speed. Therefore, it is necessary to incorporate a circuit group that suppresses fluctuations in control signals due to temperature changes such as phase compensation circuits and amplitude compensation circuits, which complicates the structure of the solid-state imaging device itself and complicates the manufacturing / assembly process. Could bring.

The present invention has been made in view of the above problems. An object of the present invention is to make it possible to continuously change the exposure time over the entire vertical period, and to perform automatic exposure adjustment with high accuracy and stability. An object of the present invention is to provide a solid-state imaging device that can be used.

[0023]

According to the present invention, accumulated charges obtained by photoelectrically converting light incident from a subject are converted into an image pickup signal, and the accumulated charges are swept away by supplying a reset potential. In the solid-state imaging device having the solid-state imaging device 1 configured as described above and the timing circuit 2 that creates the read pulses SG1 and SG2 based on the horizontal synchronization signal HD, a period based on the level of the first control signal L, Based on the level of the first control means 7 for generating the shutter pulse Ps for outputting the reset potential synchronized with the horizontal cycle and step-controlling the charge accumulation time T of the solid-state image sensor 1, and the level of the second control signal CONT. hand,
A second control means 6 is provided for continuously controlling the charge storage time T of the solid-state image pickup device 1 by continuously varying the phases of the read pulses SG1 and SG2 by at least one horizontal period.

The timing circuit 2 has a circuit structure for producing the read pulses SG1 and SG2 based on the horizontal synchronizing pulse Ph in a predetermined count within the vertical blanking period VBLK during the horizontal synchronizing pulse Ph in the horizontal synchronizing signal HD. In this case, the second control means 6 supplies the timing circuit 2 with a signal P2 in which the phase of the horizontal synchronization pulse Ph of the predetermined count is continuously variable based on the second control signal CONT. It is possible to adopt a circuit configuration in which the output timings of the read pulses SG1 and SG2 are continuously variable.

Specifically, the second control means 6 inputs the horizontal synchronizing pulse Ph in a certain period after the lapse of a predetermined period from the start of the vertical blanking period VBLK in the horizontal synchronizing pulse Ph in the horizontal synchronizing signal HD. And a synchronization signal control circuit 50 for invalidating the
Pulse width generation circuit 44 that outputs a first pulse signal P1 having a pulse width corresponding to the level of the control signal CONT of
A pulse generating circuit 45 for outputting a second pulse signal P2 having the same pulse width as one horizontal synchronizing pulse Ph based on the return timing of the first pulse signal P1; and a horizontal signal from the synchronizing signal control circuit 50. The synchronizing signal HD and the second pulse signal P2 from the pulse generating circuit 45 may be combined to provide a synthesizing circuit 48 which supplies the pseudo horizontal synchronizing signal dHD to the timing circuit 2.

As the first control means 7,
A sawtooth wave generation circuit 25 that generates a sawtooth wave that is reset to a predetermined potential by the read pulses SG1 and SG2 supplied from the timing circuit 2 in each vertical cycle.
And a comparator 26 for comparing the output potential Sn of the sawtooth wave generation circuit 25 with the first control signal L. By the comparison by the comparator 26, the sawtooth wave generation circuit 25 is provided.
Of the output potential Sn of the first control signal L is detected, and the charge storage time T of the solid-state image pickup device 1 is controlled based on this timing. .

[0027]

In the solid-state image pickup device according to the present invention, first,
During a period based on the level of the first control signal L, a shutter pulse Ps that outputs a reset potential synchronized with the horizontal cycle is generated, and the charge storage time T of the solid-state image sensor 1 is step-controlled. Specifically, according to the configuration of the present invention described in claim 4, in particular, according to the first control means 7, the level of the sawtooth wave Sn from the sawtooth wave generation circuit 25 and the first control signal L.
Is compared in the comparator 26, and the start of the charge storage time T is determined based on the comparison result.
In this case, the beginning of the charge storage time T is determined stepwise for each horizontal period.

At the same time, in the second control means 6, the second
Based on the level of the control signal CONT, the read pulses SG1 and SG2 are continuously varied in phase for at least one horizontal period to continuously control the end timing of the charge accumulation time T in the solid-state image sensor 1.

That is, according to the configuration of the present invention as set forth in claim 3, particularly the second control means 6, first, the synchronization signal control circuit 5
At 0, the horizontal sync pulse Ph in the horizontal sync signal HD
In the middle, the input of the horizontal synchronizing pulse Ph in a certain period after the lapse of a predetermined period from the start of the vertical blanking period VBLK is invalidated. Then, the pulse width generation circuit 44 outputs the first pulse signal P1 having the pulse width corresponding to the level of the second control signal CONT within the certain period. From the pulse generation circuit 45, one horizontal synchronization pulse P is generated based on the return timing of the first pulse signal P1.
The second pulse signal P2 having the same pulse width as h is output.

Then, in the synthesizing circuit 48, the horizontal synchronizing signal HD from the synchronizing signal control circuit 50 and the pulse generating circuit 4 are generated.
The second pulse signal P2 from 5 is combined to create the pseudo horizontal synchronizing signal dHD. This pseudo horizontal synchronization signal dH
D is supplied to the timing circuit 2. The timing circuit 2 generates the read pulses SG1 and SG2 based on a predetermined number of horizontal sync pulses Ph in the horizontal sync pulse Ph in the horizontal sync signal HD. As described above, the pseudo horizontal sync signal dHD is generated. Of the horizontal synchronizing pulse Ph in the horizontal synchronizing signal HD, the phase of the horizontal synchronizing pulse Ph of a predetermined count is varied according to the level of the second control signal CONT, and therefore is read from the second control means 6. The output timings of the pulses SG1 and SG2 are changed in the same manner as the horizontal synchronizing pulse Ph whose phase is changed.

By making the read-out pulses SG1 and SG2 variable, the charge accumulation time T is changed stepwise for each 1H (1 horizontal cycle) 1H corresponding to one cycle of the horizontal synchronizing pulse Ph. It is possible to make linear continuous variable according to the output level of Si. In particular, by setting the variable length m of the read pulses SG1 and SG2 to at least 1H, the stepwise change at the beginning of the charge accumulation time T and the 1H portion of the read pulses SG1 and SG2 that determines the end of the charge accumulation time. That is, the continuous accumulation and the continuous variation are simultaneously performed, and the charge storage time T can be adjusted over the entire vertical period.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the solid-state image pickup device according to the present invention is applied to a video camera (hereinafter referred to as a video camera according to the embodiment) will be described below with reference to FIGS.

As shown in FIG. 1, the video camera according to this embodiment converts accumulated charge obtained by photoelectrically converting light incident from a subject into an image pickup signal and resets in synchronization with a horizontal cycle. The solid-state imaging device 1 has a charge storage time that can be controlled by sweeping away the stored charges by supplying a potential.

In this solid-state image pickup device 1, for example, a large number of light-receiving portions formed by pn-junction photodiodes are arranged in a matrix in the vertical (row) direction and the horizontal (column) direction, and the accumulated charges in the light-receiving portions are transferred in the row direction. The vertical transfer registers are arranged in the column direction, for example, an interline CCD image sensor. For example, four electrodes (for example, an electrode layer made of polycrystalline silicon) forming the transfer electrodes of the vertical transfer register have four phases of vertical transfer pulses V1, V2, V having different phases during the horizontal blanking period.
3 and V4 are applied, and the accumulated charges are transferred in row units according to the application timing of these pulses V1 to V4.

In addition, at a predetermined time within the vertical blanking period, the first and second read pulses SG1 and SG
G2 is applied and the charges accumulated in the light receiving portion are read out to the vertical transfer register side. The read pulses SG1 and SG2 are applied to the corresponding transfer electrodes by being superimposed on the corresponding first and third vertical transfer pulses V1 and V3, for example. The read pulses SG1 and SG2
By applying, the potential of the read gate between each light receiving portion and the vertical transfer register rises, and the charge accumulated in the light receiving portion is transferred to the vertical transfer register side. The first read pulse SG1 is output at a timing of a phase ahead of the second read pulse SG2 by, for example, about 5 μs.

Further, in the effective pixel output period of the horizontal period, the horizontal transfer register is provided with, for example, two phases different from each other.
The phase horizontal transfer pulses H1 and H2 are supplied, and the charges transferred from the vertical transfer register to the horizontal transfer register are sequentially transferred to the output section side at the timing of horizontal scanning.

The output unit is, for example, a floating diffusion (hereinafter, simply FD) functioning as a charge-voltage conversion unit.
, A floating diffusion amplifier having a reset gate and a reset drain (hereinafter,
The electric charge from the horizontal transfer register is sequentially transferred to the FD of this FDA, converted into a voltage, and taken out as an image pickup signal Si. FD
The charges transferred to the gate are swept out to the reset drain formed adjacent to the gate by supplying the reset pulse PG to the reset gate, which raises the potential under the gate (that is, lowers the potential barrier). It is like this.

The vertical transfer pulses V1 to V4, the horizontal transfer pulses H1 and H2, the read pulses S1 and S2, and the reset pulse PG are supplied from the timing generation circuit 2 in the preceding stage. In particular, the vertical transfer pulses V1 to V4 and the read pulses S1 and S2 are supplied to the solid-state image sensor 1 via the vertical drive circuit 3 for the purpose of suppressing signal attenuation.
In particular, the read pulses S1 and S2 are superposed on the first and third vertical transfer pulses V1 and V3, for example, in the vertical drive circuit 3.

The timing generation circuit 2 generates a clock signal CLK for generating a synchronization signal based on the reference clock Pc from the high frequency oscillator (28 MHz) 4, and supplies this clock signal CLK to the synchronization signal generation circuit 5 in the subsequent stage. To do. The synchronization signal generation circuit 5 is the timing generation circuit 2 described above.
Vertical sync signal VD based on the clock signal CLK from
And a horizontal synchronizing signal HD, and a timing generation circuit 2
Supply to.

Here, the horizontal synchronizing signal HD is converted into a pseudo horizontal synchronizing signal dHD by a pseudo signal generating circuit 6 described later, and the pseudo horizontal synchronizing signal dHD is converted into the horizontal synchronizing signal H.
It is supplied to the timing generation circuit 2 as D. The timing generation circuit 2 also uses various pulse signals (vertical transfer pulses V1 to V4, horizontal transfer pulses H1 and H2, read pulses) based on the vertical sync signal VD and the pseudo horizontal sync signal dHD from the sync signal generation circuit 5. S1, S2 and reset pulse PG) are created.

Further, a predetermined substrate potential Vs is applied to the terminal Vsub of the solid-state image pickup device 1, particularly its substrate (for example, N-type substrate). The substrate potential Vs controls the potential of the overflow control region in the vertical direction due to, for example, a P-type well region existing between the light receiving portion and the substrate. When the substrate potential Vs becomes higher than a predetermined potential, the substrate potential Vs becomes higher. Potential rises and the potential barrier due to the P-type well region lowers (correctly, the barrier disappears), and the accumulated charge in the light receiving portion is swept out to the substrate side. This operation is usually called an electronic shutter.

The electronic shutter operation is performed by supplying a rectangular pulse signal Ps to the substrate potential Vs in the supply system of the substrate potential Vs and supplying the superimposed signal (Vs + Ps) to the terminal Vsub of the substrate. Be seen. The output timing of the pulse signal Ps is output during the horizontal blanking period in order to eliminate the influence (appearing as noise) on the video signal due to the electronic shutter operation. Therefore, hereinafter, this potential is referred to as a shutter pulse Ps for convenience.

The shutter pulse Ps is generated by the shutter pulse generation circuit 7 described later. Then, the shutter pulse Ps is supplied to the substrate potential setting circuit 8 and the substrate potential V set by the substrate potential setting circuit 8 is set.
substrate terminal Vsub of the solid-state imaging device 1 after being superimposed on s
Is supplied to.

On the other hand, the image pickup signal Si from the solid-state image pickup device 1
Is supplied to the signal processing circuit 9 in the subsequent stage. The signal processing circuit 9 basically includes, as shown in FIG. 2, a sample / hold (S / H) circuit 10 for sampling the image pickup signal Si at a predetermined timing, and the S / H circuit 10. An amplifier 11 for amplifying the image pickup signal Di, and an automatic gain adjustment circuit (AGC circuit) 12 for adjusting the gain of the image pickup signal Di amplified by the amplifier 11 to a predetermined level.
The image pickup signal Di from the AGC circuit 12 is sent to, for example, NTS.
It has a video signal processing circuit 13 for converting into a video signal Vi of a predetermined format such as C system.

The video signal Vi converted by the video signal processing circuit 13 is taken out from the output terminal φout and supplied to various video equipment such as a monitor receiver and a VTR.
Further, the signal processing circuit 9 is connected to a detection circuit 14 for detecting the output level (peak value or average value) of the image pickup signal Di from the S / H circuit 10, and the detection signal Li from the detection circuit 14 is , And is supplied to the shutter pulse generation circuit 7 in the subsequent stage via the amplifier 15.

Next, the structure of the shutter pulse generation circuit 7 will be described with reference to FIG. The shutter pulse generation circuit 7 includes an operational amplifier 21 and an N
A constant current source 23 mainly composed of a PN transistor Tr1;
A sawtooth wave generation circuit 25 mainly composed of an operational amplifier 24 in which a capacitor Cf and a PNP transistor Tr2 are connected in parallel to a negative feedback line, a comparator 26, and an AND circuit 3
0, a NAND circuit 27, and a shutter pulse generation circuit 29 including a NAND circuit inverter 28. A reset pulse Pr from the timing generation circuit 2, for example, is supplied to the base of the PNP transistor Tr2 in the sawtooth wave generation circuit 25 and one input side of the AND circuit via the terminal φb.

The reset pulse Pr falls on the basis of the output of the first read pulse S1 and is, for example, 200 from the end t _{VE of the} vertical blanking period (VBLK).
It is a negative pulse signal that rises at the time of μs (see FIG. 4). By the supply of the reset pulse Pr, the capacitor Cf is discharged, and the output level of the sawtooth wave accompanying the charge accumulation in the capacitor Cf drops to the reference level V ₀ .

When the output level of the reset pulse Pr returns to the high level, the PNP transistor Tr2 is turned off, and the electric current is gradually drawn into the capacitor Cf by the constant current source 23 so that the electric charge is gradually accumulated and the operational amplifier 24 is operated. The output side level of the
As shown in (1), one sawtooth wave signal Sn is formed every cycle of the reset pulse Pr, that is, every vertical cycle. Also,
In the AND circuit 30 of the shutter pulse generation circuit 29, as described above, the reset pulse Pr from the terminal φb is input to one input side, and the output signal Pw from the comparator 26 is input to the other input side. To be done. Further, the NAND circuit 27 in the subsequent stage has an AND circuit 30 on one input side.
From the sync signal generating circuit 5 is input to the other input side.

Further, the shutter pulse generating circuit 7 is
A low-pass filter 31 including an RC circuit for averaging the detection signal Li sent from the detection circuit 14 in the signal processing circuit 9 via the amplifier 15, and the low-pass filter 31.
And two operational amplifiers 32 and 33 for amplifying the output from each.

Further, the shutter pulse generating circuit 7 is provided with two switches SW1 and SW2. The one switch SW1 connects a fixed contact 34a to which the amplified signal Li1 from the one amplifier 32 is supplied, a fixed contact 34b connected to the first manual adjustment volume 36, and between these fixed contacts 34a and 34b. The movable contact 34c is movable, and the output signal L from the movable contact 34c is supplied to, for example, the + terminal of the comparator 26 in the shutter pulse generation circuit 29. The negative terminal of the comparator 26 is supplied with the sawtooth wave signal Sn from the sawtooth wave generation circuit 25.

The other switch 35 has a fixed contact 35a to which the amplified signal Li2 from the other operational amplifier 33 is supplied.
A fixed contact 35b connected to the second volume 37 for manual adjustment, and a movable contact 35c movable between the fixed contacts 35a and 35b. The output signal CONT from the movable contact 35c will be described later. Pseudo signal generation circuit 6
Is supplied to.

Then, the above two switches 34 and 35
Each of the changeover switches 34d and 35d in 1 is switched at the same time by a control signal from a system controller (not shown) based on the operation of an automatic / manual setting switch (not shown) installed outside the video camera.

Next, the signal processing operation of the shutter pulse generation circuit 7 will be described with reference to the timing chart of FIG. First, a case where "automatic" is set by an external automatic / manual setting switch will be described.
In this case, in the switches 34 and 35, the changeover switches 34d and 35d respectively have one fixed contact 34a.
And 35a side.

In this state, the sawtooth wave signal Sn is supplied to one input side of the comparator 26, and the detection signal Li (= L; image pickup signal S from the detection circuit 14 is supplied to the other input side thereof.
A DC signal based on the output level of i) is supplied via the switch 34. Then, in this comparator 26,
Output level of sawtooth wave signal Sn and detection signal Li (= L)
Output level is compared. At this time, the comparator 26
Outputs a high level signal when the output level of the detection signal Li (= L) is higher than the output level of the sawtooth wave signal Sn, and the output level of the sawtooth wave signal Sn is the detection signal Li (=
When it is higher than the output level of L), a low level signal is output.

The output of the comparator 26 is supplied as a window pulse Pw to one input side of the AND circuit at the next stage. This AND circuit equivalently performs signal processing to lengthen the pulse width of the window pulse Pw by the pulse width of the reset pulse Pr supplied to the other input side. Therefore, the output signal from this AND circuit is also referred to as a window pulse for convenience.

The window pulse Pw 'from the AND circuit is supplied to one input side of the NAND circuit 27. In the NAND circuit 27, of the horizontal synchronizing pulses Ph included in the horizontal synchronizing signal HD supplied to the other input side, the horizontal synchronizing pulse Ph during the period in which the window pulse Pw ′ is at a low level is thinned out. , The shutter pulse Ps for which the output of the horizontal synchronizing pulse Ph is valid is output only during the period when the window pulse Pw ′ is at the high level. This shutter pulse Ps
1 is supplied to the substrate potential setting circuit 8 and is combined with the substrate potential Vs in this circuit 8 and supplied to the substrate terminal Vsub of the solid-state imaging device 1.

Therefore, the detection signal Li from the detection circuit 14
When the output level of (= L) is high as shown in FIG. 5A, for example, the period without the shutter pulse Ps, that is, the exposure period T becomes short, and conversely, as shown in FIG. 5B, when the output level is low, The exposure time T becomes longer. This exposure time T
Is generated by synthesizing the shutter pulse Ps with the horizontal synchronizing signal HD in the NAND circuit 27, the time corresponding to one period of the horizontal synchronizing pulse Ph (1 horizontal period) 1
It will change stepwise for each H.

As described above, in the shutter pulse generation circuit 7, the sawtooth wave signal Sn of the vertical cycle output from the sawtooth wave generation circuit 25 and the image pickup signal Li (= The level of L) is compared by the comparator 26 for each vertical cycle, and the exposure time T of the solid-state image sensor 1 is controlled by the shutter pulse Ps generated based on the comparison result, and the shutter speed control of the electronic shutter is performed. An automatic exposure adjustment mechanism is configured.

Next, if "manual" is set by an external automatic / manual setting switch, each switch 3
Changeover switches 34d and 35d in 4 and 35
However, since they are respectively connected to the other fixed contacts 34b and 35b, the set potential Va (= L) by the first manual adjustment volume 36 is supplied to the other input side of the comparator 26. In this case, the first manual adjustment volume 36
When the exposure time T is converted, the maximum variable width of the resistance value is the maximum time from the generation time t ₀ of the sawtooth wave signal Sn to the reset time t _E of the sawtooth wave signal Sn, and the minimum, for example, vertical blanking. It is set to the time from the beginning t _V of the period (VBLK) to the reset time t _E of the sawtooth wave signal Sn.

Next, the circuit configuration of the pseudo signal generating circuit 6 will be described with reference to FIG. The pseudo signal generating circuit 6 has a predetermined number of horizontal synchronizing pulses Ph in the horizontal synchronizing pulse Ph in the horizontal synchronizing signal HD from the synchronizing signal generating circuit 5.
The pseudo horizontal synchronizing signal dHD whose phase is continuously variable is generated.

That is, the circuit 6 includes two multivibrators 41 and 42 (to be exact, Dual Precision Monos).
table Multivibrator: eg MC74HC4538)
, A second IC circuit IC2 in which an 8-bit shift register 43 (for example, MC74HC164) is incorporated, and a third IC circuit IC2 in which two multivibrators 44 and 45 (MC74HC4538) are incorporated. IC circuit IC3 and four NAND circuits 46
4th IC incorporating ~ 49 (MC74HC00)
It is composed of a circuit IC4.

The connection relationship between the IC circuits IC1 to IC4 is such that the A terminal of the first multivibrator 41 in the first IC circuit IC1 is fixed to the ground potential Vss.
The vertical synchronizing signal VD from the synchronizing signal generating circuit 5 is connected to the B terminal so as to be supplied. The inverted Q terminal of the multivibrator 41 is connected to the reset terminal RESET of the shift register 43 in the second IC circuit IC2. The Qh terminal at the final stage of the shift register 43 is connected to the A terminal of the second multivibrator 42 in the first IC circuit IC1, and the inverted Q terminal of the multivibrator 42 is connected to the fourth IC circuit IC.
4 is connected to one input side of the second NAND circuit 47.

The first NAND circuit 46 in the fourth IC circuit IC4 constitutes an inverter, and the horizontal synchronizing signal HD from the synchronizing signal generating circuit 5 is supplied to both input sides thereof. The output of the NAND circuit 46 is connected to the other input side of the second NAND circuit 47, and the output of the second NAND circuit 47 is connected to one input side of the third NAND circuit 48. The output of the first NAND circuit 46 is connected to the clock terminal CLOCK of the shift register 43 via the contact a. This shift register 4
The final stage Qh terminal of 3 is the third IC through the contact b on the way.
A of the first multivibrator 44 in the circuit IC3
The inverted Q terminal of the multivibrator 44 is connected to the A terminal of the second multivibrator 45.

Then, the second multivibrator 4
The inverted Q terminal of 5 is connected to the other input side of the third NAND circuit 48. The output CONT from the switch 35 shown in FIG. 3 is supplied to the contact c of the resistor R3 and the capacitor C3 outside the first multivibrator 44. And the fourth IC
The fourth NAND circuit 49 in the circuit IC4 constitutes an inverter, and the output from the third NAND circuit 48 is supplied to both input sides of the fourth NAND circuit 49.
The D circuit 49 outputs a pseudo horizontal synchronizing signal dHD described later.

Functionally, the first IC circuit IC
First multivibrator 41 and second IC in No. 1
The shift register 43 in the circuit IC2 includes the delay circuit 5
The second NAND circuit 47 in the second multivibrator 42 and the fourth IC circuit IC4 configures the horizontal synchronizing signal HD for a certain period after the lapse of a predetermined period from the start of the vertical blanking period (VBLK). The synchronization signal control circuit 50 that invalidates the input is configured.

The first multivibrator 44 of the third IC circuit IC3 is a pulse width generation circuit which outputs a first pulse signal P1 having a pulse width corresponding to the output CONT from the switch 35 during the above-mentioned certain period. The second multivibrator 45 constitutes a pulse generation circuit that outputs the second pulse signal P2 having the same pulse width as the one horizontal synchronization pulse Ph based on the restoration timing of the first pulse signal P1. .

Third NA in Fourth IC Circuit IC4
The ND circuit 48 receives the horizontal synchronizing signal from the second NAND circuit 47 and the second sync signal from the second IC circuit IC3.
The second pulse signal P2 from the multi-vibrator (pulse generation circuit) 45 of FIG.
And a synthesis circuit for outputting as. The pseudo horizontal synchronizing signal dHD is supplied to the timing generating circuit 2 as a horizontal synchronizing signal.

Next, a specific signal processing operation of the pseudo signal generating circuit 6 will be described with reference to the timing chart of FIG.

First, the vertical synchronizing signal VD from the synchronizing signal generating circuit 5 is supplied to the B terminal of the first multivibrator 41 in the first IC circuit IC1, and as shown in FIG. 7C, from the inverting Q terminal, At the fall of the vertical synchronizing signal VD (that is, the start of the vertical blanking period VBLK)
Pulse width (1 is determined by the power supply voltage Vdd and the time constant of the external resistor R1 and the capacitor C1).
A negative pulse signal Pt of about 0 μs) is output.

This pulse signal Pt is used as a so-called trigger, and the reset terminal RE of the shift register 43 is used.
Supplied to SET. The final stage Qh of the shift register 43
A high-level signal is always output from the terminal, but the output level is changed based on the supply of the pulse signal Pt.
Invert to low level. This inversion period is until the output of the eighth count horizontal synchronizing pulse Ph. That is, it returns to a high level at the output (falling edge) of the eighth horizontal sync pulse Ph (see FIG. 7D).

The signal Pq from the terminal Qh of the final stage of the shift register 43 is A of the second multivibrator 42.
The inverted Q of this multivibrator 42 is supplied to the terminal.
From the terminal, as shown in FIG. 7E, the shift register 43
From the power supply Vd
A negative pulse signal Pz having a pulse width (about 160 μs) determined by d and the time constant of the external resistor R2 and the capacitor C2 is output.

Therefore, in this case, the second NAND in the latter stage is
The horizontal synchronization signal HD from the synchronization signal generation circuit 5 is input to the other input side of the circuit 47, but when the signal Pz supplied to one input side becomes low level, the horizontal synchronization signal HD The level change of is ignored. That is, the second
While the signal Pz from the multivibrator 42 is low level, the input of the horizontal synchronizing signal HD is invalid. Therefore, the horizontal synchronizing signal HD from the synchronizing signal control circuit 50 is a signal in which the horizontal synchronizing pulse Ph is thinned out while the signal Pz is at a low level.

The final stage Q of the shift register 43
The signal Pq from the h terminal is supplied to the A terminal of the first multivibrator 44 (pulse width generation circuit) in the third IC circuit IC3 via the contact b. From the inverted Q terminal of the pulse width generation circuit 44, as shown in FIG. 7F,
It rises when the signal Pq from the shift register 43 rises, and the output C from the switch 35 becomes the power supply voltage Vdd.
The positive first pulse signal P1 having a pulse width determined by the potential on which the ONT is superimposed and the time constant of the external resistor R3 and the capacitor C3 is output. Therefore, this first
Pulse signal P1 of the output CONT from the switch 35
Will have a pulse width corresponding to.

This first pulse signal P1 corresponds to the second pulse of the latter stage.
Is supplied to the A terminal of the multivibrator 45 (pulse generation circuit). From the inverted Q terminal of the pulse generation circuit 45, as shown in FIG. 7G, it falls when the first pulse signal P1 falls, and is determined by the power supply voltage Vdd and the time constant of the external resistor R4 and the capacitor C4. The second pulse signal P2 having a negative pulse width (in this example, the same width as the pulse width of the horizontal synchronizing pulse Ph) is output. Therefore, the second pulse signal P2 is transmitted to the switch 3
5 has an output timing according to the output CONT. That is, the output level CO from the switch 35
If NT is high, the phase is advanced by that amount, and if NT is low, the phase is delayed by that amount.

Then, the second pulse signal P2 is supplied to the other input side of the third NAND circuit 48. On the other hand, the output from the sync signal control circuit 50 is invalidated only during the low level period of the pulse signal Pz from the second multivibrator 42 (that is, the horizontal sync pulse is thinned out only during that period). Since HD is output, the second NAND circuit 48 outputs the second N
The pseudo horizontal synchronizing signal dHD (FIG. 7H, which is a combination of the horizontal synchronizing signal HD from the AND circuit 47 and the second pulse signal P2).
Is output). This pseudo horizontal synchronization signal dHD is
Timing generation circuit 2 via the fourth NAND circuit 49
Is supplied as a horizontal synchronization signal.

The timing generating circuit 2 is normally shown in FIG.
As shown in, the period of the reference clock Pc from the high frequency oscillator 4 is doubled based on the output of the horizontal synchronization pulse Ph of the 9th count from the start of the vertical blanking period VBLK in the supplied horizontal synchronization signal HD. The first read pulse SG1 is generated at the time when the counting clock (14 MHz) is set to several hundred. The second read pulse SG2 is 5 μm after the output of the first read pulse SG1.
It is output at intervals of s.

Timing generation circuit 2 in this embodiment
Does not perform the above processing, and as shown in FIG. 7I, of the supplied horizontal synchronization signal (pseudo horizontal synchronization signal) dHD,
A count clock (14 MHz) obtained by doubling the cycle of the reference clock Pc from the high frequency oscillator 4 is output based on the output of the horizontal synchronization pulse (the phase is variable) of the 8th count from the start of the vertical blanking period VBLK. The first read pulse SG1 is generated at the time point when several hundreds have been counted. The second read pulse SG2 is output at an interval of 5 μs after the output of the first read pulse SG1 as in the normal case.

Further, the maximum variable length of the first read pulse SG1 in this embodiment is set to a length of 1H (1 horizontal period) corresponding to 1 period of the horizontal synchronizing pulse Ph. , The first read pulse SG1 in the normal case
Is set so as to be positioned in the middle of the variable length m of the first read pulse SG1 according to the present embodiment.

This setting is made, for example, when the changeover switch 35d of the switch 35 is changed over to one fixed contact 35a side and the level of the detection signal Li (imaging signal) from the detection circuit 14 is supplied as the output CONT of the switch 35. , The value of the negative feedback resistor Rf of the operational amplifier 33 (see FIG. 3) and the external width of the pulse width generation circuit 44 so that the maximum fluctuation width of the detection signal Li becomes a pulse width of 1H in the pulse width generation circuit 44. Resistor R3 and capacitor C
Adjust the values such as 3.

The maximum variable width of the set potential Vb associated with the operation of the second manual adjustment potentiometer 37 is also the length of the pulse width of the first pulse signal P1 output from the pulse width generation circuit 44 for 1H. The variable width of the resistance in the volume 37 is adjusted so that

From the above, the shutter pulse generating circuit 7 and the pseudo signal generating circuit 6 will be described. First, when "automatic" is set by the external automatic / manual setting switch. That is, when the changeover switches 34d and 35d of the switches 34 and 35 are both switched to the one fixed contact 34a and 35a side, the sawtooth wave signal from the sawtooth wave generation circuit 25 in the shutter pulse generation circuit 7 is generated. Sn and the output level of the detection signal Li (imaging signal) from the detection circuit 14 are compared in the comparator 26, and the start of the exposure time T is determined based on the comparison result. In this case, the start of the exposure time T is determined stepwise for each horizontal period.

At the same time, in the pseudo signal generation circuit 6, based on the output level of the detection signal Li from the detection circuit 14, during the horizontal synchronization pulse Ph in the horizontal synchronization signal HD,
Predetermined count (in this example, vertical blanking period VBL
A pseudo horizontal synchronizing signal dHD in which the phase of the horizontal synchronizing pulse Ph at the 8th count from the start of K) is continuously varied is created and supplied to the timing generating circuit 2 in the preceding stage.
The timing generation circuit 2 uses the continuously variable horizontal synchronizing pulse Ph (=) in the supplied pseudo horizontal synchronizing signal dHD.
Based on the output timing of P2), first and second read pulses SG1 and SG2 that determine the end of the exposure time T are created and supplied to the solid-state image sensor 1.

Further, the timing generation circuit 2 creates the reset pulse Pr (see FIG. 4) based on the created first read pulse SG1 and the PNP of the sawtooth wave generation circuit 25 in the shutter pulse generation circuit 7. The signal is supplied to the base terminal φb of the transistor Tr2 to reset the sawtooth wave signal Sn to the predetermined potential V ₀ .

The pseudo horizontal synchronizing signal dHD is the detection signal L from the detecting circuit 14 when the horizontal synchronizing pulse Ph of a predetermined count is included in the horizontal synchronizing pulse Ph in the horizontal synchronizing signal HD.
i output level, that is, the imaging signal S from the solid-state imaging device 1
Since the phase is changed according to the output level of i, the phase of the first and second read pulses SG1 and SG2 from the timing generation circuit 2 is the same as that of the horizontal sync pulse Ph whose phase is changed. The output timing is variable.

The first and second read pulses SG1
And SG2 are made variable so that the exposure time T is a time corresponding to one cycle of the horizontal synchronizing pulse (one horizontal cycle).
It is possible to change from a stepwise variable for each 1H to a linear continuous variable according to the output level of the image pickup signal Si.

Particularly, the first and second read pulses SG
By setting the variable length of 1 and SG2 to at least 1H, the stepwise variable at the beginning of the exposure time T and the continuous variable of 1H of the read pulses SG1 and SG2 are simultaneously performed, and the vertical cycle The exposure time T can be adjusted over the entire area.

On the other hand, when "manual" is set by the external automatic / manual setting switch, both the changeover switches 34d and 35d of the switches 34 and 35 are switched to the other fixed contacts 34b and 35b side. The comparator 26 of the shutter pulse generation circuit 7 is supplied with the set potential Va by the first volume 36, and the pulse width generation circuit 44 of the pseudo signal generation circuit 6 is supplied with the set potential Vb by the second volume 37. To be done.

In this case, the timing of the start of the exposure time T is changed stepwise by the set potential Va of the first volume 36, and the first and second read operations are performed by the set potential Vb of the second volume 37. Pulse SG
Since the output timings of 1 and SG2 are continuously variable, the exposure time T can be adjusted over the entire vertical period in this case as well.

As described above, the video camera according to the present embodiment enables completely continuous exposure adjustment regardless of whether the exposure time T is long or short. Therefore, the response when the exposure time T is relatively short is improved. It is possible to perform stable exposure adjustment with accuracy.

[0090]

As described above, according to the solid-state image pickup device of the present invention, the period based on the level of the first control signal,
A first control unit that generates a shutter pulse that outputs a reset potential synchronized with the horizontal cycle to step-control the charge storage time of the solid-state image sensor, and the read pulse of the read pulse based on the level of the second control signal. Phase at least 1
Since the second control means for continuously controlling the charge accumulation time of the solid-state image sensor by continuously varying the horizontal period is provided, the exposure time can be continuously varied over the entire vertical period.
It is possible to perform highly accurate and stable automatic exposure adjustment.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment (hereinafter, referred to as a video camera according to the embodiment) in which a solid-state imaging device according to the present invention is applied to a video camera.

FIG. 2 is a block diagram showing a configuration of a signal processing circuit incorporated in the video camera according to the present embodiment.

FIG. 3 is a circuit diagram showing a configuration of a shutter pulse generation circuit incorporated in the video camera according to the present embodiment.

FIG. 4 is a timing chart showing a signal processing operation of a shutter pulse generation circuit incorporated in the video camera according to the present embodiment, particularly an output timing of a shutter pulse synchronized with a horizontal synchronizing pulse.

FIG. 5 is a timing chart showing a signal processing operation of a shutter pulse generation circuit incorporated in the video camera according to the present embodiment, particularly a window pulse output timing.

FIG. 6 is a circuit diagram showing a configuration of a pseudo signal processing circuit incorporated in the video camera according to the present embodiment.

FIG. 7 is a timing chart showing the signal processing operation of the pseudo signal processing circuit incorporated in the video camera according to the present embodiment.

FIG. 8 is a block diagram showing an overall configuration of a mechanical auto iris mechanism in a video camera according to a conventional example.

FIG. 9 is a timing chart showing a signal processing operation by an electronic shutter function in a video camera according to another conventional example.

[Explanation of symbols]

 1-Solid-state image sensor 2-Timing generation circuit 3-Vertical drive circuit 4-Oscillator 5-Sync signal generation circuit 6-Pseudo signal generation circuit 7-・ ・ ・ Shutter pulse generation circuit 8 ・ ・ ・ Substrate potential setting circuit 9 ・ ・ ・ ・ Signal processing circuit 14 ・ ・ ・ Detection circuit 23 ・ ・ ・ Constant current source 25 ・ ・ ・ Sawtooth wave generation circuit 26 ・ ・ ・Comparator 29 ... Shutter pulse generation circuit 34, 35 ... Switch 44 ... Pulse width generation circuit 45 ... Pulse generation circuit 48 ... Synthesis circuit 50 ... Synchronization signal control circuit 51 ... Delay circuit

Claims (4)

[Claims] 1. An accumulated charge obtained by photoelectrically converting light incident from a subject is converted into an image pickup signal, and
In a solid-state imaging device including a solid-state imaging device configured to sweep away the accumulated charges by supplying a reset potential, and a timing circuit that creates a read pulse based on a horizontal synchronizing signal, a level of a first control signal Based on the level of the second control signal, a first control unit that generates a shutter pulse that outputs a reset potential synchronized with the horizontal cycle during the period based on The solid-state imaging device further comprises second control means for continuously controlling the charge storage time of the solid-state imaging device by continuously varying the phase of the read pulse by at least one horizontal period. 2. The timing circuit creates a read pulse based on a horizontal sync pulse at a predetermined count within a vertical blanking period in the horizontal sync pulse in the horizontal sync signal, and the second control means is configured to perform the read pulse. Second
The output timing of the read pulse is continuously variable by supplying to the timing circuit a pseudo horizontal sync signal in which the phase of the horizontal sync pulse of the predetermined count is continuously varied based on the level of the control signal of 1. The solid-state imaging device according to claim 1. 3. The synchronizing signal control for invalidating the input of the horizontal synchronizing pulse in a certain period after a lapse of a predetermined period from the start of the vertical blanking period in the horizontal synchronizing pulse in the horizontal synchronizing signal. A circuit, a pulse width generation circuit that outputs a first pulse signal having a pulse width corresponding to the level of the second control signal during the certain period, and a return timing of the first pulse signal based on 1
A pulse generation circuit that outputs a second pulse signal having the same pulse width as the horizontal synchronization pulse, a horizontal synchronization signal from the synchronization signal control circuit, and a second pulse signal from the pulse generation circuit are combined to generate a pseudo horizontal signal. The solid-state imaging device according to claim 2, further comprising a combining circuit that supplies the timing circuit as a synchronization signal. 4. The sawtooth wave generation circuit for generating a sawtooth wave reset to a predetermined potential by a read pulse supplied from the timing circuit every vertical period, the first control means comprising: A comparator for comparing the output potential of the sawtooth wave generation circuit with the first control signal is provided, and the output potential of the sawtooth wave generation circuit is changed to the first control by the comparison by this comparator. The solid-state imaging device according to claim 1, 2 or 3, wherein a timing at which the signal level is exceeded is detected, and the charge storage time of the solid-state imaging device is controlled based on the timing.