JPH0530431A - Exposure time control circuit for solid-state image pickup device - Google Patents

Abstract

PURPOSE:To set a proper exposure time quickly with high accuracy by providing a comparison means comparing a signal level with a signal level range. corresponding to a proper exposure time and a control means controlling an exposure time to the control circuit. CONSTITUTION:A signal level of an output signal of a solid-state image pickup element (CCD) 1 is compared with a signal level range corresponding to a proper exposure time by a comparator means. Then the control means 7 decides a rough adjustment block, a fine adjustment block and no adjustment block corresponding to the result of comparison and in the case of the rough adjustment block, the exposure time is rough-adjusted, and in the case of the fine adjustment block, the exposure time is fine-adjusted and in the case of no adjustment block, the current exposure time is latched. Thus, the exposure time is adjusted quickly with high accuracy to any luminous flux fluctuation and the performance of the exposure time control circuit of the solid-state image pickup element is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure time control circuit for electronically setting an appropriate exposure time in a solid-state image pickup device, and more particularly to setting an appropriate exposure time quickly and accurately with respect to any fluctuation in light quantity. Regarding technology.

[0002]

2. Description of the Related Art In general, a proper image cannot be obtained in a camera unless the exposure amount is appropriate. For example, a video camera using a solid-state image sensor such as a CCD is used in a surveillance door horn camera or the like installed at a front door, and when a person stands in front of the video camera, a sudden change in brightness occurs. There are cases. In such cases,
When the video signal from the video camera is monitored on the TV, the TV screen suddenly becomes dark or bright and the video taken by the video camera cannot be confirmed temporarily. Therefore, even if the light amount changes to the solid-state image sensor due to a rapid change in brightness, it is necessary to have a function of adjusting the appropriate exposure time corresponding to the exposure amount as quickly and accurately as possible. There is an exposure time control circuit for electronically obtaining such a function.

In FIG. 1 showing an exposure time control circuit of such a solid-state image pickup device, a CCD 1 is a solid-state image pickup device for converting an optical signal into an electric signal. SSG (Sync.signal
generator: sync signal generator 2 is, for example, NTSC, P
A horizontal synchronizing signal HDI, a vertical synchronizing signal VDI, an even-odd field discriminating signal FLDI, and an external control signal XSG1 described later, which are necessary for a video signal based on a standard such as AL, are generated, and these generated signals are charged with DRIVER3 and charge. The signal is output to the sweep-out pulse generation circuit 9. DRIVE
The R3 inputs each output signal of the SSG2 and the external control signal OFDX from the charge sweep-away pulse generation circuit 9, and controls the CCD 1 to operate based on each signal. The BUFFER 4 holds the input signal of the CCD 1 and outputs it to the signal processing circuit 5. The signal processing circuit 5 is BUFFE
The output signal of R4 is a normal video signal (NTSC, PAL
Signal). The integrating circuit 6 receives the signal of the signal processing circuit 5 and integrates it in each vertical scanning period to detect a signal level value which is a value based on the average exposure amount of the image input to the CCD 1 in each vertical scanning period. The exposure time control unit 7 receives the output signal of the integrating circuit 6, detects the exposure level, and outputs the signals CUI and CDI, and the signals CUI and C output from the level detection circuit 8.
A charge sweep-out pulse generation circuit 9 for outputting an external control signal OFDX which is a charge sweep-out pulse signal based on DI
And consists of.

Next, the structure of the CCD 1 of the interline transfer system will be described with reference to FIG. Incidentally, FIG.
Then, the number of pixels of the CCD 1 is simplified to 4 × 6.
The CCD 1 is provided for each pixel, receives a video image, and stores the electric charges proportional to the exposure amount, and the photosensors 21 corresponding to the respective photosensors 21. A vertical transfer CCD 22 that reads out and transfers the charges in the vertical direction, a horizontal transfer CCD 23 that horizontally transfers the charges transferred from the vertical transfer CCD 22, and a horizontal transfer CCD.
And an output amplifier 24 that outputs the charge transferred from 23. The even and odd scanning lines are alternately arranged in the horizontal direction. Further, when the external control signal OFDX is input to the CCD 1 from the charge sweep-out pulse generation circuit 9, the charge accumulated in the photo sensor 21 is output to an overflow drain portion (not shown) to empty the charge of the photo sensor 21, and the SSG 2 externally When the control signal XSG1 is input, the charge accumulated in the photo sensor 21 is transferred vertically to the CCD.
Output to 22.

Next, the configurations of the conventional integrating circuit 6 and level detecting circuit 8 will be described with reference to FIG. Integrating circuit 6
Is composed of a resistor R1 and a capacitor C1 and integrates the output signal of the CCD 1 input from the signal processing circuit 5 to output a voltage V _A which is the signal level value. Level detection circuit 8
Is a comparator that sequentially connects resistors R2 to R4 from the power source of voltage V to ground and resistors R2 and R3 at the inverting input terminal and inputs the output voltage V _A of the integrating circuit 6 at the non-inverting input terminal. 31 and resistors R3 and R at the non-inverting input terminal
4 and the output voltage V _A of the integrating circuit 6 at the inverting input terminal
, A power supply and comparator 31,
A pull-up resistor R5 connected between the output of 32 and
R6 and.

Next, the operation will be described. In SSG2, for example, a horizontal synchronizing signal HDI, a vertical synchronizing signal VDI, an even-odd field discriminating signal FLDI, etc., which are necessary for a video signal based on the standards such as NTSC and PAL, are generated. For example, in the case of the NTSC system, one horizontal scanning time is 63.5 μs, the horizontal synchronizing signal HDI is generated by SSG2 and is output every 1H (horizontal scanning period), and the vertical synchronizing signal is output every 262.5 times of the horizontal synchronizing signal HDI. Signal VD
I is generated by SSG2. In addition, the external control signal XSG1
Is generated only once immediately after the vertical synchronizing signal VDI. N
Since interlaced scanning is performed in the method such as TSC and PAL, even-numbered and odd-numbered fields can be discriminated by generating an even-numbered and odd-numbered field discrimination signal. These signals are output to CCD1 via DRIVER3. When the external control signal XSG1 is output to the CCD1 via the DRIVER3, the charges accumulated in the photosensor 21 are transferred to the vertical transfer CCD22, and the CCD is transferred via the horizontal transfer CCD23 and the output amplifier 24.
It is output from 1.

The output signal of the CCD 1 is input to the signal processing circuit 5 via the BUFFER 4, processed into a normal video signal (signal of NTSC, PAL, etc.) and output. The signal input to the signal processing circuit 5 is integrated by the integration circuit 6
Entered in. Then, it is integrated for each vertical synchronization period to obtain C
CCD which is the average value of the exposure amount of the image input to CD1
The signal value level value V _A of the output signal of 1 is detected. This signal level value V _A is set by the comparators 31 and 32 of the level detection circuit 8 of the exposure time control unit 7 to the voltages V ₁ and V _2.
(Comparison voltage V ₁ > V ₂ ) and the signals CUI and CD output from the comparators 31 and 32, respectively, as shown in Table 1.
If the voltage V ₁ <V _A , the amount of exposure of the image is large, and I is the “H” and “L” level, respectively, and if V ₂ <V _A ≦ V _2, it is the appropriate exposure range and both are the “L” level. , V _A <V ₂ , the exposure amount is small and the levels are “L” and “H”, respectively.

[0008]

[Table 1]

Next, in the charge sweep-away pulse generation circuit 9 of the exposure time control unit 7, the signals CUI, CD
Based on I, the external control signal OFD is generated every vertical synchronization period.
X is output to the CCD 1 through the DRIVER 3 by a predetermined pulse number N in synchronization with the horizontal synchronizing signal HDI from the SSG 2. When the external control signal OFDX is input to the CCD 1, the excess charge accumulated in the photo sensor 21 of the CCD 1 is output to the overflow drain portion (not shown), and the charge amount of the photo sensor 21 becomes empty, that is, becomes nothing. When the external control signal OFDX is output by the predetermined number N of pulses,
After that, charges are accumulated in the photo sensor 21 until the external control signal XSG1 is output. Therefore, immediately after the pulse of the external control signal OFDX is generated, the external control signal X
The exposure time is the time until the SG1 pulse is generated, and the exposure time can be controlled by controlling the predetermined pulse number N of the external control signal OFDX. N
In the case of the TSC method, the exposure time is calculated by the following formula: exposure time = (number of scanning lines in one field−predetermined number of pulses) × 1 horizontal scanning time = (262.5−N) × 63.5 (μs). If this predetermined pulse number N = 0, the exposure time will be 1/60 second (16.7 ms), and the exposure time will change from 16.7 ms.
It can be shortened at 63.5 μs intervals. And CC
The signal C is output from the integrating circuit 6 based on the image input to D1.
DI and CUI are output, but the signals CDI and CU in Table 1 are output.
Based on I, the value of N is increased or decreased by 1 in each vertical synchronization period. In this way, the exposure amount of the CCD 1 is adjusted so as to obtain proper exposure.

[0010]

By the way, in the exposure time control circuit of the conventional solid-state image pickup device, for example, when the power is turned on,
When the predetermined number of pulses of the external control signal OFDX is set to N = 1, if the photographing location is extremely bright and the optimum exposure time cannot be obtained unless the exposure time is set to the minimum value, the predetermined number of pulses is set to N = 1. Starts and reaches the optimum exposure time N =
Up to 262, N must be incremented by 1 in each vertical sync period. Therefore, the predetermined number of pulses is N = 2
It takes 4.4 seconds (= 262 × 16.7 ms) to reach 62, and even if the brightness fluctuates, the response to the brightness fluctuation may not be good. In order to improve the responsiveness, the value of the predetermined pulse number N may be incremented by a predetermined value n (for example, n = 5), but instead, the exposure time setting interval is set to 63.5 μs × n steps. Therefore, the accuracy may be deteriorated and an appropriate exposure amount may not be obtained.

The present invention has been made in view of such a conventional problem, and an exposure time control circuit of a solid-state image pickup device capable of promptly and accurately adjusting to proper exposure to any variation in light amount. The purpose is to provide.

[0012]

Therefore, according to the present invention, a solid-state image sensor for accumulating and photoelectrically converting charges based on an input image, and an output signal of the solid-state image sensor are integrated to detect a signal level value. And an integration unit for performing an exposure time control circuit of a solid-state image pickup device for setting an exposure time for accumulating charges in the solid-state image pickup device within a predetermined period based on a signal level value detected by the integration unit. A comparing means for comparing the signal level value detected by the integrating means with a signal level range corresponding to a preset appropriate exposure time; and the detecting means for detecting the integrating value based on the comparison result of the comparing means. When the signal level value greatly deviates from the signal level range corresponding to the appropriate exposure time, it is determined to be a rough adjustment section, the exposure time is greatly changed, and it is detected by the integrating means. When the signal level value deviates from the signal level range corresponding to the appropriate exposure time by a small amount, it is determined as a fine adjustment section, the exposure time is changed to a small value, and the signal level value detected by the integrating means becomes the appropriate exposure time. When it is within the corresponding signal level range, it is determined to be a non-adjustment section, and a control means for holding the current exposure time is provided.

Further, signal output means for outputting to the control means a charge sweep-away signal for making the charge amount of the solid-state image pickup device null, and a charge sweep-away signal when it is determined to be a rough adjustment section. The output time of the charge is greatly changed, the time when the charge sweep signal is output is changed when it is determined to be the fine adjustment section, and the time when the charge sweep signal is output is not changed when it is determined to be the non-adjustment section. Then, setting means for variably setting the exposure time during which the charge is accumulated in the solid-state imaging device within the predetermined period by setting the time for outputting the charge sweep-out signal is provided.

[0014]

According to the above arrangement, the solid-state image pickup device accumulates electric charge based on the image and photoelectrically converts it into an electric signal. The output signal of the solid-state image sensor is integrated by the integrating means to detect the signal level value. This signal level value is a value based on the average exposure amount of the image input to the solid-state image sensor. This signal level value is compared by the comparison means with a signal level range corresponding to the preset proper exposure time, and based on the comparison result, the signal level value of the output signal of the solid-state image pickup device is a signal corresponding to the proper exposure time. When it is outside the level range, the control means judges it as a rough adjustment section and changes the exposure time greatly, and when it is outside the level range, the control means judges it as a fine adjustment section and changes it a little, and the exposure time is adjusted appropriately. At some time, the control means determines that there is no adjustment section and holds the current exposure time. As a result, it becomes possible to quickly and accurately set the proper exposure time for any fluctuation in the light amount.

When the charge sweep-out signal is output from the signal output means from the beginning of the predetermined period and the charge sweep-out signal is output from the signal output means, the charge accumulated in the solid-state image pickup device becomes zero. Therefore, the exposure time is the time during which charges are accumulated in the solid-state image sensor within a predetermined period after the output of the charge sweep signal is stopped, and when the control unit determines that it is in the rough adjustment section, the charge sweep signal is output. The exposure time is roughly adjusted by roughly changing the exposure time, and when it is determined to be a fine adjustment section, the time when the charge sweeping signal is output is changed to a small amount and the exposure time is finely adjusted. , Do not change the exposure time.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. The same elements as those in FIGS. 1, 2, 5 and 6 are designated by the same reference numerals and the description thereof will be omitted. For example, in the case of a door horn camera for monitoring installed at the entrance, other TV cameras, sensor cameras, etc., for example, CCD
A video camera using a solid-state image sensor such as the above is used. Further, this video camera is provided with an exposure time control circuit of the solid-state imaging device for electrically adjusting the exposure time to an appropriate value. FIG. 1 is a block diagram showing an exposure time control circuit of the solid-state image pickup device, in which the exposure time control unit 9 corresponds to control means, and the level detection circuit 8 corresponds to comparison means. FIG. 3 is a circuit diagram showing an integrating circuit 6 and a level detecting circuit 8 which are integrating means of the exposure time control circuit, and FIG. 4 is a block diagram showing a charge sweeping-out pulse generating circuit 9 of the present embodiment.

In FIG. 3, resistors R11 to R15 have a voltage V _C.
From the power source to the ground, and connect the power source voltage V _C to
Each voltage is divided into voltages V _{1 to} V ₁₄ . Pull-up resistor R
16 to R18 are connected at one end to the power supply of the voltage V _C , the resistor R16 is connected at the other end to the output ends of the comparators 41 and 44, and the resistor R17 is connected at the other end to the output end of the comparator 43. R
The other end of 18 is connected to the output end of the comparator 42. The comparator 41 inputs the voltage V ₁₁ at its non-inverting input terminal, inputs the output voltage V _A of the integrating circuit 6 at its inverting input terminal, connects the output terminal to the output terminal of the comparator 44, and outputs the signal WIDE. The comparator 42 has a voltage V ₁₂ at its inverting input terminal.
Is input, the output voltage V _A of the integration 4 is input at the non-inverting input terminal, and the signal CU is output from the output end. Comparator 43
Inputs the voltage V ₁₃ at the non-inverting input terminal, the output voltage V _A of the integrating circuit 6 at the inverting input terminal, and outputs the signal CD from the output end. The comparator 44 receives the voltage V ₁₄ at its inverting input terminal and the output voltage V _A of the integrating circuit 6 at its non-inverting input terminal.

In FIG. 4, the latch circuit 51 is connected to the output terminals of the comparators 42 to 44 of the level detection circuit 8, and SSG
When the vertical synchronizing signal VDI is input from 2, the signals CU, CD and WIDE from the level detection circuit 8 are latched.
The encoder 52 which is the setting means is connected to the latch circuit 51,
When the respective signals CU, CD, WIDE are latched by the latch circuit 51, the signals CU, CD, WIDE are input, and the conditions shown in Table 2 are determined in accordance with these signals, and corresponding to Table 2. The control signal is output to the storage unit 53 such as a ROM, and the counter 54 is output a control signal for counting up or down the count value. The storage unit 53 stores a correction value n (for example, n = 5) and 1 for correcting the predetermined pulse number N of the external control signal OFDX, which is a charge sweep-away signal, and corrects it in accordance with the control signal from the encoder 52. The value n or 1 is output to the counter 54. The counter 54 inputs a count-up or count-down control signal from the encoder 52, counts up or counts down by the correction value n or 1 from the storage unit 53 based on this control signal, and holds this count value. The latch circuit 55 latches the count value held by the counter 54 and outputs the control circuit 56 and the encoder 52 which are signal output means.
And output to. The control circuit 56 uses the external control signal O
It has a built-in counter that counts the number of times FDX is output, and connects to SSG2 to connect photo sensor 21
When the external control signal XSG1 for outputting the charges accumulated in the vertical transfer CCD 22 is input, this built-in counter is reset, and the external control signal OFDX is synchronized with each input of the horizontal synchronization signal HDI from SSG2. Is output and the count value of this built-in counter is incremented. Further, the control circuit 56 compares this count value with the count value of the counter 54 latched by the latch circuit 55, until the count value of the built-in counter matches the count value of the counter 54 or becomes larger than the external control signal. Output OFDX.

Next, the operation will be described. As in the conventional case, as shown in FIG. 5, the horizontal sync signal HDI, the vertical sync signal VDI, and the even-odd field discrimination signal FLD necessary for the video signal based on the standards such as NTSC and PAL are supplied from the SSG2.
I, the external control signal XSG1 and the like are output to the DRIVER3, and of these, the horizontal synchronization signal HDI, the vertical synchronization signal VDI, the external control signal XSG1 and the like are also output to the charge sweep-out pulse generation circuit 9. The external control signal X
Only one shot of SG1 is generated immediately after the vertical synchronization signal VDI, and the period during which the external control signal XSG1 is output is the predetermined period. Further, the external control signal OFDX is input to the DRIVER 3 from the charge sweep-off pulse generation circuit 9, and DR
CCD1 based on each signal input to IVER3
Is controlled and operates. The output signal of CCD1 is BUF
The signal processing circuit 5 processes the video signal through the FER 4 and outputs the video signal.

The output signal of the CCD 1 is a signal processing circuit 5
The signal level value is input to the integration circuit 6 via the signal and is integrated for each vertical scanning period, and this signal level value based on the average exposure amount for each vertical scanning period is detected. The voltage V _{A which} is the detected signal level value is input to the level detection circuit 8 and each of the voltages V _{11 to} V is input by the comparators 41 to 44 of the level detection circuit 8.
Compared with ₁₄ . When the output voltage V _A of the integrator circuit 6 is under the input signal condition as shown in Table 2, the outputs of the comparators 42, 43, 41 and 44 of the level detection circuit 8 which are the comparison results are as shown in Table 2. The signals CU, CD and WIDE are output.

[0021]

[Table 2]

In Table 2, V ₁₂ ≦ appropriate exposure time area (non-adjustment section) ≦ V ₁₃ , and an area less than voltage V ₁₂ , voltage V
_The area exceeding ₁₃ is a control area and an adjustment area outside the proper exposure time area. This signal CU, CD, WIDE
Is latched and held by the latch circuit 51 in synchronization with the rising of the vertical synchronizing signal VDI. The latched signals CU, CD, WIDE are input to the encoder 52, the encoder 52 determines the comparison result of Table 2 corresponding to the signals CU, CD, WIDE, and outputs the control signal to the storage unit 53. The correction value 1 or n of the predetermined pulse number N of the external control signal OFDX is selected. When a control signal is output from the encoder 52 to the storage unit 53, the selected correction value 1 or n is output to the counter 54. On the other hand, the counter 54 outputs the next external signal immediately after the latch circuit 51 latches the signals CU, CD, WIDE by the correction value 1 or n from the storage unit 53 based on the count-up or count-down control signal from the encoder 52. Count-up or count-down is performed until the pulse of the control signal XSG1 is generated. The count value of the counter 54 is fetched and held in the latch circuit 55 at or immediately before the pulse of the external control signal XSG1 is generated. The count value of the counter 54 when the power is turned on may be set to 1 as an initial value, or may be the median of the count values of the exposure time.
You may set a value around 131.

External control from the SSG2 to the control circuit 56
When the control signal XSG1 is input, the control circuit 56
The built-in counter is reset, and 1 vertical as shown in Fig. 5.
Each time the horizontal synchronizing signal HDI is input from the beginning of the scanning period
An external control signal OFDX is output in synchronization with. Out of this
When the control signal OFDX is output to CCD1, CCD1
Excess charge accumulated in the photo sensor 21 of is not shown
Photo sensor swept to the overflow drain
The charge of 21 becomes empty, that is, becomes empty. Also control circuit
The horizontal sync signal HDI is the count value of the 56 built-in counters.
It counts up each time it is input. Also this count
The value is the count of the counter 54 held in the latch circuit 55.
Of the internal counter of the control circuit 56
The count value matches the value in the latch circuit 55, or the count value is
The external control signal OFDX is output until it reaches the threshold. So
After stopping the output of the external control signal OFDX, one vertical scanning period
Until the external control signal XSG1 is output
During the exposure time, the photo sensor 21 of CCD 1 is charged
Accumulated. Therefore, as shown in Table 2, one vertical scanning period
Signal level value voltage V_AIs the input signal condition V_A>
V₁₁, V_A> V₁₄If so, the difference from the appropriate exposure time range
The external control signal OFDX largely appears during the next vertical scanning period.
2 control output status (N ± n) is output and coarse adjustment is performed.
Input signal condition V ₁₁≧ V_A> V₁₂, V₁₃> V_A≧ V₁₄
If so, the difference from the appropriate exposure time region is small and the control output in Table 2 is
Only the force state (N ± 1) is output and finely adjusted.

According to this structure, the level detection circuit 8 compares the signal level value corresponding to the appropriate exposure time with the signal level range of the output signal of the CCD 1 and accumulates in the photo sensor 21 of the CCD 1 based on the comparison result. Predetermined number of pulses N of the external control signal OFDX for sweeping away the excess charge generated
Correction value 1 or n is selected, and the exposure time is variably set so that the exposure time approaches the appropriate value in accordance with the difference from the appropriate exposure amount, no matter how the light amount to the CCD 1 changes, The exposure time can be quickly and accurately adjusted to an appropriate value, and the performance of the exposure time control circuit of the solid-state imaging device is improved. If the exposure time control circuit of such a solid-state image pickup device is used in, for example, the door horn camera or the like, even if a person stands in front of the camera and suddenly changes in brightness, a television such as a monitor is displayed. Since the brightness of the screen follows this fluctuation, you can always check the image with the brightness that is easy to see.

The count value held in the latch circuit 55 may be input to the encoder 52, the range may be set according to the count value, and the correction value n may be selected. This range is, for example, N = 1 to 100, 100 to 150,
If N> 150, and the count values are within their respective ranges, correction values n = 10, 5, 3 are selected. With this configuration, it is possible to properly select the predetermined number of pulses of the external control signal OFDX.

Further, when the exposure time is short, the change amount of the light amount becomes large if the horizontal period is switched, so that the exposure time is adjusted at intervals of 1 / m (for example, m = 4) of one horizontal scanning period. You may do it. In the embodiment, the CCD of the interline transfer system is used, but the CCD is not limited to this, and of course, the frame transfer system may be used.

[0027]

As described above, according to the present invention, the signal level value of the output signal of the solid-state image pickup device is compared with the signal level range corresponding to the appropriate exposure time by the comparison means, and the control is performed according to the comparison result. Means are coarse adjustment section, fine adjustment section,
The exposure time is determined to be a non-adjustment section, the exposure time is roughly adjusted in the rough adjustment section, the exposure time is finely adjusted in the fine adjustment section, and the current exposure time is held in the non-adjustment section. The adjustment can be performed quickly and accurately, and the performance of the exposure time control circuit of the solid-state imaging device can be improved.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an exposure time control circuit of a solid-state imaging device.

FIG. 2 is a diagram showing a configuration of an interline transfer type CCD.

FIG. 3 is a circuit diagram showing an integration circuit and a level detection circuit of this embodiment.

FIG. 4 is a block diagram showing an exposure time control unit of this embodiment.

FIG. 5 is a signal waveform diagram of FIG.

FIG. 6 is a circuit diagram showing a conventional integrating circuit and level detecting circuit.

[Explanation of symbols]

1 CCD 6 Integration Circuit 7 Exposure Time Control Section 8 Level Detection Circuit 9 Charge Sweep-out Pulse Generation Circuit 2 SSG (Sync.signal generator) 52 Encoder 53 Storage Section 54 Counter 56 Control Circuit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Toshiaki Ishida             Konica Stock, 1 Sakura-cho, Hino City, Tokyo             In the company

Claims (2)

[Claims] 1. A solid-state image sensor for accumulating and photoelectrically converting charges based on an input image, and an integrating means for integrating an output signal of the solid-state image sensor to detect a signal level value. Based on the signal level value detected by the means,
An exposure time control circuit of a solid-state image pickup device for setting an exposure time for accumulating charges in the solid-state image pickup device within a predetermined period, wherein a signal level value detected by the integrating means corresponds to a preset appropriate exposure time. Comparing means for comparing the signal level range with the selected signal level range, and based on the comparison result of the comparing means, when the signal level value detected by the integrating means greatly deviates from the signal level range corresponding to the appropriate exposure time. If the signal level value detected by the integrator is slightly outside the signal level range corresponding to the appropriate exposure time, it is determined as a fine adjustment section. If the exposure time is changed slightly and the signal level value detected by the integrating means is within the signal level range corresponding to the appropriate exposure time, it is determined that there is no adjustment section. Exposure time control circuit of the solid-state imaging device characterized by comprising a control means for holding the current exposure time. 2. A signal output means for outputting to the control means a charge sweep-out signal for making the amount of charge of the solid-state image pickup element null from the beginning of the predetermined period, and a charge sweep-out signal when it is determined to be a rough adjustment section. The output time of the charge is greatly changed, the time when the charge sweep signal is output is changed when it is determined to be the fine adjustment section, and the time when the charge sweep signal is output is not changed when it is determined to be the non-adjustment section. And setting means for variably setting an exposure time for accumulating charges in the solid-state imaging device within the predetermined period by setting a time for outputting the charge sweep-out signal. Item 2. An exposure time control circuit of the solid-state imaging device according to item 1.