JPH06153023A - Pseudo vertical synchronizing signal detection device and monitoring device - Google Patents

Abstract

PURPOSE:To discriminate the presence or absence of a pseudo vertical synchronizing signal by selecting the count period of a counter means counting an equivalent pulse from the start point of a vertical synchronizing signal or the pseudo vertical synchronizing signal as a period shorter than the vertical synchronizing signal. CONSTITUTION:A timer 21 starts counting from the falling point of time of vertical synchronizing pulse VSYNC, and outputs a count period control signal causing the counter 20 to execute a counting operation in a period T1 till it comes to time up. A fall detection circuit 22 outputs a reset signal at the falling point of time of VSYNC and a deciding part 23 is reset. The number of the equivalent pulses in the original vertical synchronizing signal VD is measured by the counting operation against the equivalent pulse of the counter 20 in the period T, and a carrier is outputted. Thus, the decision part 23 decided the vertical synchronizing signal to be original VD and outputs decision SA that the signal is a regular video signal. When a carrier output cannot be obtained, it is decided to be VDE and it is set to be a special video signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monitor device and a pseudo vertical synchronizing signal detecting device mounted on the monitor device.

[0002]

2. Description of the Related Art In recent years, various kinds of information have been superposed within a vertical blanking period of a video signal and transmitted together with the video signal. As the information to be superposed, there are known character multiplex broadcasting information, closed caption signals, video IDs, etc. These are superposed by setting a predetermined horizontal line position in the vertical blanking period.

For example, the closed caption signal is inserted at the position of 21H or 284H in the vertical blanking period, and its form is, as shown in FIG. 12, after the horizontal synchronizing signal HD and the color burst CB, first the clock run-in information is inserted. Are arranged. Clock run-in information,
This is information for generating a bit clock for reading subsequent data. Then, subsequently, the start bit SB and the data bit DB which is the actual character information are arranged.

On the monitor device side such as a television receiver, the closed caption signal thus superposed is decoded, the character to be generated is selected, and superimposed on the video signal to display the image on the screen. As shown in 13, the character information (ABC) is displayed together with the video.

By the way, the monitor device generally includes not only a video signal received by a tuner but also a VTR, for example.
A video signal line-input from the device is also supplied and output as a reproduced video. However, when special reproduction such as high-speed reproduction is performed in the VTR device, the above-mentioned closed caption signal or the like is superimposed on the special reproduction video signal. Data is difficult to decode correctly, and frequent decoding errors are inevitable. For this reason, if the decoded character information is output to the screen as it is, the display becomes very difficult to see, and normally, when the specially reproduced video signal is supplied, the superimposed data is decoded and displayed on the screen. It is preferable not to execute the above output.

In order to determine the execution of the decoding output in this way, the video signal input to the monitor device is, for example, NT.
It is a normal signal (hereinafter referred to as a normal video signal) that is normally received by the SC system or reproduced at a normal speed by the VTR device, or a special video signal such as a high-speed reproduced signal (hereinafter, a special video signal). In some cases, a circuit is provided for determining whether the signal is a video signal).

When performing special reproduction on a VTR,
For example, it is not possible to accurately trace a track recorded on a magnetic tape by a helical scan method (a track inclination angle with respect to the tape width direction is larger in the case of high speed reproduction, and smaller in the case of low speed reproduction). (Although head scanning is performed at an inclination angle), a pseudo vertical synchronization signal is externally added in order to monitor the image output to some extent appropriately even with the image information obtained by this (( Hereinafter, this is referred to as a pseudo vertical synchronization signal). The pseudo vertical sync signal stabilizes the raster of the monitor screen so that the image can be monitored even during special reproduction.

FIG. 14 shows a pseudo vertical synchronizing signal detection circuit provided in a conventional monitor device. _{Reference numeral} 80 denotes a counter for counting the horizontal synchronizing pulse H _SYNC (including the equalizing pulse), 81 denotes a falling edge detecting section for detecting a falling edge of the vertical synchronizing pulse V _SYNC and outputting a reset signal, 82 Indicates a determination unit (flip-flop circuit) that obtains a determination output S _A for determining the presence or absence of the pseudo vertical synchronization signal based on the carry output from the counter 80.

The determination operation of this pseudo vertical sync signal detection circuit will be described with reference to FIG. FIG. 15A is a normal video signal in which the vertical synchronizing signal VD is present in the vertical blanking period VBLK, and FIG. 15B is a pseudo vertical synchronizing signal V in this period.
The special video signal to which DE is added is shown. The determination operation is performed by determining whether or not an equalizing pulse is present as a vertical synchronizing signal.

From the falling edge detecting section 81, the judging section 82 and the counter 80 are reset at the falling timing of the vertical synchronizing signal VD or the pseudo vertical synchronizing signal VDE (FIG. 1).
5 (c)). The counter 80 produces a carry output when the count value of the equivalent pulse reaches 6, for example (FIG. 15).
(D)). When the carry output from the counter 80 is obtained, the determination unit 82 determines that the vertical synchronization signal is the vertical synchronization signal VD and that the determination output S indicates a normal video signal as shown by the solid line in FIG. Output _A.
On the other hand, if no carry output is obtained, the vertical synchronizing signal is assumed to be the pseudo vertical synchronizing signal VDE, and the determination output S _A indicating the special video signal is output as indicated by the dotted line.

[0011]

However, in such a pseudo vertical synchronizing signal detection circuit, a special video signal may be erroneously detected as a normal video signal, and eventually unsightly character information is displayed on the monitor screen. There is a problem that it may end up.

This occurs because the pseudo vertical sync signal VDE is not necessarily added in conformity with the position of the vertical sync signal VD in the vertical blanking period. For example, in FIG.
As shown in FIG. 1A, the pseudo vertical sync signal VDE is shifted forward from the original vertical sync signal VD and overlaps.
As shown in 7 (a), the pseudo vertical sync signal VDE may be added to a position apart from the vertical sync signal VD.

In the case of FIG. 16, the vertical sync pulse V _SYNC and the horizontal sync pulse H _SYNC obtained by the sync separation process are as shown in FIGS. 16 (b) and 16 (c). Here, when the counter 80 is reset (FIG. 16 (d)) due to the fall of the vertical synchronizing pulse V _SYNC , counting continues from the period of the pseudo vertical synchronizing signal VDE to the period of the original vertical synchronizing signal VD. Eventually, the carry pulse is output as shown in FIG. 16E due to the equivalent pulse existing in the original vertical synchronizing signal VD period. Therefore, the determination output S _A is shown in FIG. 16 in spite of the presence of the pseudo vertical synchronization signal VDE.
As shown in (f), the regular video signal is shown.

In the case of FIG. 17, the vertical sync pulse V _SYNC and the horizontal sync pulse H obtained by the sync separation process.
_SYNC is as shown in FIGS. 17 (b) and 17 (c). In this case, the resetting of the counter 80 takes place both at the start time of the pseudo vertical sync signal VDE and the start time of the original vertical sync signal VD as shown in FIG. 17 by the counting operation in FIG.
Carry output is performed as in (e). Therefore, in this case as well, the determination output S _A is the pseudo vertical synchronization signal VD.
Despite the presence of E, the normal video signal is shown as shown in FIG.

[0015]

In view of the above problems, the present invention provides a pseudo vertical sync signal detecting device capable of accurately determining the presence / absence of a pseudo vertical sync signal in a monitor device. It is an object to prevent unsightly decoded output display when a special video signal is output.

Therefore, as a pseudo vertical synchronizing signal detecting device, a counter means for counting equalized pulses in an input video signal and a vertical synchronizing signal for the counter means from the start point of the vertical synchronizing signal or the pseudo vertical synchronizing signal. It is determined whether or not the pseudo vertical synchronizing signal is superimposed on the video signal by the counter control means for controlling the counting operation to be executed only for a predetermined period shorter than the period and the output (carry output) based on the count value of the counter means. And a discriminating means for carrying out.

Further, in this case, the counter control means starts time counting from the start time point of the vertical synchronizing signal or the pseudo vertical synchronizing signal, and counts the counting means until a preset predetermined period elapses. It is composed of timer means for outputting a count period control signal to be executed.

Alternatively, as the counter control means, time counting is started from the start time point of the vertical synchronizing signal or the pseudo vertical synchronizing signal, and a first predetermined period longer than a preset vertical synchronizing signal period elapses. A first timer means for outputting a count period control signal of 1, a first count period control signal, a vertical synchronizing signal and a pseudo vertical synchronizing signal are supplied, and the time count start control signal is provided only at the start time point of the pseudo vertical synchronizing signal. And a counting means for starting time counting from the time when the time counting start control signal is supplied from this gate means and until a second predetermined period shorter than a preset vertical synchronizing signal period elapses. And second timer means for outputting a second count period control signal for executing the count operation.

The monitor device is equipped with such a pseudo vertical synchronizing signal detecting device, and when the pseudo vertical synchronizing signal detecting device detects that the pseudo vertical synchronizing signal is superposed on the video signal, the image is detected. It is configured so that the decoded output of the information superimposed in the vertical blanking period of the signal is not executed.

[0020]

By selecting the counting period of the counter means for counting the equivalent pulse as a period shorter than the vertical synchronizing signal period from the start point of the vertical synchronizing signal or the pseudo vertical synchronizing signal, the pseudo vertical synchronizing signal becomes the original vertical synchronizing signal. Even if they are added with a shift, the counting operation can be accurately executed in correspondence with the period of the pseudo vertical synchronizing signal.

[0021]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a block diagram showing a main part of an embodiment of a monitor device having a pseudo vertical synchronizing signal detecting device of the present invention. Reference numeral 1 denotes a tuner, which receives an antenna reception signal and a reproduced video signal from an external VTR device. The video signal tuned by the tuner 1 is converted into an intermediate frequency by the intermediate frequency amplification unit 2, and Y
It is supplied to the / C processing unit 3 and the sync separation circuit 5.

The Y / C separation circuit 3 separates the supplied composite video signal into a luminance signal and a chrominance signal, and then applies predetermined processing to the luminance signal and the chrominance signal B-, for example.
Matrix processing is performed on Y and R-Y to obtain an R signal,
The G signal and B signal are demodulated. The R signal, G signal, and B signal are amplified by the RGB processing unit 4 to be drive signals for the electron gun, which are supplied to the CRT 9 and output as an image.

On the other hand, in the sync separation circuit 5, the horizontal sync pulse H _SYNC and the vertical sync pulse V are output from the composite video signal.
_SYNC extracted, vertical amplifier 6 and horizontal amplifier 7 respectively
Supply to. The vertical amplifier 6 and the horizontal amplifier 7 generate vertical and horizontal deflection currents from the supplied synchronization pulses and apply them to the deflection coil 8.

Reference numeral 10 surrounded by a chain line indicates the 21st horizontal line or the 284th line in the vertical blanking period of the video signal.
7 shows a caption decoder that decodes a closed caption signal that is superimposed on a horizontal line.

Reference numeral 11 is a clamp circuit for performing clamp processing on the composite video signal, 12 is a comparator for comparing the clamped video signal with a reference voltage of a predetermined level to extract superimposition data, and 13 is a comparator 12. 7 shows a data register that fetches the extracted data at a predetermined timing.

Reference numeral 14 is a sync separation circuit for extracting the horizontal sync pulse H _SYNC and the vertical sync pulse V _SYNC from the composite video signal, and 15 is a timing controller,
The timing controller 15 performs, for example, a counting operation on the horizontal synchronizing pulse H _SYNC and the vertical synchronizing pulse V _SYNC , and outputs based on the timing signal S _TG controlling the fetch timing of the data register 13 and the decoded data fetched by the data register 13. A timing signal S _TD for controlling the timing is output.

That is, the data of 1 or 0 is successively extracted from the comparator 12 by comparing the video signal with the reference voltage, whereas the timing controller 15 outputs the data to the data register 13 as the timing control signal S _TG. On the other hand, when the data acquisition is executed at the timing corresponding to the 21st horizontal line or the 284th horizontal line in the vertical blanking period, the closed caption signal is acquired in the data register 13.

Reference numeral 17 is an on-screen display processing unit (OSD), and this OSD 17 is a data register 1
R is generated by generating a character signal according to, for example, character information as a closed caption signal taken in
It is supplied to the GB processing unit 4. The generation timing of the character signal is controlled by the timing control signal S _TD from the timing controller 15, so that the character display is superimposed at predetermined horizontal and vertical positions on the screen.

Reference numeral 16 is a pseudo vertical synchronizing signal detection circuit,
From the vertical sync pulse V _SYNC and the horizontal sync pulse H _SYNC ,
_A discrimination output S _A for discriminating whether or not the video signal displayed and output by the monitor device is a special video signal to which the pseudo vertical synchronizing signal is added in the vertical blanking period is formed.
The discrimination output S _A is supplied to the OSD 17 and the timing controller 15, and if the pseudo vertical synchronization signal is detected and it is determined that it is a special video signal, the character signal output based on the decoded data from the OSD 17 is not executed. It is configured.

The monitor device of the present embodiment is configured in this manner so that, for example, when outputting a high-speed playback video signal, character information or the like that becomes unsightly due to a decoding error is not displayed.

A first embodiment of the pseudo vertical sync signal detection circuit 16 mounted on this monitor will be described below. FIG. 2 is a block diagram of the pseudo vertical sync signal detection circuit 16, and 20 is a counter for counting the horizontal sync pulse H _SYNC (including the equalization pulse).
For example, a carry output is made when the pulse count value reaches 4. Reference numeral 21 is a timer circuit that measures a predetermined time from the start period (falling point) of the vertical synchronization pulse, and the timer circuit 21 controls the count period to be the count execution period only during the predetermined period from the start period of the vertical synchronization pulse. The signal is supplied to the counter 20. The predetermined time counted by the timer circuit 21 is a period shorter than the vertical synchronization signal period.

Reference numeral 22 is a falling edge detection circuit, which detects the trailing edge of the vertical synchronizing pulse V _SYNC and outputs a reset signal. Reference numeral 23 denotes a determination unit, which is configured to obtain the determination output S _A based on whether or not the carry output is supplied from the counter 20 after being reset by the reset signal from the falling edge detection circuit 22.

The determination operation of the pseudo vertical sync signal detection circuit 16 will be described with reference to FIGS. FIG. 3 shows the case where a normal video signal is input, and the input video signal and vertical sync pulse V _SYNC and horizontal sync pulse H _SYNC are shown in FIG.
(A), (b), and (c). Here, the timer 21 starts time counting from the _{trailing edge} of the vertical synchronizing pulse V _SYNC , and is the period T ₁ until the time is up.
In FIG. 3, a count period control signal for causing the counter 20 to perform a count operation is output as shown in FIG. Further, the falling detection circuit 22 outputs the reset signal of FIG. 3E at the falling time point of the vertical synchronizing pulse V _SYNC , and the determination unit 23 is reset.

By the counting operation for the equalizing pulse of the counter 20 in the period T _1, the number of equalizing pulses in the original vertical synchronizing signal VD is counted, and the carry output is performed as shown in FIG. 3 (f). Therefore, the judging section 23 judges that this vertical synchronizing signal is the original vertical synchronizing signal VD, and makes a judgment output S _A indicating that it is a normal video signal as shown in FIG.

Next, in the case where the pseudo vertical synchronizing signal VDE is added to the original vertical synchronizing signal period in the input video signal as shown in FIG. 4A, the vertical synchronizing pulse shown in FIG. Based on V _SYNC , the timer circuit 21 specifies the count operation period of the T ₁ period (see FIG. 4).
(D)), the counter 20 tries to count the equalized pulses, but during this period, the equalized pulses are not input to the counter 20 as shown in FIG. 4 (c). Therefore, the carry output is not obtained within the period T ₁ (FIG. 4 (f)), and the determination unit 23 determines this as the pseudo vertical synchronization signal VDE, and the carry output shown in FIG.
As shown in (g), the judgment output S _A indicating the special video signal is formed.

Next, as shown in FIG. 5A, when the pseudo vertical sync signal VDE is superimposed on the original vertical sync signal VD with a deviation, the vertical sync pulse V _SYNC and the horizontal sync pulse H _SYNC.
Is as shown in FIGS. Here, the timer 21
Is a count period control signal that causes the counter 20 to perform a count operation as shown in FIG. 5D during the period T ₁ from the time when the vertical synchronizing pulse V _{SYNC falls} to the time when it starts counting up. Will output
Since this period corresponds to the period of the pseudo vertical synchronizing signal VDE, the equalization pulse is not input to the counter 20 and therefore the carry output cannot be obtained (FIG. 5 (f)).
Therefore, the determination unit 23 determines that this is the pseudo vertical synchronization signal VDE.
It is possible to accurately determine that the signal is an added signal, and it is possible to provide a determination output S _A indicating that it is a special video signal as shown in FIG.

As described above, in the pseudo vertical sync signal detection circuit 16 of this embodiment, even if the pseudo vertical sync signal VDE is overlapped and overlapped at a position deviated from the original vertical sync signal VD as shown in FIG. 5A. The presence of the pseudo vertical sync signal VDE can be accurately determined. Therefore, by providing such a pseudo vertical sync signal detection circuit 16 as a monitor device, for example, in the case of high-speed playback video output, the caption becomes unsightly. It is possible to control not to display information and the like.

By the way, normally, the pseudo vertical sync signal detection circuit 16 can sufficiently cope with the non-execution control of the decode output of the caption data in the case of the special video signal, but in some cases, the pseudo vertical sync signal detection circuit 16 is simulated as shown in FIG. Vertical sync signal VDE
May deviate from the original position of the vertical synchronizing signal VD, and the vertical synchronizing pulse V _SYNC may be generated in two units as shown in FIG. 6B.

In this case, the output of the timer 21 is as shown in FIG. 6D, and the counter 20 performs the counting operation in both the pseudo vertical synchronizing signal VDE period and the original vertical synchronizing signal VD period. A carry output is made in the vertical synchronizing signal VD period as shown in (f), and an erroneous determination output S _A that makes this a normal video signal as shown in FIG.
Will be done.

Therefore, as a second embodiment, a description will be given of the pseudo vertical sync signal detection circuit 16 which can perform an accurate determination operation even in such a case. FIG. 7 is a block diagram of the pseudo vertical sync signal detection circuit 16 of this embodiment. Compared with the embodiment of FIG. 2, the timer circuit has 21A and 2A.
1B and 2 units are provided, and a gate circuit (AND gate or NAND gate) 24 is provided, which is a difference.

The timer circuit 21A counts time for a T ₂ period longer than the vertical synchronizing signal VD period, and supplies a first count period control signal to the gate circuit 24 during that time. In addition, the timer circuit 21A counts the time of the T ₃ period shorter than the vertical synchronizing signal VD period, and supplies the second count period control signal to the counter 20 during that time.

The operation of this embodiment will be described with reference to FIGS. FIG. 8 shows a case where a normal video signal is input. Here, as shown in FIG. 8 (d), the timer 21A counts the time of the T ₂ period from the falling point of the vertical synchronizing pulse V _SYNC , and the pulse of L level during that time is the gate circuit 2
4 is supplied. On the other hand, the gate circuit 24 is shown in FIG.
The vertical synchronizing pulse V _{SYNC of is} also supplied, so that the output of the gate circuit 24 becomes as shown in FIG. The timer circuit 21B counts the time T ₃ from the falling edge of the output of the gate circuit 24, and outputs the second count period control signal output to the counter 20 as shown in FIG. .

Since the count execution period of the counter 20 is designated by the second count period control signal, T
Equalized pulse counting is performed only for _three periods. Therefore,
In this case, the number of equalization pulses in the original vertical synchronization signal VD is counted, carry output is performed as shown in FIG. 8 (h), and the determination unit 23 determines that this vertical synchronization signal is the original vertical synchronization signal VD.
8 (i), a determination output S _A indicating that the signal is a normal video signal is obtained.

Next, as shown in FIG. 9A, when the pseudo vertical synchronizing signal VDE is added during the original vertical synchronizing signal period in the input video signal, the timer circuit 21A
And similar operation of the gate circuit 24 (FIGS. 9D and 9E).
Then, the count period of the counter 20 is designated by the output of the timer 21B for the T ₃ period (FIG. 9 (f)), and the counter 20 tries to count the equalized pulses. No equalization pulse is input to the counter 20 as shown. Therefore, no carry output is obtained within the T ₃ period (FIG. 9 (h)), and the determination unit 23 determines that this is the pseudo vertical synchronization signal VDE and determines that it is a special video signal as shown in FIG. 9 (i). The determination output S _A shown is obtained.

Next, when the pseudo vertical synchronizing signal VDE is superimposed on the original vertical synchronizing signal VD with a shift as shown in FIG. 10A, the vertical synchronizing pulse V _SYNC and the horizontal synchronizing pulse H are generated.
_SYNC is as shown in FIGS. Here, the timer 21B is also based on the same operation of the timer circuit 21A and the gate circuit 24 (FIGS. 10D and 10E).
The T ₃ period is designated for the counter 20 (see FIG. 10).
(F)). Since this T ₃ period corresponds to the period of the pseudo vertical synchronizing signal VDE, the equalizing pulse is not input to the counter 20 and therefore the carry output cannot be obtained (FIG. 10 (h)). Therefore, the determination unit 23 can accurately determine this as a signal to which the pseudo vertical synchronization signal VDE is added, and makes a determination output S _A indicating that it is a special video signal as shown in FIG. 10 (i). be able to.

Further, when the pseudo vertical synchronizing signal VDE is largely deviated from the position of the original vertical synchronizing signal VD as shown in FIG. 11A, the vertical synchronizing pulse V _SYNC is generated in two units as shown in FIG. 11B. Will end up. However, in the case of this embodiment, the timer circuit 21B outputs the output of the timer circuit 21A (FIG. 11D) and the vertical synchronizing pulse V _SYNC (FIG. 11).
Since the gate circuit output to which (b)) is supplied is as shown in FIG. 11E, it is pseudo vertical that the timer 21B designates execution of the counting operation in the T ₃ period as shown in FIG. 11F. Only during the period corresponding to the synchronization signal VDE,
The counting operation of the counter 20 is not executed within the original vertical synchronizing signal VD period. Therefore, the carry output cannot be obtained as shown in FIG.
Then, this can be accurately determined as a signal to which the pseudo vertical synchronizing signal VDE is added, and a determination output S _A indicating that it is a special video signal can be provided as shown in FIG. 11 (i).

Pseudo-vertical sync signal detector 1 of this embodiment
By mounting 6 on a monitor device and controlling the presence or absence of decoding output of a closed caption signal, for example, unsightly display output due to a decoding error in the case of a special video signal is completely prevented.

In the embodiment, the pseudo vertical synchronizing signal detecting device provided in the decoder for the closed caption signal has been described as an example, but the present invention is not limited to this, and a decoder for other superimposed data such as a decoder for character multiplex broadcasting information. It is needless to say that the pseudo vertical synchronizing signal detecting device in (1) can also be realized.

[0049]

As described above, according to the present invention, the counting period of the counter means for counting the equivalent pulse is selected as a period shorter than the vertical synchronizing signal period from the start point of the vertical synchronizing signal or the pseudo vertical synchronizing signal. Even if the pseudo vertical sync signal is added with a deviation from the original vertical sync signal, the counting operation of the equalization pulse can be accurately executed in correspondence with the period of the pseudo vertical sync signal. There is an effect that it can be accurately determined.

Therefore, in a monitor device equipped with such a pseudo vertical synchronizing signal detecting device, the data superimposed in the vertical blanking period is judged based on the discrimination of the special video signal or the normal video signal depending on the presence or absence of the pseudo vertical synchronizing signal. Execution / non-execution of decoding output can be appropriately controlled, and it is possible to prevent the display of character information or the like that becomes unsightly due to a decoding error when a special video signal is input.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of an embodiment of a monitor device of the present invention.

FIG. 2 is a block diagram of a first embodiment of a pseudo vertical synchronizing signal detecting device of the present invention.

FIG. 3 is an explanatory diagram of a discriminating operation of the first embodiment of the pseudo vertical synchronizing signal detecting device.

FIG. 4 is an explanatory diagram of a discrimination operation of the first embodiment of the pseudo vertical synchronization signal detection device.

FIG. 5 is an explanatory diagram of a discrimination operation of the first embodiment of the pseudo vertical synchronization signal detection device.

FIG. 6 is an explanatory diagram of misjudgment at the time of the discrimination operation of the first embodiment of the pseudo vertical synchronization signal detection device.

FIG. 7 is a block diagram of a second embodiment of the pseudo vertical synchronization signal detection device of the present invention.

FIG. 8 is an explanatory diagram of a discrimination operation of the second embodiment of the pseudo vertical synchronization signal detection device.

FIG. 9 is an explanatory diagram of a discrimination operation of the second embodiment of the pseudo vertical synchronization signal detection device.

FIG. 10 is an explanatory diagram of a discrimination operation of the second embodiment of the pseudo vertical synchronization signal detection device.

FIG. 11 is an explanatory diagram of a discrimination operation of the second embodiment of the pseudo vertical synchronization signal detection device.

FIG. 12 is an explanatory diagram of a closed caption signal.

FIG. 13 is an explanatory diagram of superimposing with a closed caption signal.

FIG. 14 is a block diagram of a conventional pseudo vertical synchronization signal detection device.

FIG. 15 is an explanatory diagram of a discrimination operation of a conventional pseudo vertical synchronization signal detection device.

FIG. 16 is an explanatory diagram of misjudgment at the time of the discrimination operation of the conventional pseudo vertical synchronization signal detection device.

FIG. 17 is an explanatory diagram of misjudgment in the discrimination operation of the conventional pseudo vertical synchronization signal detection device.

[Explanation of symbols]

 10 Caption Decoder 11 Clamp Circuit 12 Comparator 13 Data Register 14 Sync Separation Circuit 15 Timing Controller 16 Pseudo Vertical Sync Signal Detection Circuit 17 OSD 20 Counters 21, 21A, 21B Timer Circuit 22 Falling Edge Detection Circuit 23 Judgment Section 24 Gate Circuit

Claims (4)

[Claims] 1. A counter means for counting equalized pulses in an input video signal, and a counting operation for said counter means only for a predetermined period shorter than a vertical sync signal period from the start of a vertical sync signal or a pseudo vertical sync signal. A counter control means for controlling so as to be executed, and a discrimination means for discriminating whether or not the pseudo vertical synchronizing signal is superimposed on the video signal by the output based on the count value of the counter means. Characteristic pseudo vertical synchronization signal detection device. 2. The counter control means starts time counting from the start time point of the vertical synchronizing signal or the pseudo vertical synchronizing signal, and performs a counting operation on the counting means until a preset predetermined period elapses. The pseudo vertical synchronizing signal detecting device according to claim 1, wherein the pseudo vertical synchronizing signal detecting device comprises a timer means for outputting a count period control signal. 3. The counter control means starts time counting from the start time point of the vertical synchronizing signal or the pseudo vertical synchronizing signal, and starts the first counting until a first predetermined period longer than a preset vertical synchronizing signal period elapses. First timer means for outputting a count period control signal, the first count period control signal, a vertical synchronizing signal and a pseudo vertical synchronizing signal are supplied, and a time count start control signal is provided only at the start point of the pseudo vertical synchronizing signal. And a count means for starting time counting from the time when the time count start control signal is supplied from the gate means until a second predetermined period shorter than a preset vertical synchronization signal period elapses. Second timer means for outputting a second count period control signal for executing a count operation for Pseudo vertical sync signal detection apparatus according to claim 1, wherein. 4. A counter means for counting equalized pulses in an input video signal, and a counting operation for a predetermined period shorter than a vertical sync signal period from the start point of the vertical sync signal or the pseudo vertical sync signal with respect to the counter means. And a determination means for determining whether or not the pseudo vertical synchronization signal is superposed on the video signal by the output based on the count value of the counter means. A detection device is provided, and when the pseudo vertical synchronization signal detection device detects that the pseudo vertical synchronization signal is superimposed on the video signal, the decoding output of the information superimposed in the vertical blanking period of the video signal is not executed. A monitor device having the following configuration.