JP3365569B2 - Closed caption receiver - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a repetitive signal indicating the phase and amplitude of a binarized signal and a closed caption signal including the binarized signal following the repetitive signal, which is superimposed during a vertical blanking period. The present invention relates to a closed caption receiving device that extracts the closed caption signal from a television signal that is present and decodes the closed caption signal.

[0002]

2. Description of the Related Art Currently, a system for transmitting various information by superimposing a binarized signal during a vertical blanking period of a television signal has been realized. As one of the systems, information such as characters and figures is transmitted. Teletext to be transmitted is provided. In the United States, in particular, subtitled broadcasting called closed captioning has been provided since 1980.

In the closed caption system, the closed caption signal is superimposed on, for example, the line 21 during the vertical blanking period of the first field of the television signal,
The closed caption signal is decoded and the character information obtained by this decoding is displayed on the screen of the television receiver while being superimposed on the image. This closed caption caption signal is, as shown in FIG.
It is composed of a packet of a clock run-in signal (hereinafter referred to as a CRI signal) added to the head thereof, a start bit, and a binarized signal indicating binarized information data. The CRI signal is a repetitive signal indicating the phase and amplitude of the data and the start bit, and the start bit is bit data of "001" indicating the start of the binarized signal.

In the closed caption receiving apparatus for receiving this closed caption broadcast, a slice for extracting a binarized signal included in the closed caption signal from the closed caption signal superimposed during the vertical blanking period. By performing processing, the distorted binarized signal is waveform-shaped into a regular binarized signal, and the binarized signal is decoded to obtain character information.

Next, this closed caption receiver will be described with reference to the drawings. FIG. 9 is a block diagram showing a conventional closed caption receiver.

The closed caption receiver is shown in FIG.
As shown in FIG. 3, a comparator 2 for inputting a video signal from the input terminal 1 is provided. The comparator 2 compares the voltage of the video signal input thereto with the reference voltage. When the voltage of the video signal is higher than the reference voltage, the "H" level slice signal is output, and when the voltage of the video signal is lower than the reference voltage, the "L" level slice signal is output.

The slice signal from the comparator 2 is CR
It is applied to the I gate circuit 3 and the output terminal 4. A CRI gate pulse is input to the CRI gate circuit 3 via the terminal 5. The CRI gate pulse is generated with reference to the horizontal synchronizing signal of the video signal, and its pulse width is preset so as to correspond to the input period of the CRI signal. The CRI gate circuit 3 takes in and outputs the slice signal during the input period of the CRI signal indicated by the CRI gate pulse. CR
The slice signal output from the I gate circuit 3 is a binarized signal corresponding to the CRI signal.

The slice signal from the CRI gate circuit 3 is an up / down counter (hereinafter referred to as a U / D counter).
Given to 6. The U / D counter 6 operates with a system clock that is sufficiently faster than the cycle of the CRI signal, and counts according to the logic level of the slice signal from the CRI gate circuit 3. When the slice signal from the CRI gate circuit 3 is at "H" level, the count value rises, and when the slice signal is at "L" level, the count value decreases. The system clock given to the U / D counter 6 is generated by the clock generator 7.

The count value of the U / D counter 6 is given to a digital / analog converter (hereinafter, D / A converter) 8. The D / A converter 8 converts the count value of the U / D counter 6 into a corresponding voltage, and supplies this voltage to the comparator 2 as a reference voltage.

Next, the operation of the closed caption receiver will be described with reference to the drawings. FIG. 10 shows FIG.
3 is a time chart showing a CRI signal waveform, a CRI gate pulse, and a slice signal used for explaining the operation of the closed caption receiving device of FIG.

Referring to FIG. 10A, first, the comparator 2 performs a slicing process on the video signal by comparing the voltage of the video signal with a reference voltage (slice level). By this slicing process, FIG.
As shown in (c), a slice signal is generated. Next, as shown in FIG. 10B, the CRI gate circuit 3 is supplied with an “H” level CRI gate pulse indicating that it is in the input period of the CRI signal. During the input period of the CRI signal indicated by the CRI gate pulse, the CRI gate circuit 3 fetches the slice signal corresponding to the CRI signal from the comparator 2 and outputs this slice signal to the U / D counter 6. The U / D counter 6 operates in synchronization with the system clock from the clock generator 7, and increases or decreases the count value according to the logic level of the slice signal.

During the input period of the CRI signal, the count value of the U / D counter 6 fluctuates up and down according to the amplitude of the CRI signal, and the reference voltage changes with the fluctuation of the count value. That is, the slice level for the video signal changes due to the change in the reference voltage.

When the CRI signal input period shifts to the start bit period, the logic level of the CRI gate pulse shifts from the "H" level period to the "L" level period, and CR.
The I gate circuit 3 stops its output. The U / D counter 6 stops operating as the output of the CRI gate circuit 3 stops. When the operation of the U / D counter 6 is stopped, the U / D counter 6 holds the final count value, and this count value is D
It is given to the / A converter 8.

The D / A converter 8 converts the final count value of the U / D counter 6 into a corresponding voltage, and this voltage is given to the comparator 2 as a reference voltage. The reference voltage of the comparator 2 is held at the voltage corresponding to the final count value of the U / D counter 6. The reference voltage corresponding to this final count value, that is, the slice level, corresponds approximately to the center value of the amplitude of the CRI signal. Therefore, the data portion following the CRI signal of the video signal can be processed by the optimum slice level.

Next, a method of generating a CRI gate pulse will be described.

As one of the methods of generating the CRI gate pulse, there is a method of raising the CRI gate pulse based on the horizontal synchronizing signal of the video signal, detecting the CRI signal for 7 clocks, and then lowering the CRI gate pulse.

As another method of generating a CRI gate pulse, when the CRI gate pulse is raised on the basis of the horizontal synchronizing signal of the video signal and the "L" level period continuing for a predetermined period is detected, this period is followed by the CRI signal. There is a method of determining that the period corresponds to the subsequent start bit and lowering the CRI gate pulse.

However, in the television signal in the weak electric field, the television signal including the influence of the ghost signal, or the reproduction signal of the abnormal VTR due to the loss of the recording tape, a part of the CRI signal is missing or C
When the RI signal is significantly distorted, the amplitude of part of the CRI signal may decrease. Further, in commercially available video software, a CRI signal having a predetermined number of clocks may not be inserted, for example, the clock number of the CRI signal is 6 clocks or less. Further, the overshoot of the horizontal synchronizing signal may be erroneously determined as the CRI signal.

In each of the above cases, the former CRI gate pulse generation method cannot accurately detect the CRI signal for 7 clocks, and the latter CRI gate pulse generation method accurately detects the start bit period. However, the CRI gate pulse generation method cannot generate the CRI gate pulse that accurately indicates the input period of the CRI signal. Therefore, the detection accuracy of the CRI signal is reduced, which may cause a malfunction.

A copy guard signal (eg, 10) for preventing dubbing of a normal video signal or commercially available video software is provided on the line 21 during the vertical blanking period of the first field, which is the target of superimposing the closed caption signal.
When a 0% white level AGC signal or the like) or a scramble signal used for providing a pay program is inserted, a malfunction may occur as in each of the cases described above.

Further, regardless of the method of creating the CRI gate pulse, when the initial value of the reference voltage (the initial value of the slice level) is too low or too high with respect to the amplitude of the CRI signal, the detection accuracy of the CRI signal decreases, It may cause malfunction.

[0022]

As described above, in the conventional closed caption receiver, the CRI gate pulse indicating the CRI signal input period is not accurately generated when the CRI signal is deformed or lost. Alternatively, since the initial value of the slice level is not properly set with respect to the amplitude of the CRI signal, the detection accuracy of the CRI signal may be reduced, which may cause a malfunction.

According to the present invention, the CRI signal input period is set accurately, or the initial value of the slice level for the CRI signal is optimally set.
It is an object of the present invention to provide a closed caption receiving device that can improve signal detection accuracy and can prevent malfunction due to low CRI signal detection accuracy.

[0024]

According to a first aspect of the present invention, there is provided a closed caption receiving apparatus which comprises a repetitive signal indicating the phase and amplitude of a binarized signal, a logic signal following the repetitive signal, and a logic signal after the logic signal. A closed caption receiving device that extracts the closed caption signal from a television signal on which a closed caption signal including the subsequent binarized signal is superimposed during a vertical blanking period, and performs a decoding process on the closed caption signal. Then, slicer means for performing slice processing on the television signal by comparing the voltage of the television signal with a reference voltage, and slicer means for generating a slice signal, and capturing means for capturing the slice signal generated by the slicer means. , Is the slice signal acquired by the acquisition means? Counting means for counting the number of clocks of the repetitive signal, logic level detecting means for detecting a logic level period of the logic signal from the slice signal taken in by the taking means, and the repetitive signal counted by the counting means When the number of clocks is equal to or more than a predetermined set number smaller than the number of repetitions of the repetitive signal and the logic level period detected by the logic level detection means is more than the set period, the slice signal corresponding to the repetitive signal The present invention is characterized in that it is provided with a control means for determining that the capture to the capture means has ended, and for instructing the capture means to stop the capture operation for the slice signal based on this determination. The closed caption receiving device according to item 4,
Television in which a closed caption signal including a repetitive signal indicating the phase and amplitude of the binarized signal, a logic signal following the repetitive signal, and the binarized signal following the logic signal is superimposed during the vertical blanking period. Taking out the closed caption signal from the television signal, a closed caption receiving device for performing a decoding process for the closed caption signal, by performing a slicing process for this television signal by comparing the voltage of the television signal with a reference voltage. And slicer means for generating a slice signal, capturing means for capturing the slice signal generated by the slicer means, and counting means for counting the number of clocks of the repetitive signal from the slice signal captured by the capturing means. , The slice signal captured by the capturing means Level change detecting means for detecting the presence or absence of level change, comparing the number of clocks of the repetitive signal counted by the counting means with the number of repetitions of the repetitive signal, and depending on the detection result of the level change detecting means. And processing means for changing the initial value of the reference voltage of the slicer means.

[0025]

[0026]

[Operation] In the closed caption receiver of the first invention of the present application, the number of clocks of the repetitive signal counted by the counting means is equal to or more than a set number, and the logic level period detected by the logic level detection means is a set period. When it is above, it is determined that the acquisition of the slice signal corresponding to the repetitive signal to the acquisition unit is completed, and based on this determination, the acquisition unit is instructed to stop the acquisition operation for the slice signal. .

When the number of clocks of the repetitive signal counted by the counting means is equal to or greater than a set number and the logical level period detected by the logical level detection means is equal to or greater than the set period, the acquisition means includes the slice means. Since the capturing operation for the signal is stopped, the capturing stop timing of the capturing means is the time when the input period of the CRI signal is finished, and the capturing period for the CRI signal that is partially missing or deformed is accurate. Is set to. Therefore, it is possible to improve the detection accuracy of the CRI signal and prevent a malfunction due to the low detection accuracy of the CRI signal.

In the closed caption receiver of the second invention of the present application, the initial value of the reference voltage of the slicer means is determined according to the number of clocks of the repetitive signal counted by the counting means and the detection result of the level change detecting means. To change.

Since the initial value of the reference voltage of the slicer means is changed according to the number of clocks of the repetitive signal counted by the counting means and the detection result of the level change detecting means, a part is missing. The initial value of the slice level for the deformed CRI signal is optimally set. Therefore, the detection accuracy of the CRI signal can be improved, and the CRI
It is possible to prevent malfunction due to low signal detection accuracy.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the closed caption receiving apparatus of the first invention of the present application.

The closed caption receiver is shown in FIG.
As shown in, a comparator 2 for taking in a video signal from the input terminal 1 is provided. The comparator 2 compares the voltage of the video signal with the reference voltage. When the voltage of the video signal is higher than the reference voltage, a slice signal of “H” level is output, and when the voltage of the video signal is lower than the reference voltage,
The "L" level slice signal is output.

The video signal includes a closed caption signal that is superimposed during the vertical blanking period, and this closed caption signal is added to the head portion of C.
It is composed of a packet of an RI signal, a start bit, and binarized information data. The CRI signal is a repetitive signal indicating the phase and amplitude of the data and the start bit, and the start bit is bit data indicating the start of the data.

The slice signal from the comparator 2 is CR
It is applied to I gate circuit 3 and output terminal 4. CRI
The gate circuit 3 starts a slice signal capturing operation and an output operation of the captured slice signal when a CRI gate start pulse is input through the terminal 5, and an AND circuit 14 to be described later outputs a CRI gate end pulse. The input operation and output operation of the slice signal are stopped when is input.

The slice signal corresponding to the CRI signal from the CRI gate circuit 3 is the fall detection circuit 11 and U / D.
It is given to the counter 6.

The falling edge detection circuit 11 detects the falling edge of the slice signal corresponding to the CRI signal and outputs the detection result.

The detection result of the fall detection circuit 11 is given to the CRI number counter 12. The CRI number counter 12
The falling edge of the slice signal is counted and the value is output as the number of clocks of the CRI signal.

CRI counted by the CRI number counter 12
The number of clocks of the signal is microcomputer 13 and A
Given to the ND circuit 14, the microcomputer 13 executes a predetermined process based on the number of clocks of the CRI signal.

The microcomputer 13 is set with a process of changing the initial value of the slice level, a process of determining whether to perform a decoding process, and a process of determining whether to display character information on the screen of the television receiver. Has been done.

The U / D counter 6 operates with a clock of about 8 MHz from the clock generator 7, and performs up-counting operation and down-counting operation according to the logic level of the slice signal corresponding to the CRI signal. When the U / D counter 6 continuously counts down a predetermined number of times,
A start bit detection signal indicating a transition to a start bit period subsequent to the CRI signal is generated. For example, CR
Since the I signal is a sine wave of 7 consecutive clocks of about 503 KHz, the counter value "16" of the U / D counter 6 corresponds to about 1 cycle of the CRI signal. Therefore, about 8MHz
When the U / D counter 6 operating with the system clock of 16 counts down 16 times in a row, it is determined from the count value that the CRI signal input period has ended and the start bit period has been entered. A start bit detection signal is generated from the result of (1).

The count value from the U / D counter 6 is D /
The voltage is given to the A converter 8, and the D / A converter 8 converts it into a voltage corresponding to the count value from the U / D counter 6, and this voltage is given to the comparator 2 as a reference voltage.

The start bit detection signal from the U / D counter 6 is given to the AND circuit 14. AND circuit 14
Outputs a CRI gate end pulse indicating the end of the input period of the CRI signal to the CRI gate circuit 3 when the start bit detection signal is input and the number of clocks of the CRI signal from the CRI number counter 12 indicates two or more clocks. To do.

Next, the operation of the closed caption receiver will be described with reference to the drawings. FIG. 2 shows the CRI signal waveform and slice level, the CRI gate start pulse and the CRI gate end pulse, the slice signal, the output value of the CRI number counter 12 and the U / D counter 6 used for explaining the operation of the closed caption receiver of FIG. It is a time chart which shows an output waveform.

Referring to FIG. 2A, the voltage of the video signal is first compared with the reference voltage by the comparator 2. As a result of this comparison, a slice signal of the binarized signal is generated as shown in FIG. Slice signal is C
It is given to the RI gate circuit 3. As shown in FIG. 2B, a CRI gate start pulse is input to the CRI gate circuit 3 via the terminal 5, and the CRI gate circuit 3 is CR.
The acquisition of the slice signal corresponding to the I signal is started.

The slice signal output from the CRI gate circuit 3 is the falling edge detection circuit 11 and the U / D counter 6
Given to. The falling edge detection circuit 11 detects the falling edge of the slice signal corresponding to the CRI signal and outputs the detection result.

The detection result of the fall detection circuit 11 is given to the CRI number counter 12. The CRI number counter 12
As shown in FIG. 2D, the trailing edge of the slice signal is counted and the value is output as the number of clocks of the CRI signal.

CRI counted by the CRI number counter 12
The number of clocks of the signal is microcomputer 13 and A
Given to the ND circuit 14, the microcomputer 13 selects and executes a process based on the number of clocks of the CRI signal.

As shown in FIG. 2 (e), the U / D counter 6 performs up-counting operation and down-counting operation according to the logic level period of the slice signal corresponding to the CRI signal. When the U / D counter 6 continuously counts down 16 times, a start bit detection signal indicating transition to the start bit period following the CRI signal is generated.

The count value from the U / D counter 16 is D
It is given to the / A converter 7, and the D / A converter 7 converts it into a voltage corresponding to the count value from the U / D counter 16, and this voltage is given to the comparator 2 as a reference voltage.

The start bit detection signal from the U / D counter 6 is given to the AND circuit 14. AND circuit 14
2B, when the start bit detection signal is input and the number of clocks of the CRI signal from the CRI number counter 12 indicates 2 or more clocks,
A CRI gate end pulse indicating the end of the signal input period is output to the CRI gate circuit 3.

The CRI gate circuit 3 stops the acquisition of the slice signal and the output thereof based on the CRI gate end pulse.

From the above, the number of clocks of the CRI signal is 2
When the above and the number of consecutive down counts of the U / D counter 6 is 16 or more, the CRI gate circuit 3 stops the capturing operation for the slice signal by the input of the CRI gate end pulse, so that a part is missing, Deformed C
The capture period for the RI signal is set accurately. Therefore, the detection accuracy of the CRI signal can be improved, and the CRI
It is possible to prevent malfunction due to low signal detection accuracy.

Next, the processing of the microcomputer 13 will be described with reference to the drawings. 3 is a flow chart for explaining the processing operation of the microcomputer of the closed caption receiving apparatus of FIG. 1, and FIG. 4 is the clock number of the CRI signal used for explaining the processing operation of the microcomputer of the closed caption receiving apparatus of FIG. CR
It is a figure which shows the relationship with an I signal waveform.

After the start of receiving the video signal on which the closed caption signal is superimposed, as shown in FIG. 3, the microcomputer 13 first monitors whether or not the CRI gate end pulse is generated (step 101). CRI
When the generation of the gate end pulse is confirmed, the microcomputer 13 reads the count value of the CRI number counter 12 (step 102) and determines whether the clock number of the CRI signal is 2 or less (step 103). .

When it is determined that the clock number of the CRI signal is greater than 2, it is determined whether the clock number of the CRI signal is 8 or more (step 104), and the clock number of the CRI signal is less than 8. If it is determined that the number of clocks of the CRI signal is in the range of 3 to 6, it is determined (step 105).

When it is determined that the clock number of the CRI signal is not within the range of 3 to 6, it is determined that the clock number of the CRI signal is 7 (step 106). Next, the execution of the decoding process is instructed (step 115), and it is determined whether or not the reception process of the next field is performed (step 116). When the reception process is continued, monitoring of the CRI gate end pulse is started again (step 10).
1). On the other hand, when the reception process is stopped, the reception operation for the closed caption signal ends.

Next, when the number of clocks of the CRI signal is 2 or less (step 103), for example, as shown in FIG. 4A, the CRI signal has a small amplitude in the video signal such as a weak electric field, so that the CRI signal has a small amplitude. The signal may not be detected, or the initial value of the slice level may be set high so that the CRI signal cannot be sliced.
An instruction to lower the initial value of the slice level is issued to the U / D counter 6 (step 107), and the cause described above can be removed in the next field. Then CRI
Since the number of signal clocks is small, an instruction to stop the decoding process is issued (step 110), and an instruction to erase the character information from the screen of the television receiver is issued (step 111).

After the instruction to erase the character information is issued, it is determined whether or not the receiving process of the next field is performed (step 116). When the receiving process of the next field is performed, the initial value of the slice level is lowered,
Slice processing is reliably performed on the CRI signal, and the CRI signal having a predetermined number of clocks can be detected.
Therefore, accurate decoding processing can be executed, and predetermined character information can be displayed on the screen of the television receiver.

Another cause of the small number of detection clocks, such as the number of CRI signal clocks being 2 or less, is that, for example, as shown in FIG. 4B, a horizontal line in which the number of clocks of the CRI signal is detected is detected. The signal is a copy guard signal (for example, 1
When it is considered to be a scrambled signal used for providing a paid program, etc., it is impossible to perform decoding processing, and therefore an instruction to stop decoding processing is issued ( Step 11
0), an instruction is issued to erase the character information from the screen of the television receiver (step 111).

Next, when the number of clocks of the CRI signal is 8 or more (step 104), the reason why this number of clocks is larger than a predetermined value is, for example, as shown in FIG. CRI due to low
Since it is considered that overshoot, noise, etc. of the horizontal synchronizing signal other than the signal are detected as the CRI signal, an instruction to increase the initial value of the slice level is issued to the U / D counter 6 (step 108). Then CRI
Since the number of clocks of the signal is larger than the predetermined value, an instruction to stop the decoding process is issued (step 110), and an instruction to erase the character information from the screen of the television receiver is issued (step 111).

After the deletion instruction of the character information is issued, it is determined whether or not the receiving process of the next field is performed (step 116). When the receiving process of the next field is performed, the initial value of the slice level is raised,
Slice processing is reliably performed on the CRI signal, and the CRI signal having a predetermined number of clocks can be detected.
Therefore, accurate decoding processing can be executed, and predetermined character information can be displayed on the screen of the television receiver.

Next, the clock number of the CRI signal is 3 to 6
(Step 105), it is determined whether the number of clocks of the CRI signal in each field is within the range of 3 to 6 for a predetermined number of times (step 109).

When the number of clocks of the CRI signal is not in the range of 3 to 6 for a predetermined number of times consecutively, the initial value of the slice level for the next field is lowered (step 112). The clock number of this CRI signal is 3
As a cause of falling within the range from 6 to 6, the slice value cannot be sliced for several clocks of the CRI signal because the initial value of the slice level is too high.
It is conceivable that a few clocks at the beginning of the RI signal are missing, or as shown in FIG. 4D, the amplitude of a few clocks near the beginning of the CRI signal becomes smaller due to distortion or the like. By lowering the initial value of the slice level for the field of, the slice processing for the CRI signal is surely performed, and C of a predetermined number of clocks is obtained.
The RI signal can be detected. Therefore, accurate decoding processing can be executed, and predetermined character information can be displayed on the screen of the television receiver.

Then, it is judged whether or not the decoding process is possible by the CRI signal having the clock number within the range of 3 to 6 (step 113). When it is determined that the decoding process is possible, the execution of the process indicating with an indicator that the reception state is poor is instructed (step 114), and the execution of the decoding process is instructed (step 115).

When it is determined that the decoding process is impossible, an instruction to stop the decoding process is issued (step 110) and an instruction to erase the character information from the screen of the television receiver is given (step 111). ).

When the number of clocks of the CRI signal is in the range of 3 to 6 for a predetermined number of times (step 1
09), the process of lowering the initial value of the slice level is not performed so that the slice level in the next field does not decrease too much.

The above-mentioned processes are repeated until the reception operation of the closed caption signal is stopped.

Therefore, the process of changing the initial value of the slice level, the process of determining whether to perform the decoding process, and the process of determining whether to display the character information on the screen of the television receiver include the number of clocks of the CRI signal. Therefore, it is possible to prevent different character information or the like from being erroneously displayed on the screen of the television receiver for an abnormal caption signal, a received signal different from the caption signal, or the like.

In the present embodiment, if the down count by the U / D counter 6 continues 16 times, it is determined that the CRI signal input period has shifted to the start bit input period, but instead of this, U / D When the continuous down count number of the D counter 6 reaches 24 times, it is determined that the start bit period has been entered, so that it is started when slice processing cannot be performed due to a part of the CRI signal being lost or the amplitude being lowered. It is possible to eliminate a misjudgment for the bit period. Further, since the "L" level period of the start bit corresponds to 32 counts, the waveform distortion of the CRI signal is taken into consideration in this determination by using, for example, 30 consecutive down-counts to determine the transition to the start bit period. It will be more practical.

Further, in this embodiment, the number of clocks of the CRI signal is calculated by detecting the falling edge of the CRI signal. However, after the detection of one falling edge of the CRI signal, the next falling edge is detected. It is preferable to add a method of determining whether or not the received signal is the CRI signal by detecting the period until the detection. By adding this determination method, the number of clocks of the CRI signal is 3 to 6
It is possible to further prevent erroneous display that occurs when the value is in the range.

Next, another closed caption receiving apparatus will be described with reference to the drawings. FIG. 5 shows the second aspect of the present application.
It is a block diagram which shows one Example of the closed caption receiver of invention.

The closed caption receiver is shown in FIG.
As shown in, a comparator 2 for taking in a video signal from the input terminal 1 is provided. The comparator 2 compares the voltage of the video signal with the reference voltage. When the voltage of the video signal is higher than the reference voltage, a slice signal of “H” level is output, and when the voltage of the video signal is lower than the reference voltage,
The "L" level slice signal is output.

The slice signal from the comparator 2 is CR
It is applied to I gate circuit 3 and output terminal 4. CRI
A CRI gate start pulse is input to the gate circuit 3 via the terminal 5, and the CRI gate circuit 3 starts the slice signal acquisition operation and the output operation of the acquired slice signal by the CRI gate start pull, and the AND circuit. 1
The CRI gate end pulse from 4 stops the slice signal acquisition and output operations.

The slice signal corresponding to the CRI signal from the CRI gate circuit 3 is given to the CRI start detection circuit 21, the fall detection circuit 11 and the U / D counter 6.

The CRI start detection circuit 21 includes an AND circuit 2
2 and a flip-flop (hereinafter referred to as FF) 23. A gate signal near the CRI start is input to the AND circuit 22 via the terminal 24 together with the slice signal,
The AND circuit 22 calculates the logical product of the gate signal near the start of CRI and the slice signal, and outputs a signal indicating the result. The gate signal near the start of the CRI is a pulse signal that rises almost from the start of the CRI signal and has a width of three cycles of the CRI signal. In the present embodiment, the width of the gate signal near the start of the CRI signal is set to three cycles, but instead of this, a gate signal near the start of CRI having a predetermined width such as a width of two cycles is used. Can be used.

The output signal from the AND circuit 22 is FF23.
To the FF 23 as a clock signal, and the FF 23 controls the CR depending on whether or not the signal taken in as the clock signal rises.
Controls the output level of the I start signal. When the rising edge of the signal fetched as the clock signal is detected, that is, when the CRI signal is detected, the "H" level CRI is detected.
When the start signal is output and the rising edge of the signal taken in as the clock signal is not detected, that is, when the CRI signal is not detected, the "L" level CRI start signal is output. The CRI start signal is given to the microcomputer 25 described later.

The falling edge detection circuit 11 detects the falling edge of the slice signal corresponding to the CRI signal, and outputs the detection result as C
Output to the RI number counter 12. CRI number counter 12
Counts the falling edge of the slice signal and outputs the value as the number of clocks of the CRI signal.

CRI counted by the CRI number counter 12
The number of signal clocks is determined by the duty ratio detection circuit 26 described later.
Is supplied to the microcomputer 25 together with the duty ratio signal from. The microcomputer 25 is a CRI
Predetermined processing is executed based on the number of clocks of the signal, the CRI start signal, and the duty ratio signal.

The microcomputer 25 is set with a process of changing the initial value of the slice level, a process of determining whether to perform a decoding process, and a process of determining whether to display character information on the screen of the television receiver. Has been done.

The U / D counter 6 operates with the clock from the clock generator 7 and performs up-counting operation and down-counting operation according to the logic level of the slice signal corresponding to the CRI signal.

The count value from the U / D counter 6 is given to the duty ratio detection circuit 26 and the D / A converter 8. The duty ratio detection circuit 26 detects whether or not the count value of the U / D counter 6 at the end of the CRI gate is larger than a preset predetermined value, and based on the result of the detection, a slice signal corresponding to the CRI signal. "H"
A duty ratio signal indicating the difference between the level period and the “L” level period is generated. The duty ratio signal is given to the microcomputer 25.

The D / A converter 8 converts into a voltage corresponding to the count value from the U / D counter 6, and this voltage is given to the comparator 2 as a reference voltage.

Next, the processing of the microcomputer 25 will be described with reference to the drawings. 6 is a flow chart for explaining the processing operation of the microcomputer of the closed caption receiving apparatus of FIG. 5, and FIG. 7 shows the number of clocks of the CRI signal used for explaining the processing operation of the microcomputer of the closed caption receiving apparatus of FIG. CR
It is a figure which shows the relationship with an I signal waveform.

After the start of the reception of the video signal on which the closed caption signal is superimposed, as shown in FIG. 6, the microcomputer 25 first monitors whether or not the CRI gate end pulse is generated (step 201). CRI
When the generation of the gate end pulse is confirmed, the microcomputer 13 reads the count value of the CRI number counter 12 (step 202) and the CRI start signal (step 203).

Next, it is judged whether the number of clocks of the CRI signal is 2 or less (step 204).

When it is determined that the number of clocks of the CRI signal is greater than 2, it is determined whether the number of clocks of the CRI signal is 8 or more (step 205), and the number of clocks of the CRI signal is less than 8. If it is determined, it is determined whether the clock number of the CRI signal is in the range of 3 to 6 (step 206).

When it is determined that the clock number of the CRI signal is not within the range of 3 to 6, it is determined that the clock number of the CRI signal is 7 (step 207).

After it is judged that the number of clocks of the CRI signal is 7, the execution of the decoding process is instructed (step 2
21), it is determined whether or not the reception processing of the next field is performed (step 222). When the reception process is continued, monitoring of the CRI gate end pulse is started again (step 201). On the other hand, when the reception process is stopped, the reception operation for the closed caption signal ends.

Next, when the clock number of the CRI signal is 2 or less (step 204), it is determined whether the CRI start signal is 0 or 1 (step 208).
When the clock number of the CRI signal is 0, for example, as shown in FIG.
As shown in (a), the CRI signal cannot be detected due to the small amplitude of the CRI signal in the video signal such as a weak electric field, or the slice value for the CRI signal is sliced because the initial value of the slice level is set high. Since it is possible that the processing cannot be performed, the U / D counter 6 is instructed to greatly reduce the initial value of the slice level (step 209), and the above-mentioned cause can be removed in the next field.

When the clock number of the CRI signal is 1,
For example, as shown in FIG. 7B, the start of the CRI signal is detected due to the distortion of the waveform of the CRI signal, the initial value of the slice level being set low, etc.
It is possible that the falling edge of the I signal is not detected and the clock number of the CRI signal indicates 1. Thus, when the clock number of the CRI signal is 1, an instruction to greatly increase the initial value of the slice level is issued to the U / D counter 6 (step 210), and the above-mentioned cause can be removed in the next field.

Next, since the clock number of the CRI signal is small, an instruction to stop the decoding process is issued (step 211), and an instruction to erase the character information from the screen of the television receiver is issued (step 212).

After the deletion instruction of the character information is issued, it is determined whether or not the receiving process of the next field is performed (step 222). When the receiving process of the next field is performed, the initial value of the slice level is raised or lowered to be optimally set, so that the slice process for the CRI signal is reliably performed and the CRI signal of a predetermined clock number is detected. be able to. Therefore, accurate decoding processing can be executed, and predetermined character information can be displayed on the screen of the television receiver.

Another cause of the small number of detection clocks, such as the number of CRI signal clocks being 2 or less, is to prevent dubbing of a signal on a horizontal line where the number of CRI signal clocks is detected from commercially available video software. When it is considered that the signal is a copy guard signal for use in, or a scramble signal used for providing a pay program, it is impossible to perform decoding processing, and therefore an instruction to stop decoding processing is issued (step 211). An instruction is issued to erase the character information from the screen of the television receiver (step 212).

Next, when the number of clocks of the CRI signal is 8 or more (step 205), the reason why the number of clocks exceeds the predetermined value is that the initial value of the slice level is low as described above, and Since it is conceivable that overshoot, noise, etc. of the horizontal synchronizing signal are detected as the CRI signal, an instruction to increase the initial value of the slice level is issued to the U / D counter 6 (step 213).

Next, since the number of clocks of the CRI signal is larger than the predetermined value, an instruction to stop the decoding process is issued (step 211), and an instruction to erase the character information from the screen of the television receiver is issued (step 212). ).

After the deletion instruction of the character information is issued, it is determined whether or not the receiving process of the next field is performed (step 222). When the receiving process of the next field is performed, the initial value of the slice level is raised,
Slice processing is reliably performed on the CRI signal, and the CRI signal having a predetermined number of clocks can be detected.
Therefore, accurate decoding processing can be executed, and predetermined character information can be displayed on the screen of the television receiver.

Next, the clock number of the CRI signal is 3 to 6
When it is within the range (step 206), the duty ratio signal is read from the duty ratio detection circuit 26 (step 214), and it is determined whether or not the duty ratio indicated by the duty ratio signal is larger than a predetermined value (step 206). Step 215). When the duty ratio indicated by the duty ratio signal is larger than a predetermined value, an instruction to increase the slice level initial value is issued to the U / D counter 6 (step 21).
6).

Then, it is judged whether or not the decoding process is possible by the CRI signal having the clock number within the range of 3 to 6 (step 219). When it is determined that the decoding process is possible, the execution of the process indicating with an indicator that the reception state is poor is instructed (step 220), and the execution of the decoding process is instructed (step 221).

When it is determined that the decoding process is impossible, an instruction to stop the decoding process is issued (step 211) and an instruction to erase the character information from the screen of the television receiver is given (step 212). ).

On the other hand, when the duty ratio indicated by the duty ratio signal is not larger than the predetermined value, it is judged whether or not the duty ratio indicated by the duty ratio signal is smaller than the predetermined value (step 217). When the duty ratio indicated by the duty ratio signal is smaller than the predetermined value,
An instruction to reduce the initial value of the slice level is issued to the U / D counter 6 (step 218), and it is determined whether the decoding process is possible (step 219).

Next, when the duty ratio indicated by the duty ratio signal is not smaller than the predetermined value, it is determined whether the decoding process is possible (step 219).

The above-mentioned processes are repeated until the reception operation of the closed caption signal is stopped.

Therefore, the processing for changing the initial value of the slice level, the processing for determining whether to perform the decoding processing, and the processing for determining whether to display the character information on the screen of the television receiver are performed by the number of clocks of the CRI signal. Therefore, it is possible to prevent different character information or the like from being erroneously displayed on the screen of the television receiver for an abnormal caption signal, a received signal different from the caption signal, or the like.

[0104]

As described above, according to the closed caption receiving apparatus of the first invention of the present application, it is possible to improve the detection accuracy of the CRI signal by accurately setting the CRI signal input period, and to improve the accuracy of the CRI signal detection. It is possible to prevent malfunction due to low detection accuracy.

According to the closed caption receiver of the second invention of the present application, it is possible to improve the detection accuracy of the CRI signal by setting the initial value of the slice level for the CRI signal optimally, and the detection accuracy of the CRI signal is low. It is possible to prevent malfunction caused by

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a closed caption receiving device of the first invention of the present application.

2 is a CRI signal waveform and slice level, a CRI gate start pulse and a CRI gate end pulse, a slice signal, an output value of a CRI number counter 12 and a U / D counter 6 used for explaining the operation of the closed caption receiver of FIG. 3 is a time chart showing the output waveform of

FIG. 3 is a flowchart for explaining a processing operation of a microcomputer of the closed caption receiving device of FIG.

FIG. 4 is a CRI used for explaining a processing operation of a microcomputer of the closed caption receiving apparatus of FIG.
It is a figure which shows the relationship between the clock number of a signal and a CRI signal waveform.

FIG. 5 is a block diagram showing an embodiment of the closed caption receiving device of the second invention of the present application.

6 is a flowchart for explaining the processing operation of the microcomputer of the closed caption receiving apparatus of FIG.

FIG. 7 is a CRI used for explaining a processing operation of a microcomputer of the closed caption receiving device of FIG.
It is a figure which shows the relationship between the clock number of a signal and a CRI signal waveform.

FIG. 8 is a waveform diagram showing a closed caption signal.

FIG. 9 is a block diagram showing a conventional closed caption receiving device.

10 is a time chart showing a CRI signal waveform, a CRI gate pulse, and a slice signal used for explaining the operation of the closed caption receiving device of FIG.

[Explanation of symbols]

2 ... Comparator (slicer means), 3 ... CRI gate circuit (capturing means), 6 ... U / D counter, 8 ... D / A converter, 11 ... Fall detection circuit, 12 ... CRI number counter (counting means) , 13, 25 ... Microcomputer (processing means), 14, 22 ... AND circuit, 21 ... CRI start detection circuit, 23 ... FF (Philipflop), 26 ...
Duty ratio detection circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 59-21184 (JP, A) JP 61-43886 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 7/14-7/173 H04N 7/08 H04N 5/445

Claims (5)

(57) [Claims] 1. A closed caption signal including a repetitive signal indicating the phase and amplitude of a binarized signal, a logic signal following the repetitive signal, and the binarized signal following the logic signal during a vertical blanking period. A closed caption receiving device for extracting the closed caption signal from a television signal superimposed on the television signal and performing a decoding process on the closed caption signal, the television by comparing the voltage of the television signal with a reference voltage. Slicer means for performing slice processing on the John signal to generate a slice signal, capturing means for capturing the slice signal generated by the slicer means, and the number of clocks of the repetitive signal from the slice signal captured by the capturing means Counting means for counting the A logic level detector means for detecting a logic level period of the logic signal from Mareta slice signal, with the clock speed of the repetitive signal is counted by the counting means the repetitive signal repeating small predetermined set number or more than the number of Yes, and when the logic level period detected by the logic level detection means is equal to or longer than the set period, it is determined that the capture of the slice signal corresponding to the repetitive signal to the capture means is completed, and based on this determination A closed caption receiving apparatus, comprising: control means for instructing the acquisition means to stop the acquisition operation for the slice signal. 2. The processing means for controlling the display processing on the screen of the television receiver according to the number of clocks of the repetitive signal counted by the counting means. The closed caption receiver described. 3. The initial value of the reference voltage of the slicer means is changed according to the number of clocks of the repetitive signal counted by the counting means, and the display processing on the television receiver screen is controlled. The closed caption receiving device according to claim 1, further comprising: 4. A closed caption signal including a repetitive signal indicating a phase and an amplitude of the binarized signal, a logic signal following the repetitive signal, and the binarized signal following the logic signal during a vertical blanking period. A closed caption receiving device for extracting the closed caption signal from the television signal superimposed on the television signal and performing a decoding process on the closed caption signal, the television by comparing the voltage of the television signal with a reference voltage. Slicer means for performing slice processing on the John signal to generate a slice signal, capturing means for capturing the slice signal generated by the slicer means, and the number of clocks of the repetitive signal from the slice signal captured by the capturing means Counting means for counting the A level change detection means for detecting the presence or absence of level change of Mareta slice signal, the detection result of the comparison and the level change detecting means with the number of repetitions of the number of clocks between the repetitive signal of the repetitive signal counted by said counting means And a processing unit that changes an initial value of the reference voltage of the slicer unit according to the above. 5. The processing means further controls the display processing on the screen of the television receiver according to the number of clocks of the repetitive signal counted by the counting means and the detection result of the level change detecting means. 5. The method according to claim 4, wherein
The closed caption receiving device according to 1.