JP3789713B2 - Data demodulation circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data demodulation circuit that demodulates a data signal included in a video signal.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there is a system that transmits a video signal on which digital data is superimposed at a broadcasting station and transmits various information by demodulating the digital data at a receiving side. For example, there are services called VPS (Video Program System), PDC (Program Delivery Control), and the like. In this service, a broadcast time of a program is sent to a video signal. For this reason, a VTR (Video Tape Recorder) can control recording of a program based on the transmitted data. That is, when a program recording reservation is made, recording can be performed when the program is broadcast, and the reserved program can be recorded even when the broadcast time is changed.
[0003]
In such a VPS or PDC service, digital data is superimposed on a video signal in a period in which there is no video signal to be displayed immediately after the vertical blanking period. For example, a predetermined start code consisting of H and L is arranged after a clock signal (eight clock RUN) that repeats a high level (H) and a low level (L) at a predetermined frequency in a specific horizontal period. Then, the data represented by H and L are arranged. Therefore, on the receiving side, the presence of data is recognized by the clock RUN, and a threshold value that is intermediate between them is set based on the H and L levels of the clock RUN, and the subsequent data is compared with the threshold value. Then, it is determined whether it is H or L, and the data is demodulated.
[0004]
[Problems to be solved by the invention]
However, a video signal is transmitted from a normal broadcasting station by radio waves, received by an antenna, and then supplied to a VTR or the like. Therefore, the received wave often deteriorates due to the influence of the radio wave propagation situation. If the received wave is deteriorated, only a clean image cannot be obtained, but the digital data may become erroneous data.
[0005]
In the conventional apparatus, there is a case where correct data cannot be demodulated, and it is desired to perform highly accurate data demodulation.
[0006]
The present invention has been made in view of the above problems, and an object thereof is to provide a data demodulation circuit capable of accurately demodulating a data signal superimposed on a video signal.
[0007]
[Means for Solving the Problems]
The present invention relates to a data demodulating circuit for demodulating a data signal included in a video signal, a high level peak detecting means for detecting a high level peak of the video signal, and a low level for detecting a low level beak of the video signal. Peak detecting means, threshold determining means for determining a threshold for data detection from high level and low level peaks, and data demodulating means for demodulating a data signal in a video signal based on the determined threshold Determination means for determining whether or not a predetermined data signal has been correctly demodulated, follow-up control means for controlling follow-up to the detection peak in the high-level peak detection means and the low-level peak detection means, And the follow-up control means has at least one of the high level peak detection means and the low level peak detection means according to the determination result of the determination means. That controls the follow-up.
[0008]
Thus, according to the present invention, the followability control means controls the followability in the high level peak and low level peak detection means according to the determination result of the determination means. Appropriate threshold values are considered to change depending on the radio wave propagation status and data status, and by changing the followability of the high-level peak and low-level peak that determine the threshold value, appropriate threshold settings can be made. And accurate data demodulation.
[0009]
The followability control means has a plurality of control modes that are set by switching the followability of the high level peak detection means and the low level peak detection means in a plurality of stages according to the determination result of the determination means. When an error of a predetermined value or more is detected in the determination result of the determination means, the control mode is sequentially changed to determine an appropriate control mode. An appropriate control mode can be determined by such a method. In particular, since data is basically changed for each program, correct data can be obtained by changing the control mode after an error has occurred to some extent.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.
[0011]
FIG. 1 is a block diagram showing the overall configuration of the data demodulation circuit of this embodiment. The received composite video signal is supplied to the H peak detection circuit 10 and the L peak detection circuit 12. The H peak detection circuit 10 and the L peak detection circuit 12 are integration circuits composed of, for example, a capacitor C and a resistor R, and hold the H peak and the L peak with a time constant corresponding to the value of CR, respectively. Therefore, the H peak detection circuit 10 and the L peak detection circuit 12 output signals regarding the values of the H peak and the L peak in the input video signal.
[0012]
The time constants of the H peak detection circuit 10 and the L peak detection circuit 12 can be changed. For this, a capacitor or a resistor whose value can be changed may be adopted, or a plurality of these may be provided and switched to change the value.
[0013]
Outputs of the H peak detection circuit 10 and the L peak detection circuit 12 are supplied to a threshold value determination circuit 14. The threshold value determination circuit 14 detects an intermediate value (for example, an average value of both) from the supplied H peak and L peak, and uses this as a threshold value as one input terminal of the comparison circuit 16. To supply.
[0014]
The composite video signal is supplied to the other input terminal of the comparison circuit 16. Therefore, the comparison circuit 16 determines whether the composite video signal is equal to or greater than a threshold value, and outputs the result. The digital data superimposed on the composite video signal is binary data of H or L, and demodulated data is obtained at the output of the comparison circuit 16.
[0015]
Here, the demodulated data which is the output of the comparison circuit 16 is supplied to the discrimination circuit 18. The determination circuit 18 determines whether or not the demodulated data is correct based on whether or not predetermined data included in the video signal exists. If it is determined that an error has occurred, the result (error signal) is supplied to the error counter 20. The error counter 20 outputs a count-up signal when, for example, 30 is counted, and is reset at a predetermined period (for example, every 100 vertical periods).
[0016]
When the error counter 20 counts up, a count-up signal is supplied to the control circuit 22. When receiving the count-up signal, the control circuit 22 changes the control signal supplied to the H peak detection circuit 10 and the L peak detection circuit 12. As a result, the time constant in the H peak detection circuit 10 and / or the L peak detection circuit 12 is changed.
[0017]
Next, the operation of this circuit will be described. The composite video signal includes a vertical synchronization signal for each video signal for display for one screen, and a horizontal synchronization signal for each horizontal scan of the screen. Since the video signal of a predetermined number of horizontal lines after the vertical synchronization signal is not actually displayed on the screen, digital data is superimposed on the video signal during this period. For example, in the case of VPS, the data signal is superimposed on the 16th horizontal line, and in the case of PDC, the data signal is superimposed on any of the 6th to 22nd horizontal lines and the 318th to 335th horizontal lines.
[0018]
In the horizontal line on which the data signal is superimposed, a color burst signal is present after the horizontal synchronizing signal, and then a clock RUN, a start code, and data that repeat H and L are present.
[0019]
In the case of VPS, as shown in FIG. 2, there is a clock RUN of 200 nsec × 16 after 12.5 μsec ± 1.5 μsec from the falling edge of the horizontal synchronizing signal, and then 15 bytes × 16 starting from the start code. There are data signals. The data frequency is 5 MHz.
[0020]
On the other hand, in the case of the PDC, as shown in FIG. 3, there is a clock RUN of 144 nsec × 16 after 12.0 μsec + 0.4 μsec or −1.0 μsec from the fall of the horizontal synchronizing signal, and then starts from the start code. There is a data signal of 45 bytes × 8. The data frequency is, for example, 6.9375 MHz.
[0021]
In the H peak detection circuit 10 to which such a composite video signal is input, first, the H peak is detected by the clock RUN. That is, the H level of this clock RUN is detected and held. On the other hand, the L peak detection circuit 12 detects and holds the L peak value of the clock RUN.
[0022]
Since the intermediate value between the H and L peak values is supplied from the threshold value determination circuit 14 to the comparison circuit 16, the comparison circuit 16 determines the intermediate value between the H level and the L level at the end of the clock RUN. The composite video signals are compared, and the subsequent data is demodulated and output.
[0023]
Here, the data following the clock RUN is a start code. The start code is predetermined data, and the determination circuit 18 checks the content of the start code. Then, it is determined whether the start code is correct. Note that which data signal of VPS or PDC is targeted may be set in advance by a switch or the like, or may be automatically determined from the clock frequency of received data. The determination is preferably performed only when a predetermined clock RUN is detected.
[0024]
Then, the discrimination circuit 18 outputs an error signal when the start code is not correct. This error signal is supplied to the error counter 20 where it is counted. Since one data signal is basically inserted in one vertical period, if there is an error every time, the data signal is counted up every one vertical period.
[0025]
The error counter 20 counts up every time an error signal is supplied, and outputs a count-up signal when it counts up to 30 within a predetermined period (for example, 100 vertical periods).
[0026]
This count-up signal is supplied to the control circuit 22. In this example, the control circuit 22 outputs four control signals CTRA, CTRB, CTRC, CTRD. CTRA and CTRB are supplied to the H peak detection circuit 10, and CTRC and CTRD are supplied to the L peak detection circuit 12.
[0027]
The control signals CTRA and CTRC are signals for determining on / off of the follow-up, and H means follow-up operation on, and L means follow-up operation off. On the other hand, CTRB and CTRD are signals for determining whether the follow-up property is to be accelerated or delayed, and means that the follow-up property is fastened by H and the follow-up property is slowed by L.
[0028]
The control circuit 22 in the present embodiment has a mode for outputting the seven types of signals shown in FIG. 4, and sequentially changes the mode each time a count-up signal is supplied.
[0029]
First, the period of the clock RUN is a period for detecting H and L peaks. Therefore, in this embodiment, all the follow-ups are made fast during this period.
[0030]
In the first mode, all control signals continue to be H, always follow the input signal quickly to detect the H peak and L peak, and determine the threshold based on these. In the second mode, after the clock RUN, the H and L peak values obtained by the clock RUN are held. In the third mode, after the clock RUN, the followability to both the H and L peaks is delayed. In the fourth mode, after the clock RUN, the followability of only the H peak is delayed. In the fifth mode, after the clock RUN, the followability of only the L peak is delayed. In the sixth mode, after the clock RUN, the tracking operation of only the H peak is performed, and the value is held for the L peak. In the seventh mode, after the clock RUN, the tracking operation of only the L peak is performed, and the value is held for the H peak.
[0031]
5 and 6 show examples of threshold value tracking operations in these seven modes. Thus, the threshold change state changes with respect to the same input signal. For this reason, it is highly possible that any one of these threshold values is a correct threshold value depending on the state of the received radio wave.
[0032]
Therefore, in the control circuit 22 of the present embodiment, these seven types of modes are prepared in advance, and when one mode is set, when the count-up signal is obtained from the error counter 20, the following Switch to mode. Thus, the mode is automatically switched when there are many errors, and an appropriate mode is selected.
[0033]
Note that the modes may always be changed in a preset order, but it is also preferable to change the order according to the frequency of selection or the most recently selected mode.
[0034]
In this manner, the H peak value and the L peak value when the followability is changed are changed by the first to seventh modes, and thus the threshold value is changed. Therefore, according to the present embodiment, the most appropriate threshold value can be selected.
[0035]
FIGS. 7 and 8 show changes in composite video signals and threshold setting states in PDC and VPS. FIGS. 7A and 8A show a normal case, and FIGS. 7B, 7C and 8B, and FIG. This shows a case where there is a possibility that data demodulation is not successful. Thus, in the data signal, when one of H and L data continues, the H peak or the L peak is likely to fluctuate. Even in such a case, the threshold value may not be appropriate depending on the radio wave condition. In this example, it is presumed that data demodulation can be stabilized, for example, in a mode in which the follow-up is made faster only at the L level.
[0036]
From these drawings, it is understood that a plurality of modes as in the present embodiment can be set, and a more appropriate threshold value can be set by sequentially switching the modes.
[0037]
In the case of VPS and PDC, the data content is data on program identification and time. Therefore, the data content changes for each program. Therefore, there is no problem by setting the threshold value to an appropriate value after a certain vertical period has elapsed.
[0038]
【The invention's effect】
As described above, according to the present invention, the followability control means controls the followability in the high level peak and low level peak detection means according to the determination result of the determination means. Appropriate threshold values are considered to change depending on the radio wave propagation status and data status, and by changing the followability of the high-level peak and low-level peak that determine the threshold value, appropriate threshold settings can be made. And accurate data demodulation.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a circuit according to an embodiment.
FIG. 2 is a diagram showing a state of digital data in VPS.
FIG. 3 is a diagram showing a state of digital data in a PDC.
FIG. 4 is a diagram illustrating a state of a control signal in each mode.
FIG. 5 is a diagram showing an H peak and an L peak in each mode.
FIG. 6 is a diagram showing an H peak and an L peak in each mode.
FIG. 7 is a diagram illustrating a waveform state in a PDC.
FIG. 8 is a diagram showing a state of a waveform in VPS.
[Explanation of symbols]
10 H peak detection circuit, 12 L peak detection circuit, 14 threshold value determination circuit, 16 comparison circuit, 18 discrimination circuit, 20 error counter, 22 control circuit.

Claims (1)

A data demodulation circuit for demodulating a data signal included in a video signal,
A high level peak detecting means for detecting a high level peak of a video signal;
A low level peak detecting means for detecting a low level peak of a video signal;
A threshold value determining means for determining a threshold value for data detection from the high level and low level peaks;
Data demodulating means for demodulating the data signal in the video signal based on the determined threshold;
Determining means for determining whether or not a predetermined data signal is correctly demodulated;
Followability control means for controlling the followability to the detection peak in the high level peak detection means and the low level peak detection means;
Have
The followability control means has a plurality of control modes that are set by switching the followability of the high level peak detection means and the low level peak detection means in a plurality of stages according to the determination result of the determination means. A data demodulating circuit characterized by sequentially changing the control mode and determining an appropriate control mode when an error of a predetermined value or more is detected in the determination result of the determination means .

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