JPH06152937A - Printer - Google Patents

Abstract

PURPOSE:To improve printing quality, to unnecessitate the storage of bit image data after reduction inside a memory and a reduction processing and to improve a processing speed by providing a mechanism for ORing a picture element under consideration to be reduced and the adjacent picture elements. CONSTITUTION:The output 24 of a register 1 for setting a reduction ratio from the data bus 12 of a CPU 12 is inputted to an adder 2 and the output 22 of the adder 2 is latched by a video clock signal 15 at the register 3. Also, the output 23 of the register 3 is the input of the adder 2 and cleared by a clear signal 27 from the CPU. The adder 2 adds a value set at the register 1 and the value of the register 3 latched by the video clock 15 to be a carry signal 25. Also, the clock 16 of a frequency twice as much as a basic video clock 13 is the rise of the clock inverted at an inverter 4 and the carry signal 25 is sampled by a flip-flop 5. The output 20 and 18 of AND circuits 7 and 8 is ORed at an OR circuit 9 and turned to the clock of a PS converter 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printing device.

[0002]

2. Description of the Related Art Conventionally, a printer that develops character information sent from a host computer or the like into a bit image in an internal memory, and then reads and outputs the bit image, if there is reduced printing, stores it in the memory. It is necessary to re-expand the reduced bit image and output it.

[0003]

However, in the above-mentioned conventional example, the memory for the original bit image and the reduced bit image to be reduced is required in the memory, and the processing time for the reduction is required.

Further, when the bit image is reduced, if the process of simply thinning out one pixel is performed, there is a drawback that the printing quality is deteriorated.

[0005]

According to the present invention, when outputting the expanded bit image data, the adjacent two pixels of the pixel of interest to be reduced are referred to, and the pixel of interest to be reduced is white. , If both adjacent pixels are black,
When white is prioritized and two adjacent pixels are not black, a mechanism for taking the logical sum of the target pixel to be reduced and the adjacent pixel is provided to improve the print quality and reduce it in the memory. Storage of later bit image data,
And reduction processing is unnecessary.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of an image data reducing unit of a printing apparatus according to an embodiment of the present invention. Reference numeral 1 is a register for setting a reduction rate from a data bus 12 of a CPU (central processing unit, not shown), and an output 24 of the register 1 is input to the adder 2. Register 3 is adder 2
Output result 22 is latched by the video clock signal 15. The output 23 of the register 3 becomes the input of the adder 2, and the output 23 is the clear signal 27 according to the instruction from the CPU.
The value is cleared to 0 by. The adder 2 adds the value set in the register 1 and the value in the register 3 latched by the video clock 15 to form a carry signal 25.

Reference numeral 16 is a clock having a frequency twice that of the basic video clock 13, and the carry signal 25 is sampled by the flip-flop 5 at the rising edge of the clock inverted by the inverter 4. The Q output 17 of the flip-flop is ANDed with the double basic video clock 16 in the AND circuit 8, and the / Q output 14 is the basic video clock 1
3 and AND circuit 7 take the logical product. AND circuit 7
Output 20 of the AND circuit 8 and the output 18 of the AND circuit 8 are logically ORed by the OR circuit 9, and the output 15 is a video clock and the latch clock of the register 3 and the clock of the parallel-serial converter (PS converter) 10. Become. The output 17 of the flip-flop 5 is sampled by the flip-flop 6 at the rising edge of the clock obtained by inverting the basic video clock 13 by the inverter 37. FIG. 2 is a detailed block diagram of the P / S converter 10. In the figure, S1 and S2 are selectors, and the load signal 36 selects the image data bus 21. The flip-flops F1 and F2 latch the output of the selector with the video clock 15. The selectors S1 and F1 form a 1-bit latch and shift register, and the number of bits of the bit image bus 21, the selector, and the flip-flop exist. Bit image bus 21 with load signal 36
When is not selected, the output of the flip-flop of the previous stage becomes the input of the flip-flop of the next stage and is latched by the video clock 15, that is, the shift register. Output serial signal 2 of flip-flop F1
Reference numeral 9 serves as an input of the flip-flop FF1, and also serves as an input of the OR circuit 103 and the inverter 102. Selector S1
Output 101 is input to the NAND circuit 104. The output of the flip-flop FF1 is the OR circuit 103 and NAND.
It becomes an input of the circuit 104, and outputs of the OR circuit 103 and the NAND circuit 104 become an input of the AND circuit 105. AN
The output 31 of the D circuit 105 becomes the reduced video signal 31.
The input 28 of the 2-selector 33, the serial signal 29 and the reduced video signal 31 are selected as the output 28 of the flip-flop 6, and the output 34 of the selector 33 is latched by the flip-flop 35 at the rising edge of the basic video clock 13 and the video signal 19 Is output to the printing unit.

Next, the operation will be described with reference to FIGS. 1, 2, 3 and 4.
This will be described with reference to FIG.

FIG. 3 is a timing chart for explaining this embodiment, and FIG. 4 is a diagram showing bit image data.

The CPU first clears the contents of the register 3 to 0, and therefore outputs a clear signal 27 to clear the register 3 to "0". Next, the CPU sets the reduction rate in the register 1 through the data bus 12. The format of the data set here is fixed point, and is shown in FIG. Here, assuming that the reduction ratio is 1.25, FIG. 5B is set. In the adder 2, the value of the register 1.3 is added, and here, 0.75 + 0 = 0.75 (step S0). In the initial state, the flip-flops 5 and 6 are in the reset state, the output 17 of the flip-flop 5 is "L", the AND circuit 8 is closed, the output 17 is "H", and the output 28 of the flip-flop 6 is " L ″, and the selector 29 selects the output 29 of the P / S converter 10 (step S0). When printing becomes possible, basic video clock 13 and double basic video clock 16
Is output and the output 14 of the flip-flop 5 is "H", the output 20 of the AND circuit 7 is "H" and O
The output of the output video clock 15 of the R circuit 9 becomes "H", and the load signal 36 is output at this time, and the selectors S1 and S2 in FIG. 2 select the bit image bus 21 and select P / S.
The converter 10 receives the data to be transferred from the data bus 21 from the image memory (step S1). At this time, the value of the output 22 of the adder 2 is latched in the register 3, and the adder 2 outputs 0.75 + 0.75 = 1 +
When it becomes 0.5, the carry signal 25 becomes "L" and is output. The double basic video clock 16 is inverted by the inverter 4, and the flip-flop 5 samples "L" of the carry signal 25 (step S).
2). At this time, since the carry signal 25 is "L", the state of the flip-flop 5 does not change. The basic video clock 13 is inverted by the inverter 37 to sample the output 17 of the flip-flop 5, but since the output 17 of the flip-flop 5 is "L", the state of the flip-flop 6 does not change and the output 28 is "L". “It remains. In step S4, since the output 28 of the flip-flop 6 is "L", the serial signal 29 is selected by the selector 33, the serial signal 29 is latched by the flip-flop 35, and the video signal 19 and Will be output. The output value of the adder 2 is sequentially latched in the register 3, and the carry signal 25 is sampled in the flip-flop 5. In step 5, the addition result becomes 0 + 0.75 = 0.75, and the carry signal 25 becomes the level “H”. At the rising edge of the double basic video clock 16 in the flip-flop 5,
The level "H" of the carry signal 25 is sampled, and the output of the flip-flop 5 is output to the level "H".
4 becomes the level "L" (step S6). Also at the same time A
When the ND circuit 7 is closed, its output 20 becomes the level "L". In step S7, the level "H" of the double basic video clock 16 is applied, the output 18 of the AND circuit 8 becomes "H", and the output 15 of the OR circuit 9 also becomes "H". At this time, at the falling edge of the basic video clock 13, the level "H" of the output 17 of the flip-flop 5 is sampled by the flip-flop 6, and its output 28 becomes "H". 31 will be selected. At this time, since the output of the selector S1 is the output of the flip-flop F2, the data level of the bit 5 in FIG. 4 is "H", and the output of the flip-flop F1 is the data level of the bit 4 "L". The output of FF1 is the data level "H" of bit 3. Since the input signals of the NAND circuit 104 are all at the level "H", its output is at the level "L", and the output reduced video signal of the AND circuit 105 is at the level "L" (FIG. 4 (b) bit). Position 3
a). In step S8, double the basic video clock 16
At the falling edge of, the level "L" of the carry signal 25 is sampled in the flip-flop 5, and its output 1
7 becomes the level "L", the output 14 becomes the level "H", and the output 18 of the AND circuit 8 becomes the level "L". Next, in step S9, the reduced video signal 31 selected by the selector 33 is generated at the rise of the basic video clock 13.
Is latched by the flip-flop 35 and the video signal 19
Is output as. At step S10, at the falling edge of the basic video clock 13, the level "L" of the output 17 of the flip-flop 5 is sampled by the flip-flop 6, its output 28 becomes the level "L", and the selector 33 causes the P / S converter. 10 output serial signals 29 are selected. Similar operations are performed thereafter, but step S1
1, the flip-flop FF1 has the same structure as that shown in FIG.
The level "L" of the bit 11 in (a) and the level "H" of the bit 12 are latched in the flip-flop F1, and the output of the NAND circuit 104 is at the level "H".
Further, the output of the OR circuit 103 also becomes the level "H", and the AND
The output 31 of the circuit 105 becomes the level "H", and in step 12, the level "H" becomes the video signal 19 and is output.

In FIG. 4, (a) is the bit image data, (b) shows the reduced bit image data in this embodiment, and (c) shows the reduced bit image data in the logical sum processing only. Indicates.

Although it has been described that the data of the left and right pixels adjacent to the pixel of interest are referred to when the image is reduced, it goes without saying that the data of the upper and lower adjacent pixels may also be referred to.

Further, at the time of reduction, means for obtaining a logical sum of pixels adjacent to the target pixel and means for referring to data of both pixels adjacent to the target pixel can be selected by a panel or by an instruction from a host computer. It is also possible to do so.

[0014]

As described above, since the bit image data expanded in the bit map memory is transmitted as a video signal while being reduced, it is not necessary to store the reduced bit image in the memory and the reduction processing is performed. Is unnecessary, which leads to an improvement in processing speed.

At the time of reduction, the pixel of interest is set to "1" or "0" according to the bit state of the pixels around the pixel of interest, instead of simply thinning out one pixel. It has the effect of preventing omission and increasing the printing quality.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a detailed diagram of a P / S converter in a block diagram of an embodiment of the present invention.

[Fig. 3] Timing chart during video transfer

FIG. 4 is a diagram showing bit image data transferred from a bit map memory, a video signal of only OR processing, and a video signal by processing of this embodiment.

FIG. 5 is a diagram showing values when a reduction rate is set.

[Explanation of symbols]

 1 Reduction ratio setting register 2 Adder 3 Addition result storage register 5, 6, 35 Flip-flop 7, 8 AND circuit 9 OR circuit 10 P / S converter 13 Basic video clock 16 Double basic video clock 33 Selector 19 Video signal 25 Carry Signals F1 and FF1 Flip-flop 104 NAND circuit 103 OR circuit 105 AND circuit

Claims (2)

[Claims] 1. A reduction rate setting means for setting a reduction rate, an addition means for sequentially adding reduction rates, an addition result storage means for storing an addition result, and a carry signal from the addition means by a video clock. Sampling means for sampling, a frequency judging means for judging whether the video clock of the pixel data of the next stage from the pixel of the previous stage is normal or one clock is inserted from the result of the sampling means, and the pixel data of the next stage Next-stage pixel data determination means for determining the next-stage pixel data according to the state of the pixel data before and after, and the next-stage pixel data is left unchanged or the next-stage pixel data is determined from the result of the sampling means. And a next-stage pixel selecting means for selecting the means. 2. When two pixels adjacent to a pixel of interest to be reduced are referred to, and when the pixel of interest to be reduced is white and both adjacent pixels are black, white is prioritized and two adjacent pixels are together. If it is not black, an image reduction method characterized by taking the logical sum of the pixel of interest to be reduced and an adjacent pixel.