JPH06152673A - Demodulator - Google Patents

Abstract

PURPOSE:To simplify the circuit configuration of a delay detector by checking a delay through signal processing of only a phase component of a base band reception input signal. CONSTITUTION:An angle converter 1 extracts only a phase component from base band reception input signals RI, RQ resulting from applying orthogonal detection to a digital phase modulation signal and the component is phase- converted. The phase theta subject to phase conversion is fed to a delay detector 2 and a phase delay signal delayed by a delay circuit 2a and an input phase signal are subject to subtraction processing at a subtractor 2b and a phase difference DELTAtheta is outputted. The delay detection output 66 and an offset phase signal are fed to an adder 3, in which they are added and an output of the adder 3 is fed to a clock recovery device 4, from which a recovered clock signal is generated. That is, when an offset phase angle is zero, since a code change point of the phase difference DELTAtheta is caused at crossing of the I axis, the phase of the code change point is detected by an edge detector 4b and phase-locked at a PLL circuit 4c to generate the recovered clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator for a digital phase modulation signal in digital communication, and more particularly to a demodulator suitable for simplifying the circuit configuration of a differential detection circuit and performing efficient demodulation.

[0002]

2. Description of the Related Art Conventionally, many demodulators for demodulating a digital phase modulation signal in digital communication have been provided in the block diagram shown in FIG. In the figure, 10 is a differential detector, the differential detector 10 is orthogonally detected baseband received input signal R _I, differential detection output signal by differential detection the R _Q D _I, demodulates outputs D _Q. Reference numeral 4 denotes a clock regenerator, which is composed of a comparator 4a, an edge detector 4b, and a PLL circuit 4c.

The demodulator constructed in this way demodulates the baseband received input signals R _I and R _Q by delay detection processing by the delay detector 10 and demodulates the input signals R _I and R _Q. And the complex detection of the differential detection output signals D _I and D _Q will be described below.

When the baseband received input signals R _I and R _Q are represented by the real and imaginary parts of the complex number, the complex number of the baseband received input signals R _I and R _Q | R = R _I + jR _Q , (Equation 1) Become. However, a complex number is represented by "| R" and is represented by the same symbol below. Similarly, the differential detection output signals D _I and D _Q are expressed by the real part and the imaginary part of the complex number in the same manner as described above. If the differential detection output signals D _I and D _Q are complex numbers | D = D _I + jD _Q , (Equation 2 ).

Here, the complex number | D _k of the differential detection output signal at a certain arbitrary time k is subjected to signal processing by a multiplier (not shown) incorporated in the differential detector 10, and is represented by the following equation. Differential detection output signal complex number | D _k = | R _k * | R _k-1 ^* , (Equation 3) where “| R _k ” is a complex number of the baseband received input signals R _I and R _{Q at} the same time k. Yes, “| R _k−1 ^* ” is a conjugate complex number of the baseband received input signals R _I and R _Q at time (k−1) one symbol before.

If the complex number | R _k of the differential detection output signals D _I and D _Q at the time k represented in this way is replaced by the polar coordinate form, the complex number | R _k of the baseband received input signals R _I and R _Q is represented. = R (cos θ
+ j · sin θ) and (Equation 4). Here, r is the absolute value of the complex number | R, that is, the amplitude, and θ is the angle of the complex number | R, that is, the phase. The complex number | D of the differential detection output signals D _I and D _Q with respect to the complex number | R of the input signal in the polar coordinate format is given by the above equation 3 as the complex number of the differential detection output signals D _I and D _Q | D _k = | R _k * | R _k-1 ^* = r _k · r _k-1 {cos (θ _k -θ _k-1 ) ＋ j · sin (θ _k -θ _k-1 )}, (Equation 5), and the phase component θ _k becomes On the other hand, the phase difference (θ _k -θ _k-1 ) from the phase component θ _k-1 one symbol before is calculated.

As described above, the differential detection output signal-processed by the differential detector 10 is, for example, a π / 4 phase-shifted four-phase PS.
K, namely π / 4-QPSK (Quadrature Phase Shift Ke
Differential detection output signal when the modulated wave of ying) is differentially detected
When D _I and D _Q are represented by Cartesian coordinates, since they are π / 4 phase shifted, they can be represented by four points A, B, C and D in the coordinate diagram shown in FIG. In the coordinate diagram of FIG. 2, the horizontal axis is the I axis and the vertical axis is the Q axis.

In this way, the baseband received input signals R _I , R
_{The Q} is delayed detected by the delay detector 10 and demodulated and output. On the other hand, the reproduced clock signal synchronized with the demodulated output is detected by the clock regenerator 4 at the sign change point of the delayed detection output signal D _Q and phase-synchronized. The clock signal was being regenerated.

The above-mentioned differential detection output signal D _{Q of the differential} detector 10
Is supplied to the edge detector 4b via the comparator 4a,
A PLL circuit 4c for detecting a sign change point of the differential detection output signal _DQ , that is, a point crossing the I axis in FIG. 2 as a sign change point, and generating a reproduction clock signal from the detected phase signal detected by the edge detector 4b. , And the reproduced clock signal is output from the voltage controlled oscillator (not shown) in phase synchronization with the phase locked loop circuit (not shown) of the PLL circuit 4c.

[0010]

However, the above-mentioned conventional demodulator for digital phase modulation signals has a baseband by a multiplier (not shown) built in the delay detector 10 in the signal processing inside the delay detector 10. Complex number of received input signal R _I , R _Q | R
In this case, since the amplitude information unnecessary for digital phase modulation, that is, the signal processing of the real number part r expressed in the polar coordinate format of the complex number | R has to be processed in the delay detector 10, the multiplication processing is performed. There is a drawback that the circuit configuration becomes complicated.

When the QPSK signal is differentially detected by the differential detector 10, the differential detection output signals D _I and D _Q are points A ', B', C ', and D'in the coordinate diagram shown in FIG. Signal points are superimposed on both the I-axis and the Q-axis. That is, points A ', C'in the figure are on the I-axis,
B ', C' because the point is located on the Q axis, it is impossible to phase detection code change point of the differential detection output signal D _Q, the offset phase angle ψ to the delay detection output signal D _Q, e.g. As shown in the figure, it is necessary to add a phase angle ψ of 45 degrees to perform a phase shift, and after adding the offset phase angle ψ in the delay detector 10, the complex number multiplication process is performed. There was a drawback that

The present invention has been made in view of the above points, and an object thereof is to solve the drawbacks of the conventional example and to perform signal processing only for the phase components of the baseband received input signals R _I and R _Q. An object of the present invention is to provide a demodulator in which the circuit configuration of the delay detector is simplified by performing the delay detection.

[0013]

The demodulator of the present invention is equipped with a delay detection means for demodulating a digital phase modulation signal, demodulates it, and synchronizes it with the phase detected by the edge detection means of the sign change point of the demodulated output signal. A demodulator having clock reproduction means for oscillating the reproduced clock signal,
An angle conversion means for detecting the phase information of the digital phase modulation signal to convert the phase angle and a delay detection means for delaying the phase information after the angle conversion are provided to demodulate the digital phase modulation signal and perform the delay detection. The reproduced clock signal phase-synchronized with the phase of the sign change point of the demodulated signal is output.

Further, it is provided with an adding means for adding the offset phase angle of the demodulated signal subjected to the delay detection, and outputs the reproduced clock signal phase-locked with the phase of the code change point of the demodulated signal added with the offset phase angle. It may be configured as follows.

[0015]

According to the present invention, only the phase component θ of the phase information of the baseband received input signals R _I and R _{Q obtained} by quadrature detection of the digital phase modulation signal is detected and the phase angle θ = tan.
^-1 (R _Q / R _I ) is converted (angle conversion means). The phase information θ obtained by the angle conversion can be delay-detected and demodulated by a delay detector including a delay circuit and a subtractor (delay detection means).

The phase of the code change point of the delay-detected demodulated output signal is detected (edge detecting means), the detected phase is supplied to the PLL circuit, and the phase-locked voltage is phase-locked by the phase-locking unit incorporated in the PLL circuit. A reproduction clock signal is generated by the control oscillation signal (clock reproduction means).

That is, the baseband received input signals R _I , R
At the same time that _Q is digitally demodulated, a phase-locked recovered clock signal can be obtained.

Also, for example, Q without π / 4 phase shift
Only the phase component θ of the PSK is differentially detected by the delay detector through the angle converter, digitally demodulated, and an adder is provided to add an arbitrary offset phase angle ψ to the demodulated output signal (offset phase angle adding means). ), The phase of the code change point is detected in the same manner as above with respect to the demodulated signal to which the offset phase angle ψ is added by this adder (edge detection means), and the PLL
It is also possible to output the reproduced clock signal in phase synchronization with the circuit.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a demodulator according to the present invention will be described with reference to FIGS. The same parts as those of the conventional example are designated by the same reference numerals and the description thereof will be omitted. FIG. 1 is a block diagram. In FIG. 1, reference numeral 1 is an angle converter that performs angle conversion of a phase angle. The angle converter 1 extracts only the phase component θ of the baseband received input signals R _I and R _Q. Convert the phase. Reference numeral 2 denotes a delay detector, which is composed of a delay circuit 2a and a subtracter 2b for subtracting the delay signal delayed by the delay circuit 2a and the input signal.

Reference numeral 3 denotes an adder. The differential detection output signal and the offset phase signal are supplied to the adder 3 for addition, and the output of the adder 3 is supplied to the clock regenerator 4 for reproduction clock signal. Can occur.

In the digital demodulator configured as described above, the angle converter 1 extracts only the phase component of the baseband reception input signals R _I and R _{Q obtained} by quadrature detection of the digital phase modulation signal, and the phase is converted. This converted phase θ
Is θ = tan ⁻¹ (R _Q / R _I ).

In this way, the phase-converted phase θ is supplied to the delay detector 2, and the phase delay signal delayed by the delay circuit 2a and the input phase signal are subjected to subtraction processing by the subtractor 2b to obtain the phase difference Δθ. Output. That is, the, the phase difference Δθ is obtained by calculating the phase of the received baseband input signals R _I, R _Q, 1-symbol preceding received baseband input signals R _I, the difference between the R _Q phase.

Now, when the QPSK modulated wave that is π / 4 phase shifted is subjected to delay detection by the delay detector 2, the delay detector 2
The phase difference Δθ of the differential detection output of 1 represents the angle of the signal points A, B, C, D expressed in polar coordinates in the coordinate diagram shown in FIG.

That is, since the sign change point of the phase difference Δθ crosses the I axis when the offset phase angle is zero degrees, the phase of this sign change point is detected by the edge detector 4b and the same as in the conventional example. A reproduced clock signal can be generated in phase synchronization with the PLL circuit 4c.

When the QPSK modulated wave is received, the phase difference Δθ detected by the delay detector 2 by delay detection represents the angles of the signal points A ′, B ′, C ′, D ′ shown in FIG. , It is necessary to add the offset phase angle to detect the sign change point, and the phase difference Δθ is added to the signal point by the adder 3, for example, by adding the offset phase angle of 45 degrees as shown in FIG. A ', B', C ', D'points can rotate the phase and cross the I axis, and the edge detector 4b cannot detect the sign change point like the π / 4 phase shift QPSK signal. , PLL circuit 4c makes it possible to obtain a reproduced clock signal similar to the above.

By constructing the angle converter 1 using a ROM table or the like, there is no need to use a multiplier in the delay detector 2 as in the conventional example, and a simple circuit configuration is eliminated without a complicated circuit configuration. It becomes possible to do.

In the above, in FIG. 1, the circuit for adding the offset phase angle by the adder 3 has been described as only one system, but from the adder 3 for adding the offset phase angle to the edge detector 4b for detecting the sign change point. A multi-phase PSK (8-phase PSK or 16-phase PSK)
It is possible to recover the clock signal of the modulated wave.

[0028]

As described above, the digital demodulator according to the present invention extracts the phase components of the baseband received input signals R _I and R _Q by the angle converter 1, converts the phase components, and performs delay detection. There is an effect that the circuit configuration of the delay detector 2 can be easily configured without using a multiplier or the like.

Furthermore, since it is possible to eliminate the multiplication processing of the complex numbers of the baseband received input signals R _I and R _Q , the circuit configuration of the delay detector 2 can be more simply constructed.

Further, the adder 3 can be provided to add an arbitrary offset phase angle, and the adder 3 of a plurality of channels and the edge detector 4b can be configured to generate modulated waves of various modulation systems. There is also an effect that a corresponding reproduction clock signal can be generated.

Moreover, it has excellent features such as a simple structure and easy implementation because it can be constructed at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital demodulator according to the present invention.

FIG. 2 is a coordinate diagram showing a demodulated signal obtained by delay detection of a π / 4 phase shift QPSK modulated wave in a polar coordinate format.

FIG. 3 is a coordinate diagram showing a signal point representing a demodulated signal obtained by delay-detecting a QPSK modulated wave in a polar coordinate format and a 45 ° offset phase angle.

FIG. 4 is a block diagram of a conventional digital demodulator.

[Explanation of symbols]

 1 Angle converter 2 Delay detector 2a Delay circuit 2b Subtractor 3 Adder 4 Clock regenerator 4a Comparator 4b Edge detector 4c PLL circuit

Claims (2)

[Claims] 1. A delay detection means for delay-detecting and demodulating a digital phase modulation signal, and a clock reproduction means for oscillating a reproduction clock signal phase-locked with a phase detected by an edge detection means of a code change point of the demodulation output signal. A digital demodulator provided with an angle converting means for detecting phase information of the digital phase modulated signal to convert a phase angle, and a delay detecting means for delay detecting the phase information after the angle conversion. A demodulator characterized in that it demodulates a phase-modulated signal and outputs a regenerated clock signal that is phase-synchronized with the phase of the code change point of the demodulated signal detected by delay detection. 2. An addition means for adding the offset phase angle of the demodulated signal detected by the delay detection is provided, and a reproduced clock signal phase-locked with the phase of the code change point of the demodulated signal added with the offset phase angle is output. The demodulator according to claim 1, wherein: