JPH06152621A - Interface system for loop transmission network system - Google Patents

Abstract

PURPOSE:To allow a system to cope with a diversified transmission speed of a connection device without incurring cost increase of an interface circuit and deterioration in a transmission efficiency. CONSTITUTION:A dual port buffer memory 21 having a storage capacity by 2 frames is provided in a station arranged on a loop transmission line LP. Write/read of reception data are respectively implemented by applying a write address generated by a loop slot counter 41 and a read address generated by an I/F slot counter 42 or the like to the dual port memory 21 in time division. Then the write address and the read address are compared by an address coincidence detection section 52 and a loop address MSB control section 53 to shift the write address by one frame when both addresses are coincident.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for performing an interface operation between a loop transmission frame and an interface frame in a loop transmission network system adopting a circuit switching system used in offices and business establishments. Regarding

[0002]

2. Description of the Related Art In a loop type local area network system (loop LAN system), a plurality of stations are generally connected in a loop via a loop transmission line, and a fixed length transmission frame including a data slot is transmitted on the loop transmission line. It is a system in which data is transmitted between arbitrary stations by circulating it. This type of system is suitable for transmitting periodic data such as voice and moving images, and has been actively used in recent years.

FIG. 6 is a schematic configuration diagram of this type of system, in which a plurality of stations ST1 to ST4 are connected in a loop via a loop transmission line LP. Connected devices TM1 and TM2 such as an electronic private branch exchange (PBX) and a video codec are connected to the stations ST1 to ST4 via interface transmission lines IP1 and IP2. Loop transmission line L
A loop transmission frame is circulated on P, and each station ST1 to ST1.
In ST4, data is transmitted between the connection devices TM1 and TM2 by placing data on this transmission frame.

FIG. 7 shows an example of the structure of the transmission frame. In the figure, a frame header FH is arranged at the beginning, and then a plurality of preamble slots P
1 to Pl and a plurality of data slots D1 to Dn are sequentially arranged. One frame length is set to 125 μsec, for example, and the number of the data slots D1 to Dn in one frame is set to 4085 slots, for example. Further, the transmission rate of the serial bit stream on the loop transmission line LP is 294.912 Mbps. In the data slots D1 to D4085, the connection device TM1,
The data transmitted from TM2 is, for example, 8B1C encoded or 8B9B encoded and inserted. Multiple stations ST
One of the stations 1 to ST4 serves as a master station, and this master station creates the transmission frame and sends it to the loop transmission line LP. The master station determines the transmission delay of the transmission frame and 125 μse.
has a memory to absorb the difference in the frame period of c,
This memory controls the transmission timing of transmission frames so that the number of transmission frames circulating on the loop transmission line LP becomes an integer.

On the other hand, data transmission is performed between the stations ST1 to ST4 and the connection devices TM1 and TM2 by an interface frame. The structure of this interface frame and its transmission speed are variously set by the connected device. FIG. 8 shows an example of the structure of an interface frame, which is composed of a plurality of data slots C0 to Cm which are time-division multiplexed. One data slot is composed of 8 bits, and the number of data slots in one frame is set to 1023 slots. Then, the length of one interface frame is set to 125 μsec.

In order to transmit such an interface frame, it is necessary for the stations ST1 to ST4 and the connection devices TM1 and TM2 to generate an interface clock synchronized with the clock 8 KHz corresponding to the frame period 125 μsec of the loop transmission frame. There is.
This interface clock is created, for example, by using a PLL circuit or by dividing the clock for data slot transfer in the loop transmission frame. In this way, the interface clock is synchronized with the clock of the loop transmission line LP. However, the mutual phase slightly changes due to slight jitter. If this phase change becomes large, data may be lost.

Therefore, in general, an elastic memory is provided in the interface section of the stations ST1 to ST4 or the connecting devices TM1 and TM2 so as to absorb the phase change due to the jitter or wander. However, the correspondence between the loop transmission frame and the interface frame,
That is, in order to perform frame mapping, it is necessary to provide an elastic memory capable of storing a data slot for two frames on both the transmitting side and the receiving side.

On the other hand, as another structure for absorbing the above phase change, a structure using a double buffer memory has been proposed. The double buffer memory has two buffers, and while the data of the loop transmission frame is being written in one buffer, the stored data is read from the other buffer, inserted into the interface frame, and sent to the connection device. Then, such an operation is performed by switching the buffer for each one loop transmission frame. This buffer switching is performed, for example, during the preamble period of the loop transmission frame.

Using this double buffer memory,
The circuit configuration of the interface unit of the station can be simplified and downsized as compared with the case where the elastic memory is used. In addition, in the circuit using the double buffer memory, even if the loop transmission frame and the interface frame are completely randomly mapped, the data of 125 μsec period in an arbitrary interface frame can reach the connected device at the destination at the same time. You can The reason is that, regarding the transmission of data to the loop transmission line LP, each data of the interface frame transmitted from the connection devices TM1 and TM2 is associated with the data slot of the loop transmission frame, and only 125 μsec worth of data is stored in one buffer. This is because, after being written, the data is read from the buffer and sent to the loop transmission line LP. Therefore, even if the last data slot of the interface frame is allocated to the data slot at the beginning of the loop transmission frame, the data of the same interface frame is transmitted by the same loop transmission frame.

That is, the interface unit using the double buffer system as described above is connected to the connection device TM like the system using the PBX as the connection devices TM1 and TM2.
This is extremely advantageous in a system in which a large number of channels (slots) of data are allocated to empty data slots of a loop transmission frame and transmitted each time a call is made from 1 or TM2.

On the other hand, when transmitting a moving image, the mapping between the interface frame and the loop transmission frame is not random but is performed by continuously allocating the data slot of the interface frame to a plurality of data slots of the loop transmission frame. Be done. For example, moving image data transmitted from a video codec having a transmission rate of 32.064 Mbps is allocated to 501 continuous data slots of a loop transmission frame. Of course, also in this case, it is possible to configure the interface unit by using the double buffer method described above. However, in recent years, moving images have been diversified from high quality images such as hi-vision images to relatively low quality images for video conferences. Therefore, the relative relationship between the preamble period of the loop transmission frame and the data slot period of the interface frame changes greatly, which makes it difficult for one interface unit to handle various moving images.

For example, the length from the frame header FH to the preamble period of the loop transmission frame having one frame length of 125 μsec and the number of slots of 4096 slots is 336 nsec. On the other hand, for example, 32.064 Mb
In the moving image data of ps, assuming that 8 bits are 1 slot, a frame of 125 μsec is constituted by 501 slots. In this case, the cycle per slot is about 250μ
It becomes sec. Therefore, even if this moving image data is handled in units of 8 bits, it is sufficiently possible to switch the buffer of the double buffer memory during the period of 336 nsec.

However, in the case of low-speed moving image data of 1.92 Mbps, assuming that 8 bits are 1 slot, a frame of 125 μsec is constituted by 30 slots. In this case, the period per slot is about 4.17.
It becomes μsec, which is extremely longer than the preamble period. Therefore, it is impossible to handle such moving image data having a slow transmission rate in units of 8 bits and then switch the buffer of the double buffer memory during the preamble period. Also, the preamble period of the loop transmission frame is 4.17 in order to enable switching of the buffer.
If it is expanded to more than μsec, the number of data slots in one frame is reduced accordingly, which is not preferable because it causes a decrease in transmission efficiency. On the other hand, in order to handle high-speed image data having a transmission speed of about 100 Mbps even when compressed, such as a high-definition image, the interface operation must be performed in 1-bit units of the image data.
Therefore, it is necessary to use a high-speed element in the interface section, which causes an increase in circuit cost.

[0014]

As described above, in the conventional loop transmission network system, when the interface between the loop transmission frame and the interface frame is performed, a double buffer memory is provided in the interface portion and the double buffer memory is provided. The buffer of the memory is switched in units of slots of the interface frame by using the preamble period of the loop transmission frame. Therefore, in order to support various transmission speeds of connected devices, the preamble period of the loop transmission frame should be lengthened at the expense of transmission efficiency, or
The interface frame had to be handled on a bit-by-bit basis in preparation for the cost increase of the interface circuit.

The present invention has been made in view of the above circumstances, and an object of the present invention is to cope with various transmission speeds possessed by a connected device without lowering transmission efficiency and increasing interface circuit cost. It is to provide a loop transmission network system capable of performing.

[0016]

In order to achieve the above object, the present invention uses a loop transmission frame in which a plurality of stations are connected in a loop via a loop transmission line and circulates on the loop transmission line. A loop transmission system for performing data transmission between the stations, and an interface transmission system for connecting data to each of the stations via a transmission path and performing data transmission using interface frames between the connection equipment and the stations. In the loop transmission network system for transmitting and receiving data between the loop transmission frame and the interface frame in each station, to each station,
A dual port buffer memory having a storage area for at least two frames that can be independently transmitted and received, an access control unit for the dual port buffer memory, and an address movement control unit are provided. And
The access control means performs time division access to the dual port buffer memory from the loop transmission system side and the interface transmission system side to write and read data, and the address movement control means controls the dual port buffer memory. A comparison is made between the access address from the loop transmission system side to the access address from the interface transmission system side, and when both addresses match, the access address from the interface transmission system side is shifted by one frame. Is.

[0017]

As a result, according to the present invention, the dual port buffer memory having the buffer area for two frames is cyclically accessed from the interface transmission system side and the loop transmission system side, for example, the hour hand and the minute hand of a clock. Will be. Therefore, no matter what the relationship between the transmission speed on the interface transmission system side and the transmission speed on the loop transmission system side, the speed difference can be sufficiently absorbed. Therefore, even when the transmission speed of the connected device is a low speed such as 1.92 Mbps, the loop transmission frame and the interface frame can be transmitted between the loop transmission frame and the interface frame without increasing the preamble period of the loop transmission frame, that is, without sacrificing the transmission efficiency. Interface is possible. On the other hand, even if the transmission speed of the connected device is high such as when handling high-definition images, the interface between the loop transmission frame and the interface frame should be performed without using a high-speed element in the interface section. This makes it possible to provide the interface section at low cost.

Further, according to the present invention, when the access address from the interface transmission system side and the access address from the loop transmission system side are likely to coincide with each other during the access to the dual port buffer memory, the loop transmission system side. Or the access address from the interface transmission side is shifted by one frame. Therefore, it is possible to prevent a problem that the access from the interface transmission system side and the access from the loop transmission system side to the buffer memory collide with each other, whereby the interface operation with high operation reliability can be realized.

[0019]

EXAMPLES The present invention will be described below based on examples.

FIG. 1 is a circuit block diagram showing a configuration of a reception interface system of a station to which an interface system of a loop transmission network system according to an embodiment of the present invention is applied. 10 is a receiving unit of the loop transmission system. Again 20
Indicates the interface reception system, respectively.

The receiver 10 of the loop transmission system includes a receiver 11
The serial-to-parallel converter 12, the frame header detection unit (FH detection unit) 13, the 9-ary counter 14, and the latch 15. The receiver 11 receives the loop transmission frame transmitted from the upstream side via the loop transmission line LP. The serial-to-parallel converter 12 converts the data received by the receiver 11 from serial format to parallel format for each data slot (9 bits). FH detector 1
In 3, the frame header FH in the loop transmission frame received by the receiver 11 is detected, and the detection signal is input to the 9-ary counter 14. 9-base counter 1
Reference numeral 4 denotes a signal which is synchronized with each slot (9 bits) of the loop transmission frame, and which is generated by the FH detector 39
Is initialized every time the FH detection signal is input from the receiver, and the loop slot synchronization signal is output each time the loop transmission clock supplied from the receiver 11 via the FH detection unit 13 is counted by 9 bits. The latch 15 temporarily stores the 8-bit data required by the connection device TM among the parallel data of 9-bit configuration output from the serial-to-parallel converter 12. The data is transferred to the word latch 22 of the interface receiving system 20 in synchronization with the loop slot synchronization signal generated from the counter 14.

The interface reception system 20 is roughly divided into a clock generation circuit system, a data storage transfer circuit system, a memory access control circuit system, and an address shift control circuit system. Of these, first, the clock generation circuit system is the PLL circuit 3
1, a division ratio register 32, and an octal counter 33. The PLL circuit 31 synchronizes with the FH detection signal output from the FH detection unit 13 and has an interface clock (65.536 MHz) IF having a frequency corresponding to the frequency division ratio stored in advance in the frequency division ratio register 32.
Generate C. The octal counter 33 includes the PLL circuit 3
8 the interface clock IFC generated by 1
A signal is output each time a count is made. This signal is a signal representing slot synchronization of the interface frame.

The data storage / transfer circuit system comprises a dual mode buffer memory 21, a word latch 22, a data selector 23, a byte latch 24, and a parallel-to-serial converter 25. The dual mode buffer memory 21 is
It has two frame memories each capable of storing the received data of one frame of the loop transmission frame. These frame memories have independent data writing / writing.
A read port is provided. The word latch 22 is
The reception slot data transferred from the latch 15 of the loop transmission system receiver 10 is temporarily stored for 2 bytes in synchronization with the loop slot synchronization signal output from the 9-ary counter 14 of the loop transmission system receiver 10. , To the two frame memories of the dual mode buffer memory 21. The data selector 23 converts the received data read from the two frame memories of the dual mode buffer memory 21 into an address selector 36 described later.
The signal is selectively selected according to the selection signal output from and is supplied to the byte latch 24. The byte latch 24 temporarily stores the received data supplied from the data selector 23 in byte units. The parallel-to-serial converter 25 converts the received data supplied from the byte latch 24 from parallel format to serial format in synchronization with the signal output from the octal counter 33, and outputs this serial data as interface data. To do.

The memory access control circuit system includes a loop slot counter 41, an interface slot counter (I / F slot counter) 42, a slot number register 43, an adder 44, and an interface MSB register (I / FMSB register) 45. A start register 46, an address selector 47, and a read / write controller (R / W controller) 48.

The loop slot counter 41 counts the loop slot synchronization signal output from the 9-ary counter 14 of the loop transmission system receiver 10 and outputs the count output to the address selector 47 as a write address. The write address is initialized by the FH detection signal output from the FH detection unit 13. The I / F slot counter 42 counts the I / F slot synchronization signal output from the octal counter 33 and supplies the count output to the adder 44. The count value of the I / F slot counter 42 is initialized when it becomes equal to the number of data slots of the interface frame stored in the slot number register 43. The adder 44 is
The count output value supplied from the I / F slot counter 42 is added to the initial value of the read address output from the start register 46, and the added output is supplied to the address selector 47 as the read address. R / W
The control unit 48 synchronizes with the loop slot synchronization signal output from the 9-ary counter 14 and the I / F slot synchronization signal output from the 8-ary counter 33, and a read / write timing signal (R / W timing signal). To generate. The address register 47 selects the write address output from the loop slot counter 41 in the write period according to the R / W timing signal supplied from the R / W control unit 48 to select the dual port buffer memory 21.
On the other hand, during the read period, the read address output from the adder 44 is selected and supplied to the dual port buffer memory 21.

The address shift control circuit system includes an address latch 51, an address coincidence detection section 52, and a loop address MSB control section 53. Address latch 5
1 temporarily stores the read address output from the adder 44 and then supplies the read address to the address coincidence detection unit 52.
The address coincidence detection unit 52 compares the read address supplied from the address latch 51 with the write address output from the loop slot counter 41,
When both addresses match, a match signal is generated. The loop address MSB control unit 53 receives the write address M in response to the match signal generated from the address match detection unit.
SB is shifted by one frame.

Next, the operation of the reception interface system configured as described above will be described. Assuming that the interface frame has 1024 8-bit width data slots in 125 μsec as shown in FIG. 8, the serial bit stream speed of the interface frame is 65. 536 Mb
It becomes ps. Then, assuming that the data slot of this interface frame is allocated to the 1024 data slots in the loop transmission frame, the PLL circuit 3
The division ratio to be input to 1 is set to 8191, the number of slots to be input to the I / F slot counter 42 is set to 1023, and the start register 46 is set to 204
8 may be set.

With this setting, the count value of the loop slot counter 41, that is, the write address is F
Each time the H detection unit 13 detects the frame header FH, it is initialized to "0000" or "1000". Then, from this initialized state, it is incremented by 1 every time the loop slot synchronization signal is output from the 9-ary counter 14.

On the other hand, the read address output from the adder 44 in the I / F slot counter 42 is
The I / F slot synchronization signal output from the octal counter 33 is counted to sequentially increase. And
This count value is the number of data slots (10
23), the MSB is inverted by the I / FMSB register 45. That is, the frame switching of the read address is performed by this inversion.

Therefore, in the dual port buffer memory 21, for example, as shown in FIG. 2, the reception data for one frame of the loop transmission frame is sequentially written in the writing periods Twa and Twb, and the next 1 is written in the writing periods Twc and Twd. Received data for frames are sequentially written. In the write periods Twb and Twd, the read periods TRa, TRb and the read periods TRc, TRd are set by time division multiple access, respectively, and the received data is read in the read periods TRa, TRb and TRc, TRd, respectively. Is performed. Then, the read reception data is converted into a serial format by the parallel-to-serial converter 25 via the byte latch 24, then inserted into each data slot of the interface frame and sent out to the connected device.

By the way, as in the case shown in FIG. 2, the count value of the I / F slot counter 42 is "00".
When it becomes "00", the frame header FH is accidentally detected by the FH detection unit 13, and the loop slot counter 41
It is assumed that the write address output from is "0000". In this case, the read periods TRa and TRb are set by the time division multiple access in the write period Twb. Therefore, the read address is overtaken and overtaken by the write address. This means that the data received from the loop transmission system is replaced with the old one in the middle of one frame, which is not preferable. Also, the interface clock IFC
Is generated by the PLL circuit 31, the interface clock IFC and the clock of the loop transmission system are theoretically synchronized. However, if the clock generated by the PLL circuit 31 contains a subtle phase variation due to jitter or wander, the relationship between the write address and the read address varies slightly due to the influence thereof. And
If this minute change occurs at the coincidence point between the write address and the read address as described above with reference to FIG. 2, for example, the same data is read twice from the dual port buffer memory 21. There may be a problem that the data of is lost.

However, in the circuit of this embodiment, the address coincidence detecting section 52 monitors whether or not the write address and the read address coincide with each other. Then, when a match between both addresses is detected, a match detection signal is supplied to the loop address MSB control unit 53, whereby the MSB of the write address is inverted. Therefore, the write address supplied to the dual port buffer memory 21 is shifted by one frame. Therefore, for example, as shown in FIG. 3, the write address and the read address are always sufficiently separated from each other, and as a result, the received data is 1
It is possible to reliably prevent the occurrence of problems such as replacement of old and new in the middle of a frame and data loss due to phase fluctuation of the interface clock IFC.

Further, the circuit of this embodiment can easily cope with various transmission speeds of the connected equipment. For example, if the transmission speed of the connected device is 32.064 Mbps, which is a high speed,
The frequency division number of the frequency division ratio register 32 attached to the PLL circuit 31 is set to 4007, and the slot number register 4
3, the number of slots is set to 500, and the PLL circuit 31
The voltage control oscillator (VCO) or the voltage control crystal oscillator (VCXO) that composes
You can change to the one.

Further, the transmission speed of the connected equipment is 1.9, which is low.
In the case of 2 Mbps, the frequency division number of the frequency division ratio register 32 is set to 239, the slot number 29 is set to the slot number register 43, and the VC of the PLL circuit 31 is set.
O or VCXO may be changed to a transmission frequency of 1.92 Mbps.

Thus, in this embodiment, the loop transmission line L
A station arranged on P is provided with a dual port buffer memory 21 having a storage area for two frames, and the write address generated by the loop slot counter 41 and the I / F are supplied to this dual port buffer memory 21. The read address generated by the slot counter 42 and the like is supplied in a time division manner to write and read the received data, respectively, and the write address and the read address are compared by the address coincidence detection section 52, and both addresses coincide. In this case, the loop address MSB controller 53 shifts the write address by one frame.

Therefore, when connected devices having different transmission speeds are used, it is possible to easily and surely cope with the change by simply changing the generation of the read address according to this speed. Therefore, even when the transmission speed of the connected device is as low as 1.92 Mbps, for example, the preamble period of the loop transmission frame is not lengthened, that is, the transmission efficiency is not sacrificed, and the loop transmission frame and the interface frame are not transmitted. Interface is possible. In addition, even if the transmission speed of the connected device is high, such as when handling high-definition images,
The interface section can be interfaced between the loop transmission frame and the interface frame without using a high-speed element, and thus the interface section can be provided at a low cost.

Further, according to the present embodiment, when the write address catches up with the read address during the read of the received data and both the addresses match, the write address is shifted by one frame at that time. For this reason, the write address and the read address are always sufficiently separated from each other, and as a result, the received data is replaced with the old one in the middle of one frame, or the data is lost due to the phase fluctuation of the interface clock IFC. Is reliably prevented.

Further, in the present embodiment, the read address is set to the address latch 5 when the above address matching is detected.
After being latched at 1, the data is read in synchronization with the write timing, and the write address at that time is compared with the address match detection unit 52. Therefore, the address match detection unit 52 can always perform stable address comparison. That is, 9 for writing address increment
Microscopically, the decimal counter 14 and the octal counter 33 for reading address increments operate independently of each other and asynchronously. For this reason, these 9-counter counters 14 and 8
The generation timings of the count values generated by the advance counter 33 may be shifted from each other, and this shift may prevent correct address comparison. However, in the present embodiment, as described above, the read address is latched by the address latch 51 and then read in synchronization with the write timing and compared with the write address. Even if there is a shift, stable address comparison can always be performed.

Further, in the present embodiment, the received data from the loop transmission system is latched by the word latch 22 for two slots and then written in the buffer memory 21. Therefore, the access time limit of the buffer memory 21 can be relaxed. In other words, it is possible to use a buffer memory having a long access time, which makes it possible to further reduce the cost of the circuit.

When a 4096-slot frame is used as a loop transmission frame as in this embodiment, about 61 nsec is required to write the 2-byte received data transmitted by this frame. Therefore, the R / W control unit 48 causes the above 61 nse.
30.5 nsec of c is fixedly assigned as a writing period, and the reception slot data latched by the word latch 22 is written in the buffer memory 21 during this period. On the other hand, for reading, as shown in FIG. 4, the remaining 30.5 nsec of the 61 nsec is assigned as the readable period, and the actual read request is 8
Each time it is output from the binary counter 33, the buffer memory 21 is actually read during the closest readable period from that point. The above operation is similarly performed when the speed of the connected device is low, only by increasing the interval between read requests.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the case where the data slot of the interface frame is continuously allocated to the loop transmission system frame for the data transmission between the connected devices has been described. However, the data slot of the interface frame is allocated to the loop transmission system frame. May be assigned monotonically as shown in FIG. In addition,
In this case, a map memory in which allocation information is stored in advance is used for the adder 44. That is, since the change of the write address in this case increases monotonically, if the read address is also set to change monotonically, the write address and the read address do not cross each other during the reading. be able to.

In the above embodiment, the write address is shifted by one frame when a match between the write address and the read address is detected. Instead, the read address is shifted by one frame. You may.

Further, in the above-described embodiment, the case where the received data sent by the loop transmission system is applied to the receiving system for transmitting to the connecting device has been described as an example, but the transmitting data sent from the connecting device via the interface frame is described. The present invention can be similarly applied to a transmission system that sends a signal to a loop transmission system. When applied to the transmission system, the flow of data is made opposite to that of the reception system, and the transmission data from the start address to the end address is read from the dual port buffer memory 21 and the transmission request is output to be sent to the loop transmission system. It may be configured to do so.

In the above embodiment, the received data is latched by the word latch 22 for two slots and then written in the buffer memory 21, but when the access time of the buffer memory 21 is short, the word latch 22 is used.
The latch amount at 1 may be set to only one slot. On the contrary, when the access time of the buffer memory 21 is long, the amount of slot data to be latched by the word latch 22 may be increased.

In addition, the configuration of the dual port buffer memory, the configuration of the memory access control means and the address moving means, the configuration of the loop transmission frame and the interface frame, etc. can be variously modified and implemented without departing from the gist of the present invention. .

[0046]

As described in detail above, according to the present invention, each station provided on the loop transmission line has a dual port buffer memory having a storage area for at least two frames which can be independently transmitted and received, and this dual port buffer. A memory access control unit and an address movement control unit are provided, and the access control unit performs time division access to the dual port buffer memory from the loop transmission system side and the interface transmission system side to write and read data. In addition, the address transfer control means compares the access address from the loop transmission system side with respect to the dual port buffer memory and the access address from the interface transmission system side, and if both addresses match, the interface transmission system side From The scan address is obtained so as to one frame shift movement.

Therefore, according to the present invention, it is possible to provide a loop transmission network system capable of coping with various transmission speeds of the connected equipment without lowering the transmission efficiency and increasing the cost of the interface circuit.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of a reception interface system of a station to which an interface system of a loop transmission network system according to an embodiment of the present invention is applied.

FIG. 2 is a diagram for explaining a reception interface operation by the circuit shown in FIG.

FIG. 3 is a diagram for explaining a reception interface operation by the circuit shown in FIG.

FIG. 4 is a diagram for explaining a reception interface operation by the circuit shown in FIG.

FIG. 5 is a diagram for explaining an interface method according to another embodiment of the present invention.

FIG. 6 is a schematic configuration diagram of a conventional loop type local area network system.

FIG. 7 is a diagram showing an example of a configuration of a transmission frame.

FIG. 8 is a diagram showing an example of a configuration of an interface frame.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Loop transmission system receiving section 11 ... Receiver 12 ... Serial-to-parallel converter 13 ... Frame header (FH) detecting section 14 ... 9-ary counter 15 ... Latch 20 ... Interface receiving system 21 ... Dual port buffer memory 22 ... Word Latch 23 ... Data selector 24 ... Byte latch 25 ... Parallel-to-serial converter 31 ... PLL circuit 32 ... Division ratio register 33 ... Octal counter 41 ... Loop slot counter 42 ... I / F slot counter 43 ... Slot number register 44 ... Addition Container 45 ... I / FMS
B register 46 ... Start register 47 ... Address selector 48 ... Read / write (R / W) control unit 51 ... Address latch 52 ... Address match detection unit 53 ... Loop address MSB control unit

Claims (1)

[Claims] 1. A loop transmission system in which a plurality of stations are connected in a loop via a loop transmission line, and data is transmitted between the stations using a loop transmission frame that circulates on the loop transmission line, and each of the stations. An interface transmission system for connecting data to the connection device via a transmission path and performing data transmission using the interface frame between the connection device and the station, and the data between the loop transmission frame and the interface frame. In the loop transmission network system for transmitting / receiving data to / from each of the stations, each station includes a dual port buffer memory having a storage area for at least two frames which can be independently transmitted / received, and the loop transmission to / from the dual port buffer memory. Data is accessed by time division access from the system side and interface transmission side. The access control means for performing writing and reading is compared with the access address from the loop transmission system side to the dual port buffer memory by the access control means and the access address from the interface transmission system side, and both addresses match. And an address moving means for shifting the access address from the interface transmission system side by one frame in this case.