JP2771514B2 - Speed conversion circuit and data transmission device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speed conversion circuit for performing speed conversion of transmission data and a data transmission device using the same, and more particularly to buffer control of a buffer provided in the speed conversion circuit.

[0002]

2. Description of the Related Art Recently, data with a demand assigning function for accommodating general data terminals, voice terminals, frame relay terminals, etc., and performing on-demand bandwidth allocation of data terminals and voice terminals to transmission line bands. Transmission devices are beginning to be used. In such a data transmission device, the bandwidth allocated to the on-demand terminal and the frame relay terminal can be dynamically changed during the operation of the system. The transmission path band can be used more efficiently than the device.

In such a data transmission apparatus, a transmission path band is divided into an on-demand band which is set each time by a request from a terminal and a frame relay band allocated to a frame relay terminal. Therefore, when a connection request is generated from an on-demand terminal, the on-demand band changes in response to the request, and the frame relay band dynamically changes.

On the other hand, in the process of data transmission, it is often necessary to convert data of a certain speed into data of another predetermined speed. In the case of using the above-described data transmission device, However, such a speed conversion process is required. In order to realize such data speed conversion, a speed conversion circuit using a buffer or the like is used. For example, Japanese Patent Application Laid-Open No. 56-93446 (title of invention; speed change circuit) and Japanese Utility Model Application Laid-Open No. 64-8860. Patent Document (Title of Invention; Speed change circuit).

[0005] The speed conversion circuits described in these documents have buffers for the number of bits equal to the block length of the blocks constituting the transmission data, and are shifted by the number determined by the speed ratio between the input data speed and the output data speed. It consists of registers. On the input side of these shift registers, a gate circuit for inputting each bit in the block to the shift register according to the data rate of the input side is provided, and on the output side, each bit in the block is output. A gate circuit for reading from the shift register according to the data rate is provided. As described above, in the conventional speed conversion circuit, the capacity of the buffer is configured to a fixed value corresponding to the block length of the transmission data.

[0006]

By the way, recently, various media such as voice, facsimile, and image have been transmitted by using the above-described data transmission apparatus in addition to simple data on a frame relay. Is coming.
For this reason, such data transmission devices are required to have real-time characteristics, and transmission delays of the data transmission devices themselves have become apparent.

However, when the above-described conventional speed conversion circuit is applied in such a situation, the following problems occur. That is, in the speed conversion circuit having a fixed buffer capacity as described above, the time required to write and read data to and from the prepared buffer changes due to a change in the frame relay data speed (clock). . That is, every time the data rate changes, the delay amount of the data passing through the buffer changes greatly.

[0008] In addition, in the above speed conversion circuit,
In order to suppress the buffer underflow when the speed of the frame relay data changes, it is necessary to always store a certain amount of data in the buffer.
Therefore, there is a problem that the data passing through the buffer (that is, the data transmission device) is delayed more than necessary.

The present invention has been made in view of the above points, and a first object of the present invention is to provide a speed conversion circuit having a small change in the amount of data delay even when the data speed changes, and a data transmission using the same. It is to provide a device. It is a second object of the present invention to provide a speed conversion circuit which does not unnecessarily delay data passing through a buffer and has a small data delay amount, and a data transmission device using the same.

[0010]

According to a first aspect of the present invention, there is provided a speed conversion circuit having a buffer in which transmission data is stored, based on a writing speed to the buffer. A delay amount for controlling timing of writing and reading of the buffer such that a delay amount from a start time of writing the buffer to a start time of reading of the buffer becomes substantially equal to a minimum delay amount at a maximum speed of the transmission data. It is characterized by comprising setting means.

According to a second aspect of the present invention, in a speed conversion circuit having a buffer for storing transmission data,
It is characterized by comprising a buffer capacity setting means for setting an upper limit of an address to be written to the buffer and an upper limit of an address to be read from the buffer based on a writing speed to the buffer.

According to a third aspect of the present invention, there is provided a data transmission apparatus for performing data transmission on a transmission path to which a band is allocated to a frame relay terminal and an on-demand terminal having priority over the frame relay terminal. Based on a connection request sent from the opposite station, a band allocation control unit that generates band information on a band relay band to be allocated to the frame relay terminal and band allocation on a transmission path of the on-demand band to be allocated to the on-demand terminal, A speed control unit that controls a data transmission speed of the frame relay terminal based on the band information, and buffers transmission data transmitted from the frame relay terminal based on a data transmission speed of the frame relay terminal. A speed conversion circuit according to 1 or 2,
Multiplexing means for transferring the transmission data buffered in the speed conversion circuit to the frame relay band based on the connection request.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing a connection relationship between a data transmission device 50 according to the present embodiment and terminals and the like connected to the data transmission device 50. The data transmission device 50 includes a buffer (see FIG. 1) described later. In FIG. 2, an on-demand terminal 51 and a frame relay terminal 52 are accommodated on the low-speed side. The frame relay terminal 52 operates according to the frame relay clock FC sent from the data transmission device 50, and
The side can control the signal transmission speed of the frame relay terminal 52.

The bandwidth on the transmission line is assigned mainly by the connection request from the on-demand terminal 51 while sharing the transmission line band between the terminals.
That is, the connection request from the on-demand terminal 51 is prioritized and a band is allocated, and the remaining band is allocated for the frame relay terminal 52. Here, the on-demand terminal 51 and the frame relay terminal 52
Are configured to exchange an on-demand system main signal DM and a frame relay main signal FR with the data transmission device 50, respectively.

Next, in the data transmission device 50, the on-demand system main signal DM is directly supplied to the multiplexing / demultiplexing circuit 53. On the other hand, the frame relay main signal FR is supplied to the multiplexing / demultiplexing circuit 53 via a buffer 56 described later. The multiplexing / demultiplexing circuit 53 changes the allocation of the time slot in the time switch input / output based on the bandwidth allocation information AI of the transmission line generated by the bandwidth allocation control circuit 58 described later. In addition, the time switch circuit 54
Based on the same band allocation information AI, connection / disconnection of the path on the transmission path is performed.

The line interface 55 connected between the data transmission device 50 and the transmission line is provided with a multiplexing / demultiplexing circuit 5.
This is a circuit for taking an interface between the main signal multiplexed through the third and time switch circuits 54 and the transmission line. The buffer 56 is provided in a portion of the data transmission device 50 that receives a signal transmitted from the frame relay terminal 52. The buffer 56 converts a signal transmitted from the frame relay terminal 52 into a frame relay band assigned to a transmission path. It functions as a buffer area for changing to a new one. The detailed configuration of the buffer 56 will be described later.

Frame relay clock generation circuit 57
Is based on the frame relay band information FI output from the band allocation control circuit 58 described below, the clock speed information CI given to the buffer 56, and the frame relay terminal 52
, A frame relay clock FC (described above) to be given to the CPU. This frame relay clock generation circuit 57
A counter (not shown) is built in, and the frequency of the frame relay clock FC is controlled by changing the frequency division ratio of the built-in counter. Note that the clock speed information CI may be, for example, data in which a speed value in a case where the clock speed is expressed in units of kilobits per second (kbps) is expressed in binary. The clock speed information CI includes
Write information WI and read speed information RI described later
(See FIG. 1).

The band allocation control circuit 58 generates band allocation information AI (described above) based on information of a path connection request CR transmitted from the on-demand terminal 51 or an opposite station (not shown) via a transmission line. I do. As the signal indicating the connection request CR, for example, a plurality of preset multiplexing modes are represented by a binary code, and a binary code that designates one of these multiplexing modes is used. It should be expressed in.

FIG. 1 is a block diagram showing a configuration of the buffer 56 described above. Hereinafter, each component of the buffer 56 will be described. First, the configuration on the writing side will be described. In the figure, a memory 1 is a storage medium as a main element of a buffer, a terminal DI is a terminal to which write data WD from the frame relay terminal 52 is input, and a terminal DO is a read data R to be transmitted to the transmission line side.
A terminal to which D is output, a terminal WADR is a terminal to which a write address WA to the memory 1 is input, a terminal RADR is a terminal to which a read address RA to the memory 1 is input, and terminals WR and RD are to write to the memory 1, respectively. Terminal for controlling reading.

The register 2 is a register for storing write speed information, and is based on the write speed information WI.
The upper limit address for writing to the memory 1 is determined and output to the comparator 3 described below. The method of determining the address upper limit will be described later. The comparator 3 outputs a pulse for resetting a write address generation counter 4 described later when the write address WA given to the memory 1 matches the address upper limit value output from the register 2.

The write address generation counter 4 is shown in FIG.
Is a counter that operates according to the frame relay clock FC sent from the frame relay clock generation circuit 57, and writes the count value of the counter to the write address WA.
To the memory 1. The write address initialization circuit 5 generates a pulse having a certain phase difference with respect to the internal reference phase pulse RP based on the write speed information WI, the internal reference phase pulse RP, and the frame relay clock FC (details). Will be described later). For this purpose, the write address initialization circuit 5 sets the internal reference phase pulse R
It is composed of a binary counter that is reset by P, and a circuit that decodes the output of the counter and generates the pulse.

The OR circuit 6 performs OR (logical sum) of the pulse output from the write address initialization circuit 5 and the reset pulse output from the comparator 3 to reset (RESET) the write address generation counter 4. Send to input terminal. As you can see, basically,
The write operation to the memory 1 is performed on the write address WA generated by the write address generation counter 4 according to the frame relay clock FC in synchronization with the frame relay clock FC. At this time, how far the write address WA is incremented in accordance with the frame relay clock FC is determined by the address upper limit value generated by the register 2 based on the write speed information WI sent from the device side.

Next, the configuration on the reading side will be described.
First, the register 7 is a register for storing read speed information. The register 7 determines an address upper limit value when reading the memory 1 based on the read speed information RI, and outputs the upper limit value to the comparator 8 described below. The method of determining the address upper limit will be described later. Comparator 8
Outputs a signal for holding the read address generation counter 9 when the read address RA given to the memory 1 matches the address upper limit value output from the register 7.

The read address generation counter 9 is a counter that operates according to the internal clock DC of the data transmission device 50, and supplies the count value of the counter to the memory 1 as a read address RA. The read address generation counter 9 is reset by the internal reference phase pulse RP connected to the reset terminal, and is held by the output signal from the comparator 8 connected to the hold (HOLD) terminal.

As can be seen from the above, the read operation from the memory 1 is performed by the read address RA generated by the read address generation counter 9 in accordance with the internal clock DC.
Is performed in bursts in synchronization with the internal clock DC. The extent to which the read address RA is incremented according to the in-device reference phase pulse RP is determined by the address upper limit value generated by the register 7 based on the read speed information RI sent from the device.

Next, a procedure for determining various parameters including the above address upper limit value will be described with reference to FIGS. In these figures, the horizontal axis represents time t,
The vertical axis is the read address RA or the write address WA given to the memory 1. Also, the address upper limit value A
_H and the address upper limit value _AL are the address upper limit values during high-speed processing and low-speed processing, respectively. The time T _dL and the time T _dH will be described later.

First, FIG. 3 shows a frame relay clock F.
This shows how the write address WA and the read address RA given to the memory 1 change when the speed of C is somewhat lower. On the other hand, FIG. 4 shows a case where the speed of the frame relay clock FC is somewhat higher. In these figures, line 7
1, 73 indicate changes in the write address WA, and lines 72, 74 indicate changes in the read address RA.

Here, it is assumed that the read speed is higher than the write speed to the buffer 56. That is, in FIG. 3 or FIG. 4, the inclination of the lines 72 and 74 during the period when the read address RA is increasing is larger than the inclination of the lines 71 and 73 during the period when the write address WA is increasing. It shall be steep. Also, in the case of the same device, the clock DC in the device does not change, and the slopes of the lines 72 and 74 are equal.

First, the time T _dH (see FIG. 4) is set such that the read address RA is equal to the write address WA even when the operating condition of the data transmission device 50 (ie, the data rate from the frame relay terminal 52) is the maximum. Set so that the following conditions are satisfied within the range not overtaken. That is, the delay of the reset signal applied to the read address generation counter 9 with respect to the reset signal applied to the write address generation counter 4 (that is, the buffer passage delay time)
There so as to minimize the time T _dH is set.

That is, in FIG. 4, the address of each line is set to "zero" within a range where the line 73 during the period when the write address WA is increasing does not intersect with the line 74 during the period when the read address RA is increasing. The change phase of the write address WA is adjusted so that the point "" comes closest. This is because the delay in the data transmission device 50 can be minimized when writing / reading of the buffer 56 is performed with the in-device reference phase pulse Rp, because the data speed is maximum.

The adjustment of the change phase is realized by resetting the write address generation counter 4 and resetting the write address WA to zero. That is, since the write address initialization circuit 5 is provided with the binary counter as described above, the output of the binary counter is decoded based on the operating condition information of the apparatus including the write speed information WI to perform address initialization. For the write address generation counter 4 via the OR circuit 6.

On the other hand, the time T _dL is set so as to be in a range equal to or less than the time T _dH and to be a value closest to this. That is, in FIG. 3, the line 71 during the period when the write address WA is increasing and the line 71 during the period when the read address RA is increasing.
The address of each line is "zero" within the range where 2 does not intersect
The change phase of the write address WA is adjusted so that the point (2) comes closest.

On the other hand, the address upper limit values A _H and A _L are inevitably determined when the times T _dH and T _dL are determined, and the increasing speed of the write address WA obtained from the clock speed information CI (ie, the line 71). , 73) and time T _dH
And the time _TdL . That is, in each case of FIGS. 3 and 4, the time T _dL and the time T
Under the condition of _dH , lines 71 and 72 or lines 73 and 74
Are set as the maximum values of addresses that do not intersect. By performing the above setting, the data delay when passing through the buffer 56 is kept substantially constant without depending on the increase or decrease of the frame relay band.

Next, the data transmission device 50 having the above configuration will be described.
Will be described. First, the case where the frame relay band decreases, that is, the case where the speed of the frame relay clock FC decreases will be described. Data transmission device 50
In FIG. 2, when the bandwidth allocation control circuit 58 detects a connection request CR from the on-demand terminal 51 or the opposite station, the bandwidth allocation information AI is multiplexed to set a new path for the on-demand system main signal DM. Notify the separation circuit 53 and the time switch circuit 54.

The band allocation control circuit 58 changes the frame relay band information FI to be sent to the frame relay clock generation circuit 57 in parallel with this processing. Here, when the band allocation control circuit 58 detects the connection request CR, the band on the transmission line band is surrendered to the on-demand system main signal DM, so that the frame relay band allocated to the frame relay terminal 52 is narrowed. Is processed in the direction in which

When the frame relay clock generation circuit 57 receives the changed frame relay band information FI, the frequency division ratio of the built-in counter is increased to decrease the frequency of the frame relay clock FC, and at the same time, the clock speed information CI To notify the buffer 56 that the clock speed of the frame relay clock FC has dropped.

The clock speed information CI sent to the buffer 56 is input to the register 2, the write address initialization circuit 5, and the register 7 in FIG. Register 2,
The register 7 calculates an address upper limit value A _L (see FIG. 3) corresponding to the speed indicated by each speed information included in the clock speed information CI according to the above-described procedure. On the other hand, the write address initialization circuit 5 calculates a relative value of the reset phase of the write address generation counter 4 with respect to the reset phase of the read address generation counter 9 based on the clock speed information CI and the internal reference phase pulse RP.

Thereafter, the data transmission device 50 repeatedly performs the following processing. At time t ₀ shown in FIG. 3, consistent with the address limit A _L of the write address WA is the output of the register 2, when the reset pulse from the comparator 3 is output, the write address generating counter 4 is reset The write address WA becomes zero. After that, the frame relay clock FC
Therefore, the frame relay main signal FR sent from the frame relay terminal 52 is sequentially written to the memory 1 as the write data WD in accordance with the write address WA.

Thereafter, the write address generation counter 4
Is reset at time t ₁ when the time T _dL has elapsed, the internal reference phase pulse RP is output. As a result, the read address generation counter 9 is reset, the read address RA becomes zero, and then the read address generation counter 9 counts up according to the internal clock DC. That is, the read address RA
The read data RD is read out from the memory 1 in a burst manner as the number of bits increases. This read data RD
Is transmitted to a transmission line via a multiplexing / demultiplexing circuit 53, a time switch circuit 54, and a line interface 55.

On the other hand, in parallel with this read operation, at time t
In _2, coincides with the address limit A _L value of the write address WA is the output of the register 2, comparators 3 outputs a reset pulse, the write address generating counter 4 is reset. As a result, the write address WA becomes zero, and the write data WD is written to the memory 1 in order from the address “zero” of the memory 1 again.

[0041] On the other hand, at time t _3, matches the address limit A _L of the read address RA outputted from the register 7, a reset pulse from the comparator 8 is output, the value of the read address generating counter 9 is held, The read address RA is held at the address upper limit value _AL , and the read operation stops. Thereafter, at time t ₄ , the internal reference phase pulse RP is output again, the read address generation counter 9 is reset, and the read data RD is read from the memory 1 again in order from the address “zero” of the memory 1 again. go.

Next, a case where the frame relay band increases, that is, a case where the speed of the frame relay clock FC increases will be described. Data transmission device 5 shown in FIG.
0, when the band allocation control circuit 58 detects the release of the connection request CR from the on-demand terminal 51 or the opposite station, the band allocation information AI is multiplexed to release the path for the on-demand system main signal DM. This is notified to the separation circuit 53 and the time switch circuit 54.

The band allocation control circuit 58 changes the frame relay band information FI to be sent to the frame relay clock generation circuit 57 in parallel with this processing. Here, when the band allocation control circuit 58 detects the release of the connection request, the band relay terminal 52 is required to surrender the band corresponding to the on-demand system main signal DM from the band on the transmission line band. The assigned frame relay band will be processed in the direction in which it is expanded.

Then, the frame relay clock generation circuit 57 receives the changed frame relay band information FI, lowers the frequency division ratio of the built-in counter to increase the frequency of the frame relay clock FC, and at the same time, converts the clock speed information CI. Then, the buffer 56 is notified that the clock speed of the frame relay clock FC has increased.

The clock speed information CI sent to the buffer 56 is input to the register 2, write address initialization circuit 5, and register 7 of FIG. The address upper limit value A _H (see FIG. 4) corresponding to the speed value indicated by CI is calculated according to the above-described procedure. Further, the write address initialization circuit 5 calculates the relative position of the reset phase of the write address generation counter 4 with respect to the reset phase of the read address generation counter 9 based on the clock speed information CI and the internal reference phase pulse RP.

Thus, based on the address upper limit value A _H and the time T _dH , the write operation and the read operation for the memory 1 are performed in the same manner as described with reference to FIG. As described above, according to the present embodiment, once the bandwidth of the transmission path is determined, the amount of delay generated inside the data transmission device can be controlled to be minimum and substantially constant, and various types of media information as described above can be stored in a frame. It becomes possible to transmit on the relay band without any problem.

[0047]

As described above, according to the first aspect of the present invention, the writing and reading of the buffer are controlled based on the writing speed of the buffer so that the amount of delay by the buffer becomes substantially the minimum value. So that the buffer delay can be close to the minimum delay at the maximum data rate at any data rate,
Therefore, it is possible to minimize the amount of delay of transmission data passing through the speed conversion circuit, and it is possible to obtain an effect that unnecessary delay due to a buffer can be eliminated.

According to the second aspect of the present invention, the upper limit value of the access address to the buffer can be changed based on the writing speed to the buffer. ), The buffer capacity can be dynamically varied according to the data bandwidth, and the effect that the delay amount of data passing through the buffer can be kept substantially constant irrespective of the data speed is obtained.

According to the third aspect of the present invention, the speed conversion circuit according to the first or second aspect is mounted so that the amount of delay in the data transmission apparatus is minimized and substantially constant. In response to a connection request from a demand terminal or the like, even if the frame relay band in the band on the transmission path changes,
The effect is obtained that the delay amount in the data transmission device does not greatly fluctuate and the effect on the service and communication in the opposite terminal can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a buffer 56 according to an embodiment of the present invention.

FIG. 2 shows a data transmission device 5 equipped with the buffer 56.
FIG. 2 is a block diagram illustrating a connection relationship between a terminal 0 and related terminals.

FIG. 3 is a timing chart showing a memory address change state in a buffer 56 during low-speed processing.

FIG. 4 is a timing chart showing a memory address change state in a buffer 56 during high-speed processing.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory, 2,7 ... Register, 3,8 ... Comparator, 4 ... Write address generation counter, 5 ... Write address initialization circuit, 6 ... OR circuit, 9 ... Read address generation counter, 50 ... Data transmission device, 51 ... On-demand terminals, 52 ... Frame relay terminals, 53 ... Multiplexing / demultiplexing circuits, 54 ... Time switch circuits, 55 ... Line interfaces, 56 ... Buffers, 57 ... Frame relay clock generation circuits, 58 ... Band allocation control circuits

Continuation of front page (56) References JP-A-6-268691 (JP, A) JP-A-62-40889 (JP, A) (58) Fields studied (Int. Cl. ⁶ , DB name) H04L 13 / 08

Claims (3)

(57) [Claims] 1. A speed conversion circuit having a buffer in which transmission data is stored, wherein a delay amount from a writing start time of the buffer to a reading start time of the buffer is based on a writing speed to the buffer. A delay amount setting means for controlling write and read timings of the buffer so that the delay amount becomes substantially equal to the minimum delay amount at the maximum speed. 2. A speed conversion circuit having a buffer in which transmission data is stored, wherein an upper limit value of a write address to the buffer and an upper limit value of an address to read from the buffer are determined based on a write speed to the buffer. A speed conversion circuit comprising a buffer capacity setting means for setting. 3. A data transmission apparatus for performing data transmission on a transmission path to which a band is allocated to a frame relay terminal and an on-demand terminal having priority over the frame relay terminal, wherein a connection request transmitted from the on-demand terminal or the opposite station is provided. Based on the, based on the band information, based on the band information, the frame relay band to be allocated to the frame relay terminal and the band allocation control means for generating band information related to band allocation on the transmission path of the on-demand band to be allocated to the on-demand terminal, Speed control means for controlling the data transmission speed of the frame relay terminal, based on the data transmission speed of the frame relay terminal,
3. The speed conversion circuit according to claim 1, wherein the transmission data sent from the frame relay terminal is buffered, and the transmission data buffered in the speed conversion circuit is loaded in the frame relay band based on the connection request. A data transmission device comprising a frog multiplexing means.