JPH06152355A - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JPH06152355A JPH06152355A JP29186592A JP29186592A JPH06152355A JP H06152355 A JPH06152355 A JP H06152355A JP 29186592 A JP29186592 A JP 29186592A JP 29186592 A JP29186592 A JP 29186592A JP H06152355 A JPH06152355 A JP H06152355A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- input
- circuit board
- signal
- ringing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、回路基板に係り、さら
に詳しくは高速動作マルチチップモジュール用に適する
回路基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board, and more particularly to a circuit board suitable for a high speed multi-chip module.
【０００２】[0002]
【従来の技術】たとえば、マルチチップモジュールのシ
ングルチップ内の半導体素子への入力信号が、その出力
バッファから回路基板の配線パターンを伝搬し、他の半
導体素子の入力バッファに入力され、その出力信号がチ
ップ内回路に到達するモデルを想定すると、１つのシン
グルチップから多数のシングルチップへ信号を伝送する
とき、一般的に図５に概略を示すような回路構成が採ら
れている。すなわち、回路基板上に搭載した半導体素子
への入力信号が、その出力バッファ１から回路基板上の
配線および回路分岐部２を介して複数の半導体素子の入
力バッファ３に入力され、その出力信号がチップ内の回
路に到達する構成の、高速動作モジュールが知られてい
る。2. Description of the Related Art For example, an input signal to a semiconductor element in a single chip of a multi-chip module propagates from its output buffer through a wiring pattern of a circuit board, is input to an input buffer of another semiconductor element, and outputs its output signal. Assuming a model in which a circuit reaches an on-chip circuit, when a signal is transmitted from one single chip to a large number of single chips, a circuit configuration generally shown in FIG. 5 is generally adopted. That is, an input signal to the semiconductor element mounted on the circuit board is input from the output buffer 1 to the input buffers 3 of the plurality of semiconductor elements via the wiring on the circuit board and the circuit branching section 2, and the output signal is output. A high-speed operation module configured to reach a circuit in a chip is known.
【０００３】[0003]
【発明が解決しようとする課題】ところで、駆動する出
力バッファ１および分岐部２で分けられた分岐線（入力
バッファ）３の増加に伴い、換言すると機能・容量を大
きくすると、分岐線３による電気信号の反射が増大し
て、信号波形に電圧リンギングが発生する。たとえば図
６に模式的に示すごとく、１つの出力バッファ１に対
し、回路分岐部２を介して８個の入力バッファ３を結線
した回路構成について、入力バッファ部３にへの入力信
号の回路シュミレーションを行った結果は、図２(a) ，
(b) の曲線ａ，ｂでそれぞれ示すごとくであった。すな
わち、伝送線路の特性インピーダンスを50Ω、出力バッ
ファ１は 8mAまで駆動が可能で回路分岐部２までの伝送
線路長さ40mm、回路分岐部２からの入力バッファ３の伝
送線路長さを20mm、入力バッファ３の伝送線路間隔を20
mm、および電源電圧 (Vdd)を5.0Vと設定し、図７に示す
電圧振幅 0−5Vのパルス波を入力して、その信号波形の
推移をシミュレーションしたところ、たとえば入力バッ
ファ３の伝送線路（ライン）3aおよび伝送線路（ライ
ン）3hの場合、３周期目に相当する75nsec〜 100nsecに
おける信号波形は、図２(a) の曲線ａ（ライン3a），図
２(b) の曲線ｂ（ライン3h）に示すごとくであった。前
記曲線ａ，ｂから分かるように、信号立上がり後は信号
レベルが 5 V中心に大きく上下し、また立ち下がり後は
0 V中心に大きく上下している。さらに、信号立上がり
後の信号波形のリンギングにおける最大信号レベル
(V1 ）および最小信号レベル(V2 ）を、各入力バッファ
３の伝送線路（ライン）3a，3b，3c，3d，3e，3f，3g，
3hの入力バッファ３入力信号波形に対して求めた結果
は、図３にそれぞれ対応する伝送線路（ライン）記号で
示した。By the way, with the increase in the number of branch lines (input buffers) 3 divided by the output buffer 1 and the branch section 2 to be driven, in other words, if the function / capacity is increased, the electric power generated by the branch line 3 increases. The signal reflection increases and voltage ringing occurs in the signal waveform. For example, as schematically shown in FIG. 6, regarding a circuit configuration in which eight input buffers 3 are connected to one output buffer 1 via a circuit branching unit 2, a circuit simulation of an input signal to the input buffer unit 3 is performed. The result is shown in Fig. 2 (a),
It was as shown by the curves a and b in (b). That is, the characteristic impedance of the transmission line is 50Ω, the output buffer 1 can drive up to 8 mA, the transmission line length to the circuit branching part 2 is 40 mm, the transmission line length of the input buffer 3 from the circuit branching part 2 is 20 mm, the input Set the transmission line spacing of buffer 3 to 20
mm, and the power supply voltage (Vdd) are set to 5.0 V, a pulse wave with a voltage amplitude of 0-5 V shown in FIG. 7 is input, and the transition of the signal waveform is simulated. For example, the transmission line of the input buffer 3 ( In case of line 3a and transmission line (line) 3h, the signal waveforms in 75nsec to 100nsec corresponding to the third period are curve a (line 3a) in Fig. 2 (a) and curve b (line in Fig. 2 (b) It was as shown in 3h). As can be seen from the curves a and b, the signal level greatly rises and falls around 5 V after the signal rises, and after the fall,
It goes up and down largely at 0 V. In addition, the maximum signal level in the ringing of the signal waveform after the signal rises
(V 1 ) and the minimum signal level (V 2 ) are set to the transmission lines (lines) 3a, 3b, 3c, 3d, 3e, 3f, 3g of each input buffer 3.
The results obtained for the input buffer 3 input signal waveform of 3h are shown by the corresponding transmission line (line) symbols in FIG.
【０００４】このように、１つの出力バッファ１に対
し、回路分岐部２を介して８個の入力バッファ３を結線
した回路構成の場合、前記分岐された伝送線路（ライ
ン）では電圧リンギング幅が大きいため、たとえば高速
動作マルチチップモジュールを構成したとき、動作の不
安定化を起こし易いことを意味し、信頼性の点で実用上
問題がある。As described above, in the case of a circuit configuration in which one output buffer 1 is connected to eight input buffers 3 via the circuit branching unit 2, the branched transmission line (line) has a voltage ringing width. Since it is large, it means that instability of operation is likely to occur when a high-speed operation multi-chip module is configured, and there is a practical problem in terms of reliability.
【０００５】本発明は上記事情に対処してなされたもの
で、電圧リンギング特性を改善し、高速動作マルチチッ
プモジュールなどの構成で、安定した動作を確保するこ
とが可能な回路基板の提供を目的とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a circuit board which has improved voltage ringing characteristics and is capable of ensuring stable operation in a structure such as a high-speed operation multi-chip module. And
【０００６】[0006]
【課題を解決するための手段】本発明に係る回路基板
は、１つの出力バッファに対し、回路分岐部を介して複
数の入力バッファを結線した回路を有する回路基板にお
いて、前記回路分岐部にダミー配線を併設して、前記分
岐による入力バッファの入力信号波形のリンギングを抑
制したことを特徴とする。A circuit board according to the present invention is a circuit board having a circuit in which a plurality of input buffers are connected to one output buffer through a circuit branch portion, and a dummy is provided in the circuit branch portion. It is characterized in that wiring is provided side by side to suppress ringing of the input signal waveform of the input buffer due to the branching.
【０００７】すなわち、本発明は回路分岐部よりダミー
の配線（ダミー伝送線路）を配置（配設）することによ
って、配線（伝送線路）長さなど変更せずに、入力バッ
ファの入力信号波形（電圧）のリンギング幅を小さく
（低減）したことを骨子とする。ここで、前記ダミーの
配線は、複数の入力バッファの配線（伝送線路）の少な
くともいずれか１本に並列的に配設されるが、複数の入
力バッファの配線の最も外側に配設することが望まし
い。つまり、複数の入力バッファの配線のうち外側程、
いわゆるノイズの発生が多い傾向があり、最も外側にダ
ミー配線を配設したとき、電圧リンギングを押さえる効
果が大きいからである。また、前記ダミー配線の電流は
微少であるため、その終端を実際的に開放状態としてお
いてもよいが、たとえばコンデンサや抵抗を介して接地
した形、あるいはダミーの入力バッファを接続した形と
してもよい。That is, according to the present invention, by arranging (arranging) a dummy wiring (dummy transmission line) from the circuit branch portion, the input signal waveform ( The main point is to reduce (reduce) the ringing width of voltage. Here, the dummy wiring is arranged in parallel to at least one of the wirings (transmission lines) of the plurality of input buffers, but it may be arranged on the outermost side of the wirings of the plurality of input buffers. desirable. In other words, of the wiring of multiple input buffers,
This is because so-called noise tends to occur frequently, and when the dummy wiring is arranged on the outermost side, the effect of suppressing the voltage ringing is great. Further, since the current of the dummy wiring is very small, the end thereof may be practically left open. However, for example, it may be grounded via a capacitor or a resistor, or connected to a dummy input buffer. Good.
【０００８】[0008]
【作用】上記のごとく、回路分岐部で分岐された入力バ
ッファの配線にダミー配線を併設した構成とすることに
より、前記分岐された入力バッファの配線（伝送線路）
を伝搬される電気信号の反射が効果的に抑制ないし低減
され、信号波形における電圧リンギングの発生が大幅に
解消される。つまり、高速動作マルチチップモジュール
など構成した場合、安定した状態で電気信号の伝搬動作
に寄与するため、機能的に信頼性の高い高速動作マルチ
チップモジュールを実現し得る。As described above, the wiring of the input buffer branched at the circuit branching portion is provided with the dummy wiring, so that the wiring of the branched input buffer (transmission line) is provided.
The reflection of the electric signal propagated through the circuit is effectively suppressed or reduced, and the occurrence of voltage ringing in the signal waveform is largely eliminated. That is, when a high-speed operation multi-chip module or the like is configured, it contributes to an electric signal propagation operation in a stable state, so that a high-speed operation multi-chip module having high functional reliability can be realized.
【０００９】[0009]
【実施例】以下図１〜図４を参照して本発明の実施例を
説明する。Embodiments of the present invention will be described below with reference to FIGS.
【００１０】図１は、本発明に係る回路基板が備えた１
つの出力バッファ４に対し、回路分岐部５を介して８個
の入力バッファ６およびダミー配線７を結線した回路の
構成例を模式的に示したものである。すなわち、伝送線
路の特性インピーダンスを50Ω、出力バッファ４は 8mA
まで駆動が可能で回路分岐部５までの伝送線路長さ40m
m、回路分岐部５からの入力バッファ６の各伝送線路
（配線）6a，6b，6c，6d，6e，6f，6g，6hの長さを20m
m、入力バッファ６の各伝送線路6a，6b，6c，6d，6e，6
f，6g，6hの間隔を20mm、および入力バッファ６の伝送
線路6a，6hの外側に20mmの間隔をおいて終端に低容量
（10-5pF）コンデンサ8aを配置した全長20mmのダミー配
線7a，7bをそれぞれ結線した回路を構成している。そし
て、本発明に係る回路基板は、前記回路層を内層した
形、つまり回路層に対し絶縁層を介して電極層（グラン
ド層）を一体的に配置した積層構造を成し、かつ前記半
導体素子の出力バッファ４および入力バッファ６と前記
回路層は、前記絶縁層のスルーホールにより電気的に接
続した構成を成して高速動作マルチチップモジュール用
に供される。FIG. 1 shows a circuit board 1 according to the present invention.
1 schematically shows a configuration example of a circuit in which eight input buffers 6 and dummy wirings 7 are connected to one output buffer 4 via a circuit branching unit 5. That is, the characteristic impedance of the transmission line is 50Ω, and the output buffer 4 is 8mA.
Can be driven up to 40m in length of transmission line up to circuit branch 5
m, the length of each transmission line (wiring) 6a, 6b, 6c, 6d, 6e, 6f, 6g, 6h of the input buffer 6 from the circuit branching unit 5 is 20m
m, each transmission line 6a, 6b, 6c, 6d, 6e, 6 of the input buffer 6
A dummy wiring 7a with a total length of 20 mm, in which a low-capacitance (10 -5 pF) capacitor 8a is placed at the end of the input buffer 6 with a distance of 20 mm and a distance of 20 mm outside the transmission lines 6a, 6h of the input buffer 6. , 7b are connected to form a circuit. The circuit board according to the present invention has a form in which the circuit layer is formed as an inner layer, that is, a laminated structure in which an electrode layer (ground layer) is integrally arranged on the circuit layer via an insulating layer, and the semiconductor element The output buffer 4 and the input buffer 6 and the circuit layer are electrically connected to each other by the through hole of the insulating layer, and are used for a high-speed multi-chip module.
【００１１】前記のごとく構成した回路に、電源電圧
(Vdd)を5.0Vと設定し、図７に示す電圧振幅 0−5Vのパ
ルス波を入力して、その信号波形の推移を回路シミュレ
ーションしたところ、たとえば入力バッファ６の伝送線
路（ライン）6aおよび伝送線路（ライン）6hの場合、３
周期目に相当する75nsec〜 100nsecにおける信号波形
は、図２(a) の曲線Ａ（ライン6a），図２(b) の曲線Ｂ
（ライン6h）に示すごとくであった。前記曲線ａ，ｂ
（比較例）と曲線Ａ，Ｂから分かるように、信号立上が
り後の信号レベル、また立ち下がり後の信号レベルとも
比較例に比べて変化幅が小さくなっている。このこと
は、信号立上がり後の信号波形のリンギングにおける最
大信号レベル(V3 ）と最小信号レベル(V4 ）との幅、比
較例の場合の信号立上がり後の信号波形のリンギングに
おける最大信号レベル(V1 ）と最小信号レベル(V2 ）と
の幅の比較からも容易に分かる。The power supply voltage is applied to the circuit configured as described above.
When (Vdd) is set to 5.0V, a pulse wave having a voltage amplitude of 0-5V shown in FIG. 7 is input, and a circuit simulation of the transition of the signal waveform is performed. For example, the transmission line (line) 6a 3 for transmission line (line) 6h
The signal waveform in 75 nsec to 100 nsec corresponding to the cycle is the curve A (line 6a) in FIG. 2 (a) and the curve B in FIG. 2 (b).
It was as shown in (line 6h). The curves a and b
As can be seen from (Comparative example) and curves A and B, the range of change in the signal level after the signal rises and the signal level after the signal fall is smaller than that in the comparative example. This means that the width between the maximum signal level (V 3 ) and the minimum signal level (V 4 ) in the ringing of the signal waveform after the signal rises, the maximum signal level in the ringing of the signal waveform after the signal rise in the comparative example ( It can be easily understood from the comparison of the width between V 1 ) and the minimum signal level (V 2 ).
【００１２】さらに、信号立上がり後の信号波形のリン
ギングにおける最大信号レベル(V1）および最小信号レ
ベル(V2 ）を、各入力バッファ６の伝送線路（ライン）
6a，6b，6c，6d，6e，6f，6g，6hの入力バッファ入力信
号波形に対して求めた結果は、図３にそれぞれ対応する
伝送線路（ライン）記号で示した。図３における対比で
明らかのように、本発明に係る回路基板の場合は、一部
の入力バッファ６の伝送線路を除いて、最大信号レベル
および最小信号レベルとも、比較例の場合に比べて、前
記基準電位(5V)に近い値を示しており、特に外側の伝送
線路6a，6hの電圧リンギング幅が大幅に改善されてい
る。しかも、前記構成の本発明に係る回路基板は、出力
バッファ４に信号が入力されてから、入力バッファ６よ
り出力されるまでの時間（伝搬遅延時間）も 2.6nsec〜
3.5nsecであり、前記比較例の回路構成（図６）の伝搬
遅延時間 2.2nsec〜 3.3nsecに対比しても、機能的にほ
とんど影響ない。Further, the maximum signal level (V 1 ) and the minimum signal level (V 2 ) in the ringing of the signal waveform after the signal rises are determined by the transmission line (line) of each input buffer 6.
The results obtained for the input buffer input signal waveforms of 6a, 6b, 6c, 6d, 6e, 6f, 6g, and 6h are shown by the corresponding transmission line (line) symbols in FIG. As is clear from the comparison in FIG. 3, in the case of the circuit board according to the present invention, both the maximum signal level and the minimum signal level are higher than those in the comparative example, except for some transmission lines of the input buffer 6. The value is close to the reference potential (5V), and the voltage ringing width of the outer transmission lines 6a and 6h is greatly improved. Moreover, in the circuit board according to the present invention having the above configuration, the time (propagation delay time) from when a signal is input to the output buffer 4 to when it is output from the input buffer 6 is 2.6 nsec.
It is 3.5 nsec, and even if it is compared with the propagation delay time of 2.2 nsec to 3.3 nsec of the circuit configuration (FIG. 6) of the comparative example, there is almost no functional effect.
【００１３】なお、上記では、入力バッファ６の伝送線
路6a，6hの外側に所定の間隔をおいて終端に低容量（10
-5pF）コンデンサ8aを配置したダミー配線7a，7bをそれ
ぞれ結線した回路を構成を例示したが、たとえば図４に
回路構成の要部を示すように、終端に高抵抗（107 Ω）
の抵抗体8bを配置したダミー配線7a，7bをそれぞれ結線
した回路としてもよいし、あるいは終端を開放とした構
成であってもよい。In the above description, a low capacitance (10) is provided at the end of the input buffer 6 at a predetermined distance outside the transmission lines 6a and 6h.
-5 pF) An example of a circuit configuration is shown in which dummy wirings 7a and 7b in which capacitors 8a are arranged are connected. For example, as shown in the main part of the circuit configuration in FIG. 4, a high resistance (10 7 Ω) is applied to the termination.
The dummy wirings 7a and 7b having the resistor 8b may be connected to each other, or the termination may be opened.
【００１４】また、本発明は、前記例示の回路構成に限
定されるものでなく、たとえば出力バッファ４や入力バ
ッファ６に接続する伝送線路の長さ、これらを形成する
伝送線路の特性、分岐される入力バッファ６の数など、
目的とする機能・性能など考慮して適宜選択し得る。Further, the present invention is not limited to the above-described circuit configuration, and for example, the lengths of the transmission lines connected to the output buffer 4 and the input buffer 6, the characteristics of the transmission lines forming them, and the branching. The number of input buffers 6
It can be appropriately selected in consideration of the intended function / performance.
【００１５】[0015]
【発明の効果】上記説明から明らかのように、本発明に
係る回路基板によれば、配線長など変えずにリンギング
特性を容易に改善でき、たとえば高速動作マルチチップ
モジュールの構成に用いた場合、より安定した機能の保
持発揮に寄与する。そして、コンパクト性の保持，構成
的に煩雑を伴わないこと、機能的な信頼性の高さなどの
点から実用上多くの利点をもたらすものといえる。As is apparent from the above description, according to the circuit board of the present invention, the ringing characteristic can be easily improved without changing the wiring length and the like. Contributes to more stable function retention. It can be said that it brings many practical advantages in terms of maintaining compactness, not complicating the structure, and having high functional reliability.
【図１】本発明に係る回路基板が具備する回路の構成例
を示す模式図。FIG. 1 is a schematic diagram showing a configuration example of a circuit included in a circuit board according to the present invention.
【図２】(a) および(b) は本発明に係る回路基板例にお
ける一部の入力バッファ（伝送線路）の入力バッファ入
力信号波形を従来の回路基板の一部の入力バッファ（伝
送線路）の入力バッファ入力信号波形とそれぞれ比較し
て示す曲線図。2A and 2B are input buffer input signal waveforms of part of an input buffer (transmission line) in an example of a circuit board according to the present invention and part of an input buffer (transmission line) of a conventional circuit board; The curve diagram which compares with the input buffer input signal waveform of FIG.
【図３】本発明に係る回路基板例における各入力バッフ
ァ入力信号および従来の回路基板の各入力バッファ入力
信号について信号立上がり後の最大信号レベルと信号立
上がり後の最小信号レベルとの比較図。FIG. 3 is a comparison diagram of the maximum signal level after a signal rise and the minimum signal level after a signal rise for each input buffer input signal in the circuit board example according to the present invention and each input buffer input signal of the conventional circuit board.
【図４】本発明に係る回路基板が具備する回路の他の要
部構成例を示す回路図。FIG. 4 is a circuit diagram showing another example of the main configuration of a circuit included in the circuit board according to the present invention.
【図５】従来の回路基板が具備する回路の要部構成を示
す回路図。FIG. 5 is a circuit diagram showing a main configuration of a circuit included in a conventional circuit board.
【図６】従来の回路基板が具備する回路の構成を示す模
式図。FIG. 6 is a schematic diagram showing a configuration of a circuit included in a conventional circuit board.
【図７】回路シミュレーションにおいて入力したパルス
の波形図。FIG. 7 is a waveform diagram of pulses input in a circuit simulation.
１，４…出力バッファ ２，５…回路分岐部 ３，
６…入力バッファ3a，3b，3c，3d，3e，3f，3g，3h，6
a，6b，6c，6d，6e，6f，6g，6h…分岐された入力バッ
ファ（伝送線路） ７，7a，7b…ダミー配線 8a…
低容量コンデンサ 8b…高抵抗体1, 4 ... Output buffer 2, 5 ... Circuit branching unit 3,
6 ... Input buffers 3a, 3b, 3c, 3d, 3e, 3f, 3g, 3h, 6
a, 6b, 6c, 6d, 6e, 6f, 6g, 6h ... Branched input buffer (transmission line) 7, 7a, 7b ... Dummy wiring 8a ...
Low capacitance capacitor 8b ... High resistance
Claims (1)
を介して複数の入力バッファを結線した回路を有する回
路基板において、 前記回路分岐部にダミー配線を併設して、前記分岐によ
る入力バッファの入力信号波形のリンギングを抑制した
ことを特徴とする回路基板。1. A circuit board having a circuit in which a plurality of input buffers are connected to one output buffer via a circuit branching unit, wherein dummy wiring is provided in parallel to the circuit branching unit, A circuit board characterized by suppressing ringing of an input signal waveform.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29186592A JPH06152355A (en) | 1992-10-30 | 1992-10-30 | Circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29186592A JPH06152355A (en) | 1992-10-30 | 1992-10-30 | Circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06152355A true JPH06152355A (en) | 1994-05-31 |
Family
ID=17774435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29186592A Withdrawn JPH06152355A (en) | 1992-10-30 | 1992-10-30 | Circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06152355A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6320475B1 (en) | 1998-08-13 | 2001-11-20 | Nec Corporation | Printed circuit board suppressing ringing in signal waveforms |
-
1992
- 1992-10-30 JP JP29186592A patent/JPH06152355A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6320475B1 (en) | 1998-08-13 | 2001-11-20 | Nec Corporation | Printed circuit board suppressing ringing in signal waveforms |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20000104 |